JP2001043181A - Method for communication between microcomputers - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the reliability of a serial communication between microcomputers by suppressing the influence of an error at the time of mode switching and an error in the count value of a clock signal. SOLUTION: When a serial communication in normal mode becomes possible, a slave-side microcomputer changes a mode signal to H (b2). A master-side microcomputer sends kind information specifying the function of a serial communication in DMA mode by the serial communication in normal mode (a3). The slave-side microcomputer interprets the received kind information (b4), and makes reception preparations for the DMA mode (b5) when the information is correct and changes the mode signal to L (b6). The master-side microcomputer 11 confirms that the mode signal is at L (a5) and performs transmission and reception in DMA mode (a7).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication method between microcomputers for performing serial communication between microcomputers in an electronic device having a plurality of microcomputers (hereinafter, may be abbreviated as "microcomputer"). .

[0002]

2. Description of the Related Art Conventionally, when performing advanced control and processing using a plurality of microcomputers, data communication is performed between the microcomputers. In data communication between such microcomputers, the communication speed is high,
And high reliability is required.

Japanese Patent Application Laid-Open No. 11-66023 discloses that when data is transmitted from a main CPU on the transmission side to a sub CPU on the reception side, the correctness of command parameters is determined by the sub CPU on the reception side.
Prior art is disclosed regarding a data transmission method between CPUs that makes a judgment and notifies the main CPU on the transmission side. In the data transmission disclosed in this prior art, data is transmitted in parallel in units of 8 bits, and the receiving side transmits a busy signal when the preparation for receiving data is not completed, and the transmitting side starts transmitting data. Send out strobe signal. When the receiving side determines that there is an error in the command parameter code in the data received from the transmitting side, an error notification is performed.

Japanese Patent Application Laid-Open No. 8-44688 discloses a prior art in which data is transferred between a microcomputer and an external device using DMA (Direct Memory Access). In this prior art, F is provided between a first CPU and a second CPU.
An I / O memory is provided, and the first CPU-side DMA controller controls data transfer with the outside to the first CPU-side memory and the FIFO at the same time so as to shorten the transfer time. ing.

Japanese Patent Application Laid-Open No. 8-123774 discloses a prior art in which, when serial communication is performed between microcomputers, N bytes of data are collectively transferred in order to increase communication efficiency and reduce the load on the microcomputer. , The DMA method is also possible.

FIG. 6 shows a microcomputer TLC manufactured by Toshiba Corporation.
The outline of the serial communication function built in S9000 will be described. A clock signal line 3, a mode switching signal line 4, a serial input signal line 5, a serial output signal line 6, and a mode signal line 7 are provided between the master microcomputer 1 and the slave microcomputer 2. On the clock signal line 3, a serial communication clock signal SEICLK serving as a timing reference for serial communication is transmitted from the master microcomputer 1 to the slave microcomputer 2. On the mode switching signal line 4, a mode switching signal SEI for distinguishing between the normal serial communication mode and the DMA mode is transmitted from the master microcomputer 1 to the slave microcomputer 2.
Send RQ. On the serial input signal line 5, a serial input signal SEIIN is transmitted from the master microcomputer 1 to the slave microcomputer 2. On the serial output signal line 6, the master microcomputer 1 is connected to the slave microcomputer 2
Transmits the serial output signal SEIOUT. The mode signal line 7 transmits to the master microcomputer 1 a mode signal MODE indicating whether the serial communication mode of the slave microcomputer 2 is the normal mode or the DMA mode.

[0007]

In the communication between microcomputers as shown in FIG. 6, the number of lines connected by performing serial communication can be reduced. When communication is performed using the DMA mode, the burden on the CPU can be reduced as compared with the normal mode in which the CPU performs a program operation. However, in the DMA mode, the amount of data to be transferred, the address of the data to be transferred on the memory, and the like must be specified. Therefore, serial communication cannot be performed only in the DMA mode unless these data are fixed. . If the operating conditions in the DMA mode are specified in the communication in the normal mode, and then the mode is switched to the DMA mode, serial communication in the DMA mode can be performed flexibly. In normal mode serial communication, D
The function of the serial communication in the MA mode is specified using the type information. Therefore, in order to perform serial communication smoothly by switching from the normal mode to the DMA mode, it is necessary that the type information is correctly transmitted from the master side to the slave side.

In a conventional communication between microcomputers as shown in FIG. 6, a normal mode and a DMA mode are alternately repeated,
In the MA mode, the functions are controlled based on the type information transmitted by the serial communication in the normal mode.
If an error occurs when the type information is received on the slave side, serial communication in the DMA mode cannot be performed correctly.

In the serial communication, noise may be mixed in data transmitted one bit at a time, and the apparent number of bits may increase or the number of bits may be lost. The hardware that performs serial communication includes a serial counter that counts bit signals, and the output value of the serial counter indicates a bit position.
If the count value of the serial counter is erroneous for some reason, all subsequent serial communication data will be erroneously received.

An object of the present invention is to provide a communication method between microcomputers which can suppress an error at the time of switching between a normal mode and a DMA mode, or an error based on a counting error generated in a serial counter when receiving a serial signal. It is to be.

[0011]

According to the present invention, serial communication is always performed between a microcomputer always acting as a master side and a microcomputer always acting as a slave side. The microcomputer has a function of switching between the mode and the DMA mode, and determines the content of the serial communication in the DMA mode immediately thereafter based on the type information that is the content of the serial communication in the normal mode. In the communication method, switching from the normal mode to the DMA mode is instructed from the master microcomputer to the slave microcomputer, and the slave microcomputer outputs a mode signal indicating a mode for waiting for serial communication. Microcomputer , When detecting an error in classification information sent from the master side of the microcomputer continues the state of waiting for serial communication in the normal mode, the master microcomputer, serial communication in the normal mode, D
After transmitting the type information for switching to the MA mode,
A communication method between microcomputers, comprising receiving a mode signal from a microcomputer on a slave side and transmitting the type information again by serial communication in a normal mode when the mode signal is not switched to the DMA mode. .

According to the present invention, serial communication is performed between the microcomputer which is always the master and the microcomputer which is always the slave. Each microcomputer has a function of performing serial communication by switching between a normal mode by a program operation and a DMA mode. The serial communication in the DMA mode is determined based on the type information which is the content of the serial communication in the normal mode. Switching from the normal mode to the DMA mode is instructed from the master microcomputer to the slave microcomputer. The microcomputer on the slave side outputs a mode signal indicating a mode for waiting for serial communication. When detecting an error in the type information sent from the master microcomputer, the slave microcomputer continues to wait for serial communication in the normal mode and does not shift to the DMA mode. The master-side microcomputer receives the mode signal from the slave-side microcomputer after transmitting the type information for switching to the DMA mode by the serial communication in the normal mode, and receives the mode signal from the slave-side microcomputer.
When the mode has not been switched to the A mode, the type information is transmitted again by the serial communication in the normal mode. Only when the type information is correctly accepted by the slave microcomputer, serial communication in the DMA mode can be performed with high reliability.

Further, the present invention relates to a communication method between microcomputers which perform serial communication between a microcomputer which is always a master and a microcomputer which is always a slave, wherein the microcomputer on the slave side has no serial communication. A microcomputer which has a function of monitoring the state of the microcomputer and initializes a shift counter used for serial communication and counting the number of input bits up to a predetermined number of clocks when a state without communication continues for a predetermined time. Communication method between the two.

According to the present invention, serial communication is performed between the microcomputer which is always the master and the microcomputer which is always the slave. The slave microcomputer has a function of monitoring the state without serial communication. When the state without communication continues for a predetermined period, the microcomputer on the slave side is used for serial communication and initializes a shift counter for counting the number of input bits up to a predetermined number of clocks. If a serial signal is received after the state without communication continues, it is highly likely that the serial communication has new contents, and by initializing the shift counter, after the state without communication continues for a long time An input serial signal can be received without error.

In the present invention, the master and slave microcomputers have a function of switching serial communication between a normal mode by a program operation and a DMA mode, and are the contents of serial communication in the normal mode. The contents of the serial communication in the DMA mode performed immediately thereafter are determined based on the type information, and the switching from the normal mode to the DMA mode is instructed from the master microcomputer to the slave microcomputer, and the slave microcomputer is switched. The microcomputer outputs a mode signal indicating a mode for waiting for serial communication,
When the slave microcomputer detects an error in the type information sent from the master microcomputer, the microcomputer on the slave side continues to wait for serial communication in the normal mode. After transmitting the type information for switching to the DMA mode, a mode signal is received from the microcomputer on the slave side, and when the mode signal is not switched to the DMA mode, the type information is transmitted again by serial communication in the normal mode. It is characterized by doing.

According to the present invention, errors in performing serial communication by switching between the normal mode and the DMA mode are suppressed,
Further, serial communication can be performed while errors due to erroneous counting of the shift counter used for serial communication are minimized.

Further, in the present invention, the slave microcomputer outputs the mode signal to the serial communication signal line.

According to the present invention, before performing serial communication from the master microcomputer to the slave microcomputer, a signal indicating a mode of serial communication in the slave microcomputer is transmitted to a signal line for serial communication. Since the output is performed, the number of signal lines connecting between the master microcomputer and the slave microcomputer can be reduced. As for the mode signal, it is only necessary that the mode signal of the slave microcomputer can be read by the master microcomputer before the serial signal is output from the master microcomputer to the slave microcomputer, so the signal line for serial communication is shared. Thus, the number of signal lines can be reduced.

[0019]

FIG. 1 is a simplified diagram showing a configuration for executing a communication method according to an embodiment of the present invention. A clock signal line 13 and a mode switching signal line 1 are provided between the master microcomputer 11 and the slave microcomputer 12.
4, a serial input signal line 15, a serial output signal line 16, and a mode signal line 17 are provided, and a serial communication clock signal SEICLK, a serial communication mode switching signal SEIRQ, a serial input signal SEIIN,
Serial output signal SEIOUT and mode signal MOD
The transmission of E is the same as the conventional configuration shown in FIG.

The master microcomputer 11 has a CPU 21 for performing serial communication and other processing or control based on a preset program. Serial communication with the slave microcomputer 12 is performed via a serial I / F 22, which is an interface circuit for serial communication. Data to be transmitted / received by serial communication is stored in the memory 23. Serial communication in the DMA mode is performed by a DMA controller (hereinafter abbreviated as “DMAC”) 24. The timer 25 can measure time. Also on the slave microcomputer 12 side,
CPU 31, serial I / F 32, memory 33, DMA
C34 and a timer 35 are included.

FIG. 2 shows the serial I / Fs 22 and 32 of FIG.
The structure of the main part in is shown. Serial I / F 22, 32
A serial communication register 4 for converting the serial input signal SEIIN into 16-bit parallel data is provided therein.
0 is included. The serial communication register 40 stores the input data one bit at a time in the serial communication clock signal S.
Input in synchronization with EICLK. Shift counter 41
Counts the serial communication clock signal SEICLK,
When the counting for 16 bits is completed, the contents stored in the serial communication register 40 are transferred to the buffer register 42.
When the 16-bit counting is completed, the count value of the shift counter 41 is re-initialized to 0, and thereafter, the operation of transferring the data in the serial communication register 40 to the buffer register 42 is repeated with the completion of the 16-bit counting.

FIG. 3 shows a procedure for performing serial communication between the master microcomputer 11 and the slave microcomputer 12 in FIG. FIG. 3A shows an operation procedure of the master microcomputer 11, and FIG. 3B shows an operation procedure of the slave microcomputer 12.

The master microcomputer 11 starts the procedure from step a1. In step a2, the mode signal line 1
7, a mode signal MODE provided from the slave microcomputer 12 is monitored. The mode signal indicates that the slave microcomputer 12 can receive serial communication in the normal mode when it is at the high level H. When the mode signal MODE is L at the low level, it indicates that the slave microcomputer 12 is in a state where serial communication in the DMA mode can be received. In step a2, the mode signal line 17 is monitored until the mode signal MODE becomes high level H. Mode signal line 17
When the mode signal MODE becomes high level H, in step a3, the type information designating the DMA mode function is transmitted by the normal mode serial communication. Next, step a4
Then, data to be transmitted in the DMA mode is prepared. In step a5, the mode signal line 17 is monitored to determine whether or not the mode signal MODE is at the low level L. When it is determined that the mode signal MODE is not at the low level L, in step a6, the timer 25
Then, it is determined whether or not the time counted by the timer has timed out exceeding a preset reference time. If it is determined in step a6 that the timeout has not occurred, the process returns to step a5, and the mode signal MO
Wait for DE to go to low level L. When the mode signal MODE becomes low level L in step a5, transmission and reception in the DMA mode are performed in step a7, and the process returns to step a2.

If it is determined in step a6 that a time-out has occurred, it is determined that the type information transmitted in step a3 has not been correctly received by the slave microcomputer 12.
In step a2 and thereafter, transmission of the type information and monitoring of the mode signal line 17 for confirmation thereof are performed again.

As shown in FIG. 3B, the slave microcomputer 12 starts the procedure from step b1, and in step b2, sets the mode signal MODE to high to indicate that serial communication in the normal mode can be received. Output at level H. Next, in step b3, reception of type information from the master microcomputer 11 is performed. If the type information is
When received by the serial communication in the normal mode, step b
At 5, the information is interpreted. If it is determined that the type information is correct, at step b5, the DMA
Prepare the data. When the preparation of the DMA data is completed, the mode signal is changed to low level L in step b6,
In step b7, the DMA with the master microcomputer 11 is executed.
Serial communication is performed by transmission and reception in mode. Step b7
When the DMA transmission / reception is completed, the flow returns to step b2, and the transmission / reception in the normal mode is enabled to prepare for the next communication.

In step b3, the serial input signal line 15 is monitored to wait for reception of the type information. When the type information is not received, the reception wait is repeated until the reception is performed. After the type information is received, step b
When it is determined that there is an error in the information interpretation in step 4, the shift counter 41 is initialized in step b8,
Return to 2.

FIG. 4 shows a mode switching state when serial communication is continuously performed from the master microcomputer 11 to the slave microcomputer 12 in the present embodiment. At time t1, serial communication in the normal mode is performed with the mode signal at the high level H, and the type information is transmitted from the master microcomputer 11 to the slave microcomputer 12. Slave microcomputer 12
Can correctly interpret the type information at time t2
, The mode signal becomes low level L, and the serial communication state of the DMA mode is established. The master microcomputer 11 is a DM
DMA data is transmitted by A-mode serial communication. D
After the transmission of the MA data is completed, the slave microcomputer 1
2 performs a reception process of the received DMA data, and when the reception process is completed, at time t3, changes the mode signal MODE to a high level H, and enters a state where serial communication in the normal mode is possible.

The master microcomputer 12 transmits the type information in the normal mode serial communication for the next DMA mode serial communication. However, if the slave microcomputer 12 detects an error in the type information, the time t
At 4, the high level H is maintained without changing the mode signal MODE to the low level L capable of serial communication in the DMA mode. Therefore, the master microcomputer 12 does not perform serial communication in the DMA mode. At time t5, the timer 25 of the master-side microcomputer 11
When a timeout occurs as shown in step a6 of (a), the master microcomputer 11 transmits the type information again at time t6. On the other hand, if the slave microcomputer 12 can receive the type information without error, the mode signal MODE is changed to the low level L at which serial communication in the DMA mode can be performed at time t7. As a result, the master microcomputer 11 can transmit the DMA data by serial communication in the DMA mode.

In this embodiment, the mode signal MODE synchronizes the serial communication in the normal mode with the serial communication in the DMA mode, thereby making it possible to detect an error in the type information. Since serial communication is not performed at the timing of detecting the mode signal MODE, the serial output signal line 16 is set to the mode signal line 1.
7 can also be used. Furthermore, the serial output signal line 16 and the serial input signal line 15 can be used as a bidirectional line and can be a single line.

FIG. 5 shows another embodiment of the present invention.
An operation of initializing the shift counter 41 when a signal-free state continues for a predetermined period will be described. The procedure from step c1 to step c8 is the same as each step from step b1 to step b8 in FIG. Step c
If the type signal is not received in step 3, it is determined in step c9 whether the reception waiting time has timed out. When it is determined that the timeout has not occurred, the process returns to step c3. If it is determined in step c9 that a timeout has occurred, the shift counter is initialized in step c8, and the process returns to step c2.

In this embodiment, the master microcomputer 11 and the slave microcomputer 12 are provided with a serial communication function in the DMA mode, but only perform the normal mode serial communication without performing the DMA mode serial communication. However, the concept of the present embodiment can be similarly applied. However, the determination of the timeout in step c9 may be performed by monitoring the serial input signal line 15 and determining whether or not the non-communication state continues for a predetermined time.

[0032]

As described above, according to the present invention, between the master microcomputer and the slave microcomputer, the normal mode by the program operation and the DM mode
Serial communication can be performed while reliably switching to the A mode. When switching to the DMA mode, the type information specifying the function of performing serial communication in the DMA mode in the normal mode is transmitted from the master microcomputer to the slave microcomputer, and the type information is received without error by the slave microcomputer. Only when D
Since the switching to the MA mode is performed, efficient and highly reliable communication can be performed.

Further, according to the present invention, when the state where there is no signal continues for a predetermined period, the slave microcomputer initializes the shift counter for counting the number of input bits by using the serial communication for serial communication. Data received by communication can be received accurately without any bit displacement.

According to the present invention, the normal mode is changed to the DM mode.
It is possible to perform highly reliable communication by suppressing the effects of switching to the A mode and bit shift occurring during serial communication.

According to the present invention, the mode signal is output from the slave microcomputer before serial communication is performed on the serial signal line, so that the mode can be switched between the normal mode and the DMA mode with a small number of signal lines. It is possible to suppress the occurrence of an error in the accompanying communication.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic hardware configuration for executing a communication method between microcomputers according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a main part of an internal configuration of serial I / Fs 22 and 32 in FIG.

FIG. 3 is a flowchart showing an operation procedure of a master microcomputer 11 and a slave microcomputer 12 of FIG. 1;

FIG. 4 is a time chart showing a synchronization state and an error detection state of serial communication in the embodiment of FIG. 1;

FIG. 5 is a flowchart showing an operation procedure of the slave microcomputer 12 according to another embodiment of the present invention.

FIG. 6 is a block diagram showing a basic hardware configuration for executing a conventional communication method between microcomputers.

[Explanation of symbols]

 11 Master side microcomputer 12 Slave side microcomputer 13 Clock signal line 14 Mode switching signal line 15 Serial input signal line 16 Serial output signal line 17 Mode signal line 21, 31 CPU 22, 32 Serial I / F 23, 33 Memory 24, 34 DMAC 25, 35 timer 40 serial communication register 41 shift counter 42 buffer register

Claims (4)

[Claims] A serial communication is performed between a microcomputer that is always a master and a microcomputer that is always a slave.
Normal mode and DM for serial communication by program operation
A function is provided to switch between the A mode and the mode. Based on the type information that is the content of the serial communication in the normal mode,
In the communication method between the microcomputers in which the content of the serial communication in the DMA mode performed immediately thereafter is determined, switching from the normal mode to the DMA mode is instructed from the master microcomputer to the slave microcomputer, and the slave microcomputer is instructed. The microcomputer on the side outputs a mode signal indicating the mode in which it waits for serial communication, and the microcomputer on the slave waits for serial communication in normal mode when it detects an error in the type information sent from the microcomputer on the master. After the master microcomputer transmits the mode information from the slave microcomputer after transmitting the type information for switching to the DMA mode by serial communication in the normal mode, the master microcomputer receives the mode signal from the slave microcomputer. Switch to Is when not, the method of communication between a microcomputer and transmits the type information in the serial communication in the normal mode again. 2. A communication method between microcomputers that perform serial communication between a microcomputer that is always a master and a microcomputer that is always a slave, wherein the microcomputer on the slave side is in a state without serial communication. Communication between microcomputers having a function of monitoring and initializing a shift counter which is used for serial communication and counts the number of input bits up to a predetermined number of clocks when a state without communication continues for a predetermined time; Method. 3. The microcomputer on the master side and the microcomputer on the slave side have a function of performing serial communication by switching between a normal mode by a program operation and a DMA mode, and type information which is a content of serial communication in the normal mode. The contents of the serial communication in the DMA mode performed immediately thereafter are determined based on the above. The switching from the normal mode to the DMA mode is instructed from the master microcomputer to the slave microcomputer, and the slave microcomputer is switched. Outputs a mode signal indicating the mode in which it waits for serial communication.When the slave microcomputer detects an error in the type information sent from the master microcomputer, it continues to wait for serial communication in normal mode. Microcomputer on the master side After transmitting the type information for switching to the DMA mode in the serial communication in the normal mode, the computer receives the mode signal from the microcomputer on the slave side, and when the mode signal is not switched to the DMA mode, it re-enters. 3. The communication method between microcomputers according to claim 2, wherein the type information is transmitted by serial communication in a normal mode. 4. The communication method between microcomputers according to claim 1, wherein the slave microcomputer outputs the mode signal to the signal line for serial communication.