KR20030060253A - Method for forming bit line of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a bit line of a semiconductor device is provided to remove a concentration of stress at an STI(Shallow Trench Isolation) corner or an edge of a gate by performing a furnace annealing process after a rapid thermal annealing process. CONSTITUTION: An insulating layer having a cell transistor and a bit line contact hole is formed on a substrate. A natural oxide layer and impurities are removed from a lower portion of a contact hole. A bit line is formed by depositing a bit line barrier metal and a bit line metal layer and patterning selectively the bit line barrier metal and the bit line metal layer. A capacitor has a structure of a lower electrode/dielectric layer/upper electrode. One electrode of the cell transistor is connected to the one electrode of the cell transistor. A capacitor upper electrode is activated by a rapid thermal annealing process.

Description

Method for forming bit line of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to a method of forming a bit line of a semiconductor device in which a leakage current in a cell region can be reduced by relieving stress generated by heat treatment.

As is known, it is desirable to implement a circuit line width of 0.15 μm to 0.13 μm in an ultra-high density semiconductor memory device such as a dynamic RAM of 256 megabits (MB) or more.

In addition, in order to prevent speed delays due to finer line widths, technologies for implementing word lines and bit lines of next-generation DRAMs as metal films instead of polysilicon films have been studied.

Hereinafter, the stress by the manufacturing process and heat treatment of the semiconductor device of the prior art will be described.

1A to 1C are cross-sectional views of a process for forming a bit line of a general semiconductor device, and FIG. 2 is a stress simulation according to RTA after capacitor formation according to the prior art.

In the next-generation memory device manufacturing process using tungsten bit line, a silicon nitride film has a structure surrounding the bit line.

First, as shown in FIG. 1A, a titanium (Ti) layer 2 as a glue layer and a titanium nitride (TiN) layer 3 as a barrier metal layer are formed on an interlayer insulating film 1 such as an oxide. , A tungsten (W) layer 4, and a silicon oxynitride (SiON) layer 5 and a silicon nitride layer 6, for photolithography processes.

Subsequently, as shown in FIG. 1B, a bit line pattern is formed through photolithography and etching, and then a silicon nitride layer 7 for spacers is deposited.

As shown in FIG. 1C, the silicon nitride layer 7 is entirely dry-etched to form spacers 7a on the sidewalls of the bit line patterns, and subsequent processes such as forming the interlayer insulating layer 8 are performed.

After the bit line pattern is completed as described above, the subsequent process proceeds to the capacitor manufacturing process. In particular, when a thermal process of 800 ° C. or higher is performed in an oxygen atmosphere, oxidation of the tungsten bit line and lifting of the pattern occur. Make progress difficult

The bit line structure, which is a path for data input and output of a semiconductor device, is a polyside structure of polycrystalline silicon and tungsten silicide.

This is a limitation in the application due to the high sheet resistance value of the next-generation semiconductors that require increased device integration and high speed information processing capability.

Recently, a bit line using tungsten having a low resistance value has been used.

However, in the case of W bit lines, there are many limitations of subsequent thermal processes.

When using a high temperature furnace process in the capacitor formation process, contact resistance is reduced due to TiSi ₂ agglomeration at the bottom of the contact and migration of boron dopants to Ti or TiSi _{2 in} the P + source / drain region. This results in an increase, resulting in many constraints in subsequent thermal processes.

Therefore, in order to lower the contact resistance deposited due to the capacitor formation process, a heat treatment is performed between 800 and 900 ° C using a rapid heat treatment device after capacitor formation to lower the contact resistance by activating a dopant in a source / drain region. I'm using the method.

However, in this case, as shown in FIG. 2, stress concentration is concentrated in the shallow trench isolation (STI) corner region and the gate edge portion during rapid heat treatment.

However, the bit line forming process of the semiconductor device of the prior art has the following problems.

In the prior art, a heat treatment is performed between 800 and 900 ° C. using a rapid heat treatment apparatus after forming a capacitor to activate a dopant in a source / drain region to lower contact resistance. In this case, shallow trench isolation ) The leakage current increases due to stress concentration in the corner region and the gate edge portion, and the refresh characteristic of the semiconductor device is deteriorated.

The present invention is to solve the problem of the bit line forming process of the prior art semiconductor device, the bit line formation of the semiconductor device to reduce the leakage current in the cell region by solving the stress caused by the heat treatment It is to provide a method.

1A to 1C are cross-sectional views of a process for forming a bit line of a general semiconductor device.

Figure 2 is a stress simulation according to the RTA after the formation of the capacitor of the prior art

3 is a stress simulation according to RTA + furnace annealing after capacitor formation according to the present invention

4 is a graph comparing the stress of each device position according to the progress of each process

5 is a refresh time variation graph according to the furnace annealing process of the present invention.

According to an aspect of the present invention, there is provided a method of forming a bit line of a semiconductor device, the method including: forming an insulating layer having a cell transistor and a bit line contact hole; and removing a natural oxide layer and impurities under the contact hole, and then removing the bit line barrier. Depositing a metal layer for forming a metal and a bit line and then selectively patterning the metal layer to form a bit line; Forming a capacitor having a lower electrode / dielectric layer / upper electrode structure on the resultant bit line and having one electrode contacted to the other electrode of the cell transistor; Forming an insulating layer on the front surface is characterized in that it comprises the step of activating the capacitor upper electrode in a rapid heat treatment process.

In this case, the furnace annealing process may be further performed after the upper electrode deposition, after the upper electrode patterning, or after the deposition of the insulating layer.

Hereinafter, a method of forming a bit line of a semiconductor device according to the present invention will be described in detail.

3 is a stress simulation according to RTA + furnace annealing after capacitor formation according to the invention.

4 is a graph showing a comparison of stress for each device position according to the progress of each process, and FIG. 5 is a graph of a change in refresh time according to the addition of the furnace annealing process according to the present invention.

The present invention suppresses TiSi ₂ agglomeration in a subsequent furnace process by minimizing the thickness of Ti used as a bit line barrier metal, and activates polysilicon after poly Si is formed as an upper electrode of a capacitor. After RTA is performed for activation, heat treatment is performed for 2 hours in a furnace at 700 ~ 800 ℃ for 2 hours to relieve stress generated at this time.

In this way, the cell area leakage current due to stress relief is reduced to improve the refresh of the semiconductor device.

The configuration of the present invention is as follows.

To ensure stable bit line contact resistance, a 300: 1 BOE solution before Ti / TiN deposition is used to remove the native oxide film and other impurities present at the bottom of the contact.

Ti / TiN is then deposited to form a bit line stable contact with the Si substrate.

In particular, when Ti is thick when Ti is deposited, TiSi ₂ agglomeration may increase during a furnace annealing process to improve refresh through RTA process after forming the upper electrode of the capacitor, which is a subsequent process.

In addition, the movement of dopants in the source / drain regions to Ti or TiSi ₂ causes the increase in contact resistance due to the lack of dopants in the source / drain regions, especially in the Si and TiSi ₂ contact boundary regions. This is very important.

For this reason, the thickness of Ti deposited is limited to within 40 ~ 100Å.

Subsequently, a bit line pattern is formed through the bit line barrier metal and the W etching exposure etching process.

The capacitor is then formed through a subsequent process. After the capacitor is formed, polysilicon is deposited at 1000 ~ 2000Å to form the upper electrode, and then patterned through exposure and etching.

Subsequently, an insulating film is deposited to 3000 to 10000 Pa for insulation from subsequent metal wirings.

In order to activate polysilicon used as the upper electrode, a heat treatment is performed for 10 to 60 sec at 800 to 900 ° C. using a rapid heat treatment apparatus.

The time point of the rapid heat treatment process may be performed after the deposition of the material layer for forming the upper electrode or after the formation of the pattern of the upper electrode or after the deposition of the insulating film for insulation with the M-1 wiring to be formed later.

As described above, even after the RTA, stress is concentrated at the STI or the gate edge.

In order to eliminate this stress concentration, the furnace is heat-treated again at 700 to 800 ° C. for 20 minutes to 2 hours.

The stress change in this case is shown in FIG.

And Figure 4 shows the stress change by position according to the overall process flow.

The present invention solves the stress concentration phenomenon at the STI corner or the gate edge by carrying out the furnace annealing process to reduce the leakage current caused by the stress concentration phenomenon to improve the refresh characteristics.

In the present invention, the RTA process may be performed immediately after the deposition of polysilicon, after the formation of the upper electrode patterning, and after the deposition of the insulating film.

Subsequent furnace annealing can be done immediately after the RTA or before the metal deposition process.

As described above, the refresh result of the semiconductor device in the case where the high-temperature furnace process is added after the RTA process is as shown in FIG. 5.

As such, it can be seen that the refresh characteristics are improved by the addition of the furnace process.

Such a method of forming a bit line of a semiconductor device according to the present invention has the following effects.

The furnace annealing process is performed after the RTA process to eliminate stress concentration at the STI corners or gate edges, thereby reducing the leakage current caused by the stress concentration and improving the refresh characteristics.

This can improve the yield of the semiconductor device, there is an effect to improve the characteristics of the semiconductor device.

Claims (7)

Forming an insulating layer having a cell transistor and a bit line contact hole; Removing the native oxide film and impurities under the contact hole, depositing a bit line barrier metal and a metal layer for forming a bit line, and then selectively patterning the bit line to form a bit line; Forming a capacitor having the lower electrode / dielectric layer / upper electrode structure and having one electrode contacted to the other electrode of the cell transistor; And forming an insulating layer on the front surface and activating the capacitor upper electrode by a rapid heat treatment process. The method of claim 1, wherein the native oxide layer and impurities under the contact hole are removed using a 300: 1 BOE solution before depositing the bit line barrier metal. The bit of the semiconductor device according to claim 1, wherein the bit line barrier metal is formed by using Ti / TiN, and the thickness of Ti is limited to 40 to 100 GPa to suppress the increase in contact resistance during the furnace annealing process. Line formation method. The method of claim 1, wherein the rapid heat treatment process for activating the capacitor upper electrode is performed at 800 ° C. to 900 ° C. for 10 to 60 sec. The method of claim 1, wherein the rapid heat treatment is performed at any point after the deposition of the upper electrode forming material layer, after the pattern formation of the upper electrode, or after the deposition of the insulating film. The method of claim 1, wherein a furnace annealing process is performed after the upper electrode deposition, after the upper electrode patterning, or after the deposition of the insulating layer. The method for forming a bit line of a semiconductor device according to claim 6, wherein the furnace annealing process is performed with a heat treatment temperature of 700 to 800 ° C and a heat treatment time of 20 minutes to 2 hours.