KR100707679B1 - Method for forming salicide in semiconductor device - Google Patents

Abstract

Disclosed is a method of forming a salicide of a semiconductor device. The method includes forming an interlayer insulating film on the entire surface of a silicon semiconductor substrate on which a field oxide film, a gate oxide film, a polycrystalline silicon gate, and a source-drain diffusion region are formed, and using a photo process and an etching process to form a gate inside the interlayer insulating film. Forming a first via hole to expose and a second via hole to expose the source-drain diffusion region, and a metal reacting with silicon to form silicide on the surface of the interlayer insulating film, the inside of the first via hole, and the inside of the second via hole; Forming a metal nitride film containing the metal nitride; forming a metal silicide on the upper portion of the gate and the source-drain diffusion region by heat-treating the substrate; and forming a contact plug filling the first via hole and the second via hole. Steps.

Salicide, Diffusion Barrier, Contact Plug

Description

Method for forming salicide of semiconductor device {Method for Forming Salicide in Semiconductor Device}

1A and 1B are cross-sectional views illustrating a conventional salicide forming method.

2A and 2D are cross-sectional views illustrating a method of forming a salicide of a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a method of forming salicide for lowering sheet resistance of a gate electrode and a source-drain diffusion region in manufacturing an integrated circuit of a semiconductor device.

In semiconductor devices such as MOSFETs, the sheet resistance of thin polycrystalline silicon gates and light source-drain diffusion regions cannot all be reduced below 10-20 ohms / square, which greatly reduces their usefulness as interconnect mediators. Interconnect delay is the first to limit the speed of Very Large Scale Integration (VLSI) circuits, and as circuit size shrinks, there is a need for ways to improve these interconnections.

As a method of reducing the effective sheet resistance of the interconnect, a method of forming a silicide having a low specific resistance on silicon in the gate or source-drain region has been developed. A wide range of precious metals and refractory metals form compounds called silicon and silicide, and the sheet resistance of polycrystalline silicon and diffusion region is reduced by forming a silicide layer having a low specific resistance value on its surface. As such metals used as silicides, there are group 8 metals such as cobalt (Co), group 4 metals such as titanium (Ti), or high melting point metals such as tungsten (W). Cobalt (Co) and titanium (Ti) forming CoSi ₂ and TiSi ₂ , respectively, are widely used.

On the other hand, when the gate and the source-drain are in electrical contact through a single metal process in the manufacturing process of the semiconductor device, parasitic capacitance due to the overlap between the source-drain and the gate may be eliminated, and the metal and the source The contact area of the drain increases, resulting in a decrease in contact resistance and source-drain internal resistance. As described above, a process of simultaneously forming silicide on the gate and the source-drain region of the transistor is called a salicide process.

Since the salicide process is for making electrical contacts to the gate and source-drain, it proceeds after forming the gate and source-drain diffusion regions on the semiconductor substrate. In other words, before performing the salicide process, a process of forming a field region such as a field oxide film or swallow trench isolation (STI) for insulation between active regions of the transistor, a process of forming a polycrystalline silicon gate electrode, and ion implantation. And forming a source-drain diffusion region by heat treatment, forming a CVD oxide layer, and then forming a side oxide spacer through reactive ion etching.

Referring to Figures 1a to 1b, the conventional salicide process will be described as follows. Here, reference numeral 10 denotes a substrate, 12 denotes a source-drain diffusion region of a lightly doped drain (LDD) structure, 14 denotes a field oxide layer, 15 denotes a gate oxide layer, 16 denotes a polycrystalline silicon gate, and 18 denotes a spacer.

As described above, the salicide process proceeds after the field oxide film 14, the gate oxide film 15, the polycrystalline silicon gate electrode 16, the oxide spacer 18, the source-drain diffusion region 12, and the like are formed. That is, a transistor structure is formed on a semiconductor substrate, and then a salicide forming metal 24 such as titanium (Ti), tantalum (Ta), or cobalt (Co) is deposited on the entire surface of the substrate (FIG. 1A). The heat treatment of the substrate induces a reaction between silicon and metal in the gate electrode 16 and the source-drain diffusion region 12 to form metal silicides, respectively. During the heat treatment, the metal silicide is formed only in the region where the metal is in contact with the silicon and the polycrystalline silicon, and in other regions, silicide is not formed because the reaction between the metal and the silicon is blocked.

As described above, when silicides are simultaneously formed on the gate electrode 16 and the source-drain diffusion region 12, and the remaining metal layer is removed by selective etching that does not react with these silicides, the gate 16 and the source-drain region 12 may be removed. You will get Sally Sides 20a and 20b automatically arranged in the. This automatically ordered salicide is shown in Figure 1b. In FIG. 1B, reference numeral 20a denotes a silicide formed on the polycrystalline silicon 16 and reference numeral 20b denotes a silicide formed on the silicon of the source-drain diffusion region 12.

Meanwhile, in recent years, as the degree of integration of semiconductor devices is greatly improved, salicides are mainly formed of titanium (Ti) in semiconductor devices having a minimum critical dimension of 0.25 μm or 0.18 μm. However, as described above, in the salicide process, a process of depositing a metal layer, a heat treatment process for reacting metal and silicon, and removing a remaining unreacted metal layer must be performed.

It is an object of the present invention to provide a novel salicide process in which metal silicides are automatically aligned in polycrystalline silicon gate and source-drain diffusion regions without the need for conventional complex salicide formation processes. This aims to simplify the manufacturing process of the semiconductor device, and ultimately reduce the manufacturing cost and processing time of the semiconductor device.

The method for forming a salicide of a semiconductor device according to the present invention comprises forming an interlayer insulating film on the entire surface of a silicon semiconductor substrate on which a field oxide film, a gate oxide film, a polycrystalline silicon gate, and a source-drain diffusion region are formed, Forming a first via hole for exposing a gate and a second via hole for exposing a source-drain diffusion region in the interlayer insulating film; and forming a surface of the interlayer insulating film, a first via hole, and a second via hole. Forming a metal nitride film containing a metal that reacts with silicon to form silicide; heat treating the substrate to simultaneously form metal silicide on top of the gate and on top of the source-drain diffusion region; And forming a contact plug to fill the two via holes.

In addition, the method of forming a salicide according to the present invention may further include forming an etch stop layer on the entire surface of the substrate before forming the interlayer insulating layer, in which case the interlayer is formed in the step of forming the first via hole and the second via hole. It is preferable to sequentially etch the insulating film and the etch stop film. In particular, the contact plug may be formed of tungsten (W), in which case the metal nitride film is preferably used as a diffusion barrier for tungsten, and may be any one of a titanium nitride film, a tantalum nitride film, a tungsten nitride film, and a titanium silicon nitride film. .

Hereinafter, a method of forming a salicide of a semiconductor device according to the present invention will be described in detail with reference to FIGS. 2A to 2D.

First, before proceeding to the salicide formation process of the semiconductor device according to the present invention, the field oxide film 14, the gate oxide film 15, and the polycrystalline silicon gate 16 defining an active region on the silicon semiconductor substrate 10. And a source-drain diffusion region 12 in the silicon substrate 10. If necessary, spacers 18 that face each other may be formed on both side walls of the gate 16. However, the spacer 18 is also used for the purpose of preventing the metal silicide formed in the gate 16 and the source-drain diffusion region 12 from being short-circuited with each other through the conventional salicide process. In this case, since the metal silicides formed in the gate 16 and the source-drain diffusion region 12, respectively, do not need to be short-circuited with each other without the spacer 18, the spacer 18 is not necessarily formed. In addition, the source-drain diffusion region 12 may be formed of a lightly doped drain structure (LDD), and the spacer 18 may be formed if necessary to form the LDD structure. Since the process of forming the components constituting the transistor device listed above may be formed according to the general process of the semiconductor device, the specific process will be readily understood by those skilled in the art. .

As shown in FIG. 2A, the etch stop layer 22 and the interlayer insulating layer 24 are sequentially formed on the entire surface of the substrate 10 on which the transistor element is formed. Here, a silicon nitride film may be used as the etch stop layer 22, and since the interlayer insulating layer 24 is formed between the polycrystalline silicon and the first metal wire, a BPSG (Borophospho-Silicate Glass) material, which is a PMD (Polysilicon-Metal Dielectric) material, may be used. It is available. In FIGS. 1A and 1B, metal silicide was formed on the gate 16 and on the source-drain diffusion region 12, respectively, using the salicide process before forming the interlayer insulating layer 24. However, in the present invention, the etch stop layer 22 and the interlayer insulating layer 24 are immediately formed without passing through the salicide process. As will be described later, the salicide may be formed through a subsequent process.

Next, as shown in FIG. 2B, the first via hole 24a and the second via hole 24b are formed in the interlayer insulating film 24. Formation of the first via hole 24a and the second via hole 24b is performed through a conventional photolithography process and an etching process. When the first and second via holes are formed through an etching process, first, the interlayer insulating layer 24 is etched and the etching is stopped when the silicon nitride layer, which is the etch stop layer 22, is exposed. Thereafter, when the exposed portion of the etch stop layer 22 is removed, the polysilicon is exposed by the first via hole 24a and the surface of the silicon substrate on which the source-drain diffusion region 12 is formed by the second via hole 24b. Is exposed. By using the etch stop layer as described above, it is possible to prevent the surface of the gate 16 or the silicon substrate 10 from being damaged by the excessive etching during the etching process of the interlayer insulating film 24.

Subsequently, as shown in FIG. 2C, a metal nitride film 26 containing a metal reacting with silicon to form metal silicide is deposited on the interlayer insulating film 24 on which the first and second via holes 24a and 24b are formed. The metal nitride film 26 is deposited not only on the surface of the interlayer insulating film 24 but also on the inner walls of the first and second via holes 24a and 24b, and thus the polycrystalline silicon gate (exposed by the via holes 24a and 24b). It is evenly deposited on the surface of 16 and the surface of the silicon substrate 10 on which the source-drain diffusion regions 12 are formed.

As the metal nitride film 26, a titanium nitride film (TiN), a tantalum nitride film (TaN), a tungsten nitride film (WN), or a titanium silicon nitride film (TiSiN) may be used. Metals contained in the metal nitride film used in the present invention, that is, titanium, tungsten, tantalum, and the like react with silicon to form metal silicides such as TiSi ₂ , WSi ₂ , TaSi _2, and the like. Furthermore, the nitrogen component contained in the metal nitride film prevents the diffusion of the metal material used as the contact plug. In other words, the metal nitride film 26 is not only used as a diffusion barrier for the metal contact plug, but also as a source material for forming metal silicide in the gate 16 and the source-drain diffusion region 12, respectively, through the process described below. Used. The material of the metal nitride film is not limited to the materials listed above, and any material may be used as long as it is a metal nitride film containing a metal that reacts with silicon to form a metal silicide.

Referring to FIG. 2D, when the substrate 10 is heat-treated after the metal nitride film 26 is formed, the metal (eg, titanium, tungsten, or tantalum) contained in the metal nitride film may be formed of polycrystalline silicon on the gate 16. The metal silicides 26a and 26b are formed by reacting with the silicon on the source-drain diffusion region 12, respectively. Here, the metal silicides 26a and 26b are automatically aligned above the gate 16 and above the source-drain diffusion region 12, respectively.

On the other hand, the remaining regions of the metal nitride film 26 that do not react with silicon remain as they are and are used as the diffusion prevention film 26c of the contact plug. Conventionally, all the remaining metal layers not involved in the silicide reaction have to be removed from the metal layer for silicide formation, but such a process is unnecessary in the present invention. Therefore, the manufacturing process of a semiconductor element becomes simpler. In addition, the conventional wet etching solution using the fruit water (H ₂ O ₂ ), ammonia (NH ₄ OH) and the like to remove the metal layer, resulting in damage to the device. However, according to the present invention, there is no need to go through the wet etching process, so that damage of the device can be relatively reduced.

In particular, the metal nitride film formed on the bottom of the via holes 24a and 24b is reduced in thickness due to the silicide reaction. In the case of the titanium nitride film and the tantalum nitride film, the resistance increases as the thickness decreases. If the titanium silicon nitride film is used as the metal nitride film, the reduction of the resistance can be reduced.

Finally, the first and second via holes 24a and 24b are filled with a conductive material to form the contact plugs 28a and 28b. The contact plugs 28a and 28b are formed using CVD-W as in the conventional method. In the process of forming the contact plug, first, tungsten is deposited on the substrate 10 using CVD to sufficiently fill the via holes 24a and 24b, and then the excess tungsten formed on the interlayer insulating film 24 is subjected to chemical mechanical polishing. Remove At this time, the metal nitride film on the interlayer insulating film 24 is also removed. Thereafter, a metal wiring 30 having a desired pattern is formed on the interlayer insulating film 24. It is also preferable to interpose a diffusion barrier film 30a between the metal wiring and the interlayer insulating film, if necessary, to prevent diffusion of the metal material used as the metal wiring. Since the formation of the contact plug and the metal wiring may be performed using a conventional process for manufacturing a semiconductor device, a detailed description thereof will be omitted.

According to the present invention, since the salicide can be formed during the metal process for connecting the transistor with the metal wiring without going through the conventional salicide process, the manufacturing process of the semiconductor device can be simplified. In particular, since it is not necessary to go through the wet etching process of removing the residual metal layer after forming the salicide, it is possible to avoid the occurrence of defects due to the wet etching.

Although a preferred embodiment of the present invention has been described so far, those skilled in the art will be able to implement in a modified form without departing from the essential characteristics of the present invention. Therefore, the embodiments of the present invention described herein are to be considered in descriptive sense only and not for purposes of limitation. Should be interpreted as being included in.

Claims (4)

Forming an interlayer insulating film on the entire surface of the silicon semiconductor substrate on which the field oxide film, the gate oxide film, the polycrystalline silicon gate and the source-drain diffusion region are formed; Forming a first via hole exposing the gate and a second via hole exposing the source-drain diffusion region in the interlayer insulating layer by using a photo process and an etching process; Forming a metal nitride film containing a metal on the surface of the interlayer insulating film, inside the first via hole and inside the second via hole to form silicide by reacting with silicon; Heat treating the substrate to simultaneously form metal silicide on top of the gate and on top of the source-drain diffusion region; And forming a contact plug to fill the first via hole and the second via hole. In claim 1, Forming an etch stop layer on the entire surface of the substrate before forming the interlayer insulating film; And sequentially etching the interlayer insulating layer and the etch stop layer in the forming of the first via hole and the second via hole. The method of claim 1 or 2, And the contact plug is formed of tungsten (W), and the metal nitride film is used as a diffusion barrier for the tungsten. In claim 3, The metal nitride film is any one of a titanium nitride film, a tungsten nitride film, a tantalum nitride film and a titanium silicon nitride film.

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