KR20030058252A - Method for forming storage node contact plug - Google Patents
Method for forming storage node contact plug Download PDFInfo
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- KR20030058252A KR20030058252A KR1020010088667A KR20010088667A KR20030058252A KR 20030058252 A KR20030058252 A KR 20030058252A KR 1020010088667 A KR1020010088667 A KR 1020010088667A KR 20010088667 A KR20010088667 A KR 20010088667A KR 20030058252 A KR20030058252 A KR 20030058252A
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- storage node
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- bit line
- plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
Abstract
Description
본 발명은 DRAM의 스토리지노드 콘택 플러그 형성방법에 관한 것으로, 특히 스토리지노드 콘택홀 형성시 콘택홀 하부 개구부를 최적화하여 안정된 스토리지노드 플러그의 형성을 가능하게 하는 DRAM의 스토리지노드 콘택 플러그 형성방법에 관한 것이다.The present invention relates to a method of forming a storage node contact plug of a DRAM, and more particularly, to a method of forming a storage node contact plug of a DRAM which enables the formation of a stable storage node plug by optimizing a lower opening of a contact hole when forming a storage node contact hole. .
종래기술에 의한 DRAM의 스토리지노드 콘택 플러그 형성방법을 도1a 내지 도 1d를 참조하여 설명하면 다음과 같다.A method of forming a storage node contact plug of a DRAM according to the prior art will be described with reference to FIGS. 1A to 1D.
먼저, 도1a에 나타낸 바와 같이 반도체기판(1)상에 제1층간절연막(2)을 형성하고, 제1층간절연막(2)을 관통하여 반도체기판(1)에 연결되는 랜딩플러그(3)를 형성한 후, 랜드플러그(3)상에 제2층간절연막(4)을 형성하고, 제2층간절연막(4)상에 장벽금속층(5), 텅스텐(6)과 캡핑질화막(7)의 순서로 적층된 비트라인패턴을 형성한다.First, as shown in FIG. 1A, the first interlayer insulating film 2 is formed on the semiconductor substrate 1, and the landing plug 3 connected to the semiconductor substrate 1 is formed through the first interlayer insulating film 2. After the formation, a second interlayer insulating film 4 is formed on the land plug 3, and the barrier metal layer 5, tungsten 6, and the capping nitride film 7 are formed on the second interlayer insulating film 4. A stacked bit line pattern is formed.
이어서 도 1b에 도시된 바와 같이, 비트라인패턴을 포함한 전면에 질화막을 약 300Å두께로 증착한 후, 전면 식각하여 비트라인패턴의 양측벽에 접하는 스페이서(8)를 형성한다.Subsequently, as shown in FIG. 1B, a nitride film is deposited on the entire surface including the bit line pattern at a thickness of about 300 μs and then etched to form a spacer 8 in contact with both sidewalls of the bit line pattern.
이어서 비트라인패턴을 포함한 전면에 제3층간절연막(9)으로서 HDP산화막을 증착하고 CMP공정을 진행하여 평탄화시킨 다음, 평탄화된 제3층간절연막(9)상에 홀형 마스크(10)를 형성한다.Subsequently, an HDP oxide film is deposited as a third interlayer insulating film 9 on the entire surface including the bit line pattern, and is planarized by performing a CMP process, and then a hole mask 10 is formed on the planarized third interlayer insulating film 9.
도 1c에 도시된 바와 같이, 홀형 마스크(10)에 의해 노출된 비트라인패턴 사이의 제3층간절연막(9)을 식각한 후, 연속해서, 제3층간절연막식각(9) 후 노출되는 제2층간절연막(4)을 식각하여 랜딩플러그(3)의 표면을 노출시키는 스토리지노드콘택홀(11)을 형성한다.As shown in FIG. 1C, after etching the third interlayer insulating film 9 between the bit line patterns exposed by the hole-type mask 10, and subsequently, the second exposed interlayer 9 after the third interlayer insulating film etching 9. The interlayer insulating film 4 is etched to form a storage node contact hole 11 exposing the surface of the landing plug 3.
그리고, 홀형 마스크(10)를 제거한다.Then, the hole mask 10 is removed.
이때, 비트라인패턴의 측벽에 형성된 스페이서(8)를 질화막으로 형성함에 따라 스토리지노드 콘택홀 형성시 얼라인 마진 확보가 어려워지게 된다.At this time, since the spacer 8 formed on the sidewall of the bit line pattern is formed of a nitride film, it becomes difficult to secure the alignment margin when forming the storage node contact hole.
다음에 도1d에 나타낸 바와 같이, 상기 스토리지노드 콘택홀(11)을 포함한 제3층간절연막(9) 전면에 스토리지노드 콘택 스페이서 형성용 질화막을 증착한 후, 전면식각하여 스토리지노드 콘택홀(11)의 내부 측벽에만 질화막이 남도록 하여 스토리지노드 콘택 스페이서(12)를 형성한다. 이때, 스토리지노드 콘택홀 측면에 스토리지노드 콘택 스페이서(12)가 형성됨에 따라 스토리지노드 콘택홀 하부영역이 작아져 플러그 콘택저항 확보가 불가능하게 된다.Next, as shown in FIG. 1D, a nitride film for forming a storage node contact spacer is deposited on the entire surface of the third interlayer insulating layer 9 including the storage node contact hole 11, and then etched to the entire surface to form the storage node contact hole 11. The nitride film remains on only the inner sidewall of the substrate to form the storage node contact spacer 12. At this time, as the storage node contact spacer 12 is formed on the side of the storage node contact hole, the lower area of the storage node contact hole becomes smaller, thereby making it impossible to secure the plug contact resistance.
이어서 전면에 스토리지노드 플러그 형성용 폴리실리콘(13)을 증착한 후, 이를 에치백하여 스토리지노드 콘택홀내에 폴리실리콘(13)으로 된 스토리지노드 콘택 플러그를 형성한다.Subsequently, the polysilicon 13 for forming the storage node plug is deposited on the front surface, and then etched back to form the storage node contact plug made of the polysilicon 13 in the storage node contact hole.
상기한 바와 같은 종래기술은 DRAM이 고집적화됨에 따라 SAC(self align contact) 식각에 의해 콘택홀을 형성하는데 있어 패터닝시 오버레이 마진 확보가 어렵고, 콘택홀의 개구 면적이 작아 콘택저항 확보가 어려운 문제점이 있다.As described above, according to the conventional technology, as the DRAM is highly integrated, it is difficult to secure an overlay margin during patterning in forming a contact hole by self-aligned contact (SAC) etching, and it is difficult to secure contact resistance due to a small opening area of the contact hole.
본 발명은 상기 문제점을 해결하기 위한 것으로써, 스토리지노드 콘택홀 하부의 개구 면적을 최대화하여 콘택저항을 확보할 수 있도록 한 스토리지노드 콘택 플러그 형성방법을 제공하는데 목적이 있다.An object of the present invention is to provide a method of forming a storage node contact plug, which can secure a contact resistance by maximizing an opening area under a storage node contact hole.
도1a 내지 도1d는 종래기술에 의한 스토리지노드 콘택 플러그 형성방법을 나타낸 공정순서도.1A to 1D are process flowcharts showing a storage node contact plug forming method according to the prior art.
도2a 내지 도2f는 본 발명에 의한 스토리지노드 콘택 플러그 형성방법을 나타낸 공정순서도.2A to 2F are process flowcharts illustrating a method of forming a storage node contact plug according to the present invention;
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 반도체기판 22 : 제1층간절연막21 semiconductor substrate 22 first interlayer insulating film
23 : 랜딩플러그 24 : 제2층간절연막23: landing plug 24: second interlayer insulating film
25 : 장벽금속층 26 : 텅스텐25 barrier metal layer 26 tungsten
27 : 캡핑질화막 28 : 실링질화막27 capping nitride film 28 sealing nitride film
29 : 산화막 30 : 제3층간절연막29 oxide film 30 interlayer insulating film
33 : 스토리지노드콘택측벽스페이서 34 : 스토리지노드콘택플러그33: Storage node contact side wall spacer 34: Storage node contact plug
상기 목적을 달성하기 위한 본 발명은, 반도체기판상의 소정영역에 비트라인을 형성하는 단계와, 상기 비트라인을 포함한 기판 전면에 산화막을 증착하는 단계, 상기 산화막을 자기정렬식각하여 비트라인 측면에 비트라인 측벽 스페이서를 형성하는 단계, 상기 반도체기판 전면에 층간절연막을 형성하는 단계, 소정의 스토리지노드 콘택 마스크를 적용하여 상기 반도체기판의 소정부분이 노출되도록 상기 층간절연막을 선택적으로 식각하여 스토리지노드 콘택홀을 형성하는 단계, 상기 스토리지노드 콘택홀 내부 측벽에 스토리지노드 콘택 스페이서를 형성하는 단계 및 상기 반도체기판 전면에 스토리지노드 플러그 형성용 도전물질을 증착하고 에치백하여 상기 스토리지노드 콘택홀내에 스토리지노드 콘택 플러그를 형성하는 단계를 포함하여 구성된 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a bit line in a predetermined region on a semiconductor substrate, depositing an oxide film on the entire surface of the substrate including the bit line, and self-aligning the oxide film to bit the side of the bit line. Forming a line sidewall spacer, forming an interlayer insulating film on the entire surface of the semiconductor substrate, selectively etching the interlayer insulating film to expose a predetermined portion of the semiconductor substrate by applying a predetermined storage node contact mask, and a storage node contact hole Forming a storage node contact spacer on an inner sidewall of the storage node contact hole; depositing and etching back a conductive material for forming a storage node plug on the front surface of the semiconductor substrate, and etching back the storage node contact plug in the storage node contact hole. Form comprising forming And that is characterized.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도 2a 내지 도 2f는 본 발명에 의한 스토리지노드 콘택 플러그 형성방법을공정순서에 따라 도시하였다.2A through 2F illustrate a method of forming a storage node contact plug according to the present invention, according to a process sequence.
먼저, 도2a에 나타낸 바와 같이, 반도체기판(21)상에 제1층간절연막(22)을 형성하고, 제1층간절연막(22)을 관통하여 반도체기판(21)에 연결되는 랜딩플러그(23)를 형성한 후, 랜드플러그(23)상에 제2층간절연막(24)을 형성하고, 제2층간절연막(24)상에 장벽금속층(25), 텅스텐(26)과 캡핑질화막(27)의 순서로 적층된 비트라인패턴을 형성한다.First, as shown in FIG. 2A, a landing plug 23 is formed on the semiconductor substrate 21 and connected to the semiconductor substrate 21 through the first interlayer insulating film 22. After forming the second interlayer insulating film 24 on the land plug 23, the barrier metal layer 25, tungsten 26 and the capping nitride film 27 on the second interlayer insulating film 24 The stacked bit line patterns are formed.
이어서 도 2b에 도시된 바와 같이, 비트라인패턴을 포함한 전면에 텅스텐(26)으로 구성된 비트라인패턴의 산화를 방지하기 위해 실링(sealing) 질화막(28)을 증착한 다음, 비트라인 측벽 스페이서 형성을 위한 산화막(29)을 증착한다. 이때, 실링 질화막(28)은 약 50Å의 두께로 증착하고, 산화막(29)은 약 500Å의 두께로 증착하는 것이 바람직하다.Subsequently, as shown in FIG. 2B, a sealing nitride film 28 is deposited to prevent oxidation of the bit line pattern composed of tungsten 26 on the front surface including the bit line pattern, and then the bit line sidewall spacer formation is formed. An oxide film 29 is deposited. At this time, the sealing nitride film 28 is preferably deposited to a thickness of about 50 GPa, and the oxide film 29 is preferably deposited to a thickness of about 500 GPa.
이어서 상기 산화막(29) 및 실링질화막(28)을 자기정렬식각(SAC)하여 도2c에 나타낸 바와 같이, 비트라인 측면에 산화막스페이서(29a)를 형성한다. 이때, 상기 산화막(29) 및 실링 질화막(28)은 질화막의 선택비가 높은 조건으로 자기정렬식각하여 개구각을 향상시켜 준다.Subsequently, the oxide film 29 and the sealing nitride film 28 are self-aligned etched (SAC) to form an oxide film spacer 29a on the side of the bit line as shown in FIG. 2C. In this case, the oxide film 29 and the sealing nitride film 28 are self-aligned and etched under the condition that the selectivity of the nitride film is high, thereby improving the opening angle.
이어서 도2d에 나타낸 바와 같이 전면에 제3층간절연막(30)으로서 HDP 산화막을 증착하고 CMP공정을 진행하여 평탄화시킨 다음, 평탄화된 제3층간절연막(30)상에 홀형 마스크(31)를 형성한다.Subsequently, as shown in FIG. 2D, an HDP oxide film is deposited on the entire surface as the third interlayer insulating film 30, and is planarized by performing a CMP process, and then a hole mask 31 is formed on the planarized third interlayer insulating film 30. FIG. .
도 2e에 도시된 바와 같이, 홀형 마스크(31)에 의해 노출된 비트라인패턴사이의 제3층간절연막(30)를 식각하고, 계속해서 제2층간절연막(24)를 식각하여 랜딩플러그(23)의 표면을 노출시키는 스토리지노드콘택홀(32)을 형성한다.As shown in FIG. 2E, the third interlayer insulating film 30 between the bit line patterns exposed by the hole mask 31 is etched, and then the second interlayer insulating film 24 is etched to make the landing plug 23. The storage node contact hole 32 exposing the surface of the electrode is formed.
다음에 도2f에 나타낸 바와 같이 스토리지노드 콘택홀(32)을 포함한 제3층간절연막(30) 전면에 스토리지노드 콘택 스페이서 형성용 질화막을 증착한다. 이때, 스페이서 형성용 막으로 질화막+산화막의 이중구조도 사용할 수 있다.Next, as illustrated in FIG. 2F, a nitride film for forming a storage node contact spacer is deposited on the entire surface of the third interlayer insulating film 30 including the storage node contact hole 32. At this time, a double structure of a nitride film + an oxide film can also be used as the spacer forming film.
이어서 질화막을 전면식각하여 스토리지노드 콘택홀(32)의 내부 측벽에만 질화막이 남도록 하여 스토리지노드 콘택 스페이서(33)를 형성한다.Subsequently, the nitride layer is entirely etched so that the nitride layer remains only on the inner sidewall of the storage node contact hole 32 to form the storage node contact spacer 33.
이어서 전면에 스토리지노드 플러그 형성용 폴리실리콘을 증착한 후, 이를 에치백하여 스토리지노드 콘택홀내에 폴리실리콘으로 된 스토리지노드 콘택 플러그(34)를 형성한다.Subsequently, after depositing polysilicon for forming the storage node plug on the front surface, the polysilicon storage node contact plug 34 is formed in the storage node contact hole by etching back the polysilicon.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 기존의 SAC에 의한 식각에서는 측벽 스페이서로 질화막을 사용하는 방식이 콘택홀의 개구부 확보에 있어서 한계에 도달한 것으로 판단됨에 따라 측벽 스페이서를 2중막으로 형성하고, 스페이서 식각시 SAC를 통해 개구각을 향상시켜 줌으로써 얇은 막의 갭 매립특성을 향상시킬 수 있으며, 사진식각공정에 의한 패터닝에 있어서 오버레이 변동시 마진 확보가 가능하게 된다.According to the present invention, since the method of using the nitride film as the sidewall spacer has reached the limit for securing the opening of the contact hole in the conventional etching by the SAC, the sidewall spacer is formed as a double layer, and the opening angle through the SAC when the spacer is etched. It is possible to improve the gap filling characteristics of the thin film by improving the, and it is possible to secure a margin during overlay variation in the patterning by the photolithography process.
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