KR20030056889A - Method for fabricating capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to be capable of improving ECD(Etch Critical Dimension) profile of Pt by using a low-permittivity dielectric film. CONSTITUTION: A low-permittivity dielectric film is formed on a semiconductor substrate(1) including a conductive plug(5). A contact hole is formed in the low-permittivity dielectric film so as to define a storage node region. A storage node electrode(13) is formed in the contact hole. The low-permittivity dielectric film is then removed. A dielectric film(17) and an upper electrode(19) are sequentially formed on the storage node electrode. At the time, SiLK, flare or BCB is used as the low-permittivity dielectric film.

Description

Method for fabricating capacitor of semiconductor device

The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device using a low dielectric material in order to overcome the difficulty of etching a non-metal during capacitor manufacturing using a high dielectric material.

The capacitor capacitance in the semiconductor device is a value proportional to the dielectric constant of the dielectric between the surface area of the electrode and the storage electrode, such as C = εA / d (ε; dielectric constant, A; surface area, d; dielectric thickness).

Therefore, in the manufacturing process of a semiconductor device which is extremely miniaturized, in order to secure a certain amount or more of capacitance for proper operation of the semiconductor device, the shape of the storage electrode is formed in a 3-D structure to increase or increase the surface area of the storage electrode. A method of securing a capacitance using a high dielectric material such as BST having a dielectric constant has been studied.

However, since the complicated process is required to form the 3-D type storage electrode, there is a disadvantage in that the manufacturing cost increases and the yield decreases due to the process increase, and the use of the BST high dielectric material strictly maintains the oxygen stoichimetry. It is difficult to have a problem of deterioration of leakage current characteristics.

In addition, in the case of BST capacitors, non-metals such as Pt and Ru, which have high oxidation resistance, should be used as electrodes, and these materials are very stable, which makes the etching process very difficult, and it is difficult to obtain a vertical profile by mainly etching by sputtering. There is a problem.

In order to overcome the difficulty of etching the non-metal, the capacitor pattern is formed by using the oxide film, and then the difference in the capacitor capacity is increased by increasing the glass difference of the Pt ECD profile and the deposition rate due to the redeposition of the oxide side wall by sputtering. It is difficult to secure reliability.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, a method of manufacturing a capacitor of a semiconductor device that can ensure the reliability of the device by reducing the variation of the capacitor capacity by reducing the glass difference of the Pt ECD profile and deposition rate The purpose is to provide.

1 to 4 are cross-sectional views for each process for explaining a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.

5 to 8 are cross-sectional views of processes for describing a method of manufacturing a capacitor of a semiconductor device according to another embodiment of the present invention.

[Description of Drawing Reference]

21 semiconductor substrate 23 insulating film

25: trench 27: low dielectric constant material layer

29 capping layer 31 contact hole

33: storage node electrode 35: insulating film

37 dielectric film 39 upper electrode

According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: forming a low dielectric constant material layer on a semiconductor substrate; Forming a contact hole in the low dielectric constant material layer to define a storage node electrode region; Forming a storage node electrode in the contact hole; Removing the low dielectric constant material layer except for the storage node electrode; And forming a dielectric film and an upper electrode on the storage node electrode.

In addition, a method of manufacturing a capacitor of a semiconductor device according to the present invention comprises the steps of: forming a low dielectric constant material layer on a semiconductor substrate; Forming a contact hole in the low dielectric constant material layer to define a storage node electrode region; Forming a storage node electrode in the contact hole; And forming a dielectric film and an upper electrode on the low dielectric constant material layer including the storage node electrode.

(Example)

Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

1 to 4 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.

In the method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention, as shown in FIG. 1, first, an insulating film 3 is deposited on a semiconductor substrate 1, and then a contact mask (not shown) is formed on the semiconductor substrate 1. Is selectively removed to form a contact hole (not shown) in the insulating film 3.

Then, the conductive material is deposited on the upper surface of the entire structure including the contact hole (not shown), and then the entire surface is etched to form the contact plug 5.

Subsequently, the low dielectric constant material layer 7 and the capping insulating layer 9 are sequentially stacked on the insulating film 3 including the contact plug 5, and then the low dielectric constant material layer is formed using a storage node mask (not shown). (7) and the capping insulating film 9 are selectively patterned to form the storage node contact holes 11 in the capping insulating film 9 and the low dielectric constant material layer 7. In this case, SiLK, flare, BCB, etc. are used as the low dielectric constant material layer 7, an oxide film or SiON is used as the capping layer, and an anti reflective coating (ARC) is used when SiON is used. . Meanwhile, before forming the storage node electrode in a subsequent process, an oxide-based spacer may be formed to stabilize the interface.

Alternatively, the interface may be stabilized through e-beam curing, Ar ion curing, and UV curing before forming the storage node electrode. At this time, He, Ne, Xe, and Xr are used instead of Ar when the Ar ions are cured.

The interface may be further oxidized to an oxygen base after ion curing.

Next, as illustrated in FIG. 2, a conductive layer (not shown) and an insulating layer (not shown) for the storage node are stacked on the capping layer 9 including the storage node contact hole 11, and then etched back to the storage. The node electrode 13 is formed. At this time, as the conductive layer, any one of polysilicon, TiN, Pt, Ru, Ir, or a combination thereof may be used.

Subsequently, as shown in FIG. 3, the low oil content material layer 7 and the insulating layer 15 are dry etched.

Next, as illustrated in FIG. 4, the dielectric layer 17 and the upper electrode 19 are sequentially deposited on the upper surface of the entire structure including the storage node electrode 13 to complete a cylindrical capacitor. At this time, the upper electrode 19 may be used any one or a combination of polysilicon, TiN, Pt, Ru, Ir.

Meanwhile, in the capacitor manufacturing method of a semiconductor device according to another embodiment of the present invention, as shown in FIG. (Not shown) to selectively remove a contact hole (not shown) in the insulating film (23).

Then, the conductive material is deposited on the upper surface of the entire structure including the contact hole (not shown), and then the entire surface is etched to form the contact plug 25.

Subsequently, the low dielectric constant material layer 27 and the capping insulating layer 29 are sequentially stacked on the insulating film 23 including the contact plug 25, and then the low dielectric constant material layer is formed using a storage node mask (not shown). A storage node contact hole 31 is formed in the capping insulating layer 29 and the low dielectric constant material layer 27 by selectively patterning the 27 and the capping insulating layer 29. In this case, SiLK, flare, BCB, etc. are used as the low dielectric constant material layer 27, an oxide film or SiON is used as the capping layer, and an anti reflective coating (ARC) is used when SiON is used. In addition, when the storage node contact hole 31 is formed, the low dielectric constant material layer 270 is selectively removed using O ₂ , N _2, NH ₄ , H _2, or the like.

Alternatively, the interface may be stabilized through e-beam curing, Ar ion curing, and UV curing before forming the storage node electrode. At this time, He, Ne, Xe, and Xr are used instead of Ar when the Ar ions are cured.

The interface may be further oxidized to an oxygen base after ion curing.

Next, as illustrated in FIG. 6, a conductive layer (not shown) and an insulating layer (not shown) for the storage node are stacked on the capping layer 29 including the storage node contact hole 31 and then etched back to the storage. The node electrode 33 is formed, and the dielectric film 35 is formed on the entire product including the storage node electrode 33. In this case, as the conductive layer, any one of polysilicon, TiN, Pt, Ru, Ir, or a combination thereof may be used.

Then, as shown in FIG. 8, the dielectric film 35 and the upper electrode 37 are deposited to complete a concave capacitor. In this case, ONO, NO, TaON, Ta ₂ O ₅ , BST, PZT, SBT, and the like are used as the dielectric film 35, and among the upper electrodes 37, polysilicon, TiN, Pt, Ru, Ir, and the like. Any one or a combination thereof may be used.

As described above, the capacitor manufacturing method of the semiconductor device according to the present invention has the following effects.

According to the present invention, in order to overcome the problems of process complexity and yield reduction when forming a capacitor having a 3-D structure, and to overcome the difficulty of etching precious metals when using high dielectric materials such as BST, PZT, and SBT. A low dielectric constant material is used when forming a capacitor pattern. That is, in the present invention, when the oxide film is used to form the storage node, in the present invention, fluorine-based etching gases such as CF ₄ , CHF ₃ , C ₄ F ₈ , C ₄ F ₆ , and C ₅ F ₈ are used. Since the pattern can be formed using a fluorine-free gas such as O ₂ , N ₂ , NH ₄ or H ₂ , a nitrogen-based stop layer is unnecessary.

Therefore, the etching of the stop layer and subsequent cleaning are not necessary, which simplifies the process and thereby lowers the yield, and suppresses the formation of unnecessary parasitic capacitors. This can reduce the RC delay, which is a problem in the high integration of the device is very useful for device high integration.

On the other hand, in order to use a low dielectric constant material when forming a storage node, an appropriate curing treatment is required, and as a curing method, e-beam and ion curing (Ar, He, Ne, Xe) are used.

Dry cleaning is possible instead of wet cleaning in subsequent steps using the above method, which simplifies the process and is economical.

In addition, when used for electro-chemical deposition (ECD), which is one of the methods of forming a capacitor using a high dielectric material, an oxide film sidewall of seed Pt or Ru generated when using a conventional fluorine gas By suppressing the fence (sidewall fence) to reduce the difference in Pt ECD profile and deposition rate, it is a very useful invention to secure the reliability of the device by reducing the variation of the capacitor capacity.

On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (13)

Forming a low dielectric constant material layer on the semiconductor substrate; Forming a contact hole in the low dielectric constant material layer to define a storage node electrode region; Forming a storage node electrode in the contact hole; Removing the low dielectric constant material layer except for the storage node electrode; And forming a dielectric film and an upper electrode on the storage node electrode. The method of claim 1, wherein SiLK, flare, and BCB are used as the low dielectric constant material layer. The method of claim 1, wherein the storage node electrode is selected from polysilicon, TiN, Ru, Pt, and Ir. The method of claim 1, wherein the removing of the low dielectric constant material layer is performed by dry etching using O ₂ , N _2, NH ₄ , and H ₂ . The method of claim 1, further comprising forming an oxide-based spacer for stabilizing an interface before forming the storage node electrode. The method of claim 1, wherein the interface is stabilized by e-beam curing, Ar ion curing, and UV curing before forming the storage node electrode. The method of manufacturing a capacitor of a semiconductor device according to claim 6, wherein He, Ne, Xe, and Xr are used instead of Ar when the Ar ions are cured. The method of manufacturing a capacitor of a semiconductor device according to claim 6, wherein the interface is oxidized to an oxygen base after ion curing. The method of claim 1, further comprising performing dry cleaning using a hydrogen vacuum after removing the low dielectric constant material layer. Forming a low dielectric constant material layer on the semiconductor substrate; Forming a contact hole in the low dielectric constant material layer to define a storage node electrode region; Forming a storage node electrode in the contact hole; And And forming a dielectric film and an upper electrode on the low dielectric constant material layer including the storage node electrode. The method of claim 10, wherein SiLK, flare, and BCB are used as the low dielectric constant material layer. The method of claim 10, wherein the removing of the low dielectric constant material layer is performed by dry etching using O ₂ , N _2, NH ₄ , and H ₂ . The method of claim 10, further comprising forming an oxide-based spacer for stabilizing the interface before forming the storage node electrode, or stabilizing the interface through e-beam curing, Ar ion curing, or UV curing. And oxidizing the interface with an oxygen base after the ion hardening.