KR20030056842A - method for fabricating capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to be capable of improving leakage current by effectively reducing carbon content in a dielectric film using two-step annealing. CONSTITUTION: An interlayer dielectric(10) having a contact plug(11) is formed on a substrate. The sacrificial insulating layer(13) having the second contact hole is formed to expose the contact plug(11). A lower electrode(17) is formed in the second contact hole. A dielectric film(18) is formed on the lower electrode(17). The resultant structure is firstly annealed by plasma and secondly annealed by a furnace. Then, an upper electrode is formed on the dielectric film.

Description

Method for fabricating capacitor of semiconductor device

The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a capacitor of the semiconductor device.

In general, the problem of efficiently reducing the area of the capacitor, that is, the capacitor to store information charges due to the high integration of semiconductor devices, has been raised, but the reduction of the area occupied by the capacitor is necessary to secure sufficient capacitance to maintain the stored information. In order to maintain the information charges due to noise and soft errors caused by α-particles, an appropriate capacitor capacitance must be secured regardless of the reduction of the memory element (capacitor).

To realize this, thinning of the capacitor dielectric film such as C = (εAs) / d (ε: dielectric constant, As: surface area, d: dielectric thickness) minimizes the distance between electrodes (d), and the capacitor structure is planar stack, In order to increase the surface area As by changing to a three-dimensional structure such as a cup (concave) or a cylinder.

However, due to the ultra-fine semiconductor process, reduction through capacitor structural improvement has reached the limit of the process, and further reduction is impossible. The need for high dielectric film development such as PZTO (Pb Zr TiO3: Lead Zirconium Titanium Oxide) has emerged.

In the case of using Ta2O5 as the dielectric film, the aspect ratio is increased in the capacitor structure according to the reduction of the design rule, and the step coverage characteristic is important.

As such, Ta2O5 must be deposited at a low temperature to improve the step coverage characteristics.

However, when Ta2O5 is deposited at a low temperature, the carbon content is increased. Conventionally, in order to improve the carbon content, RTO, RTN, or low temperature plasma annealing process is performed by post-heat treatment. There is also a limit in improving the deterioration of the leakage current characteristic of the capacitor.

The capacitor of the conventional semiconductor device as described above has the following problems.

When the dielectric film is formed of Ta 2 O 5, there is a limit in reducing the carbon content, and thus there is a limit in improving leakage current characteristics.

Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device suitable for improving leakage current characteristics by effectively reducing the carbon content in the capacitor dielectric film.

1A to 1I are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.

2A and 2B are graphs showing the mass distribution according to the temperature of carbon present in the Ta 2 O 5 film.

3 is a graph showing the crystal orientation when the Ta 2 O 5 film is post-heat treated in an N 2 O atmosphere.

Explanation of symbols on the main parts of the drawings

10: interlayer insulating film 11: contact plug

12: etching stop layer 13: sacrificial insulating film

14 contact hole 15 first polysilicon layer

16: second polysilicon layer 17: capacitor lower electrode

18 capacitor dielectric film 19 capacitor upper electrode

The capacitor manufacturing method of the semiconductor device of the present invention for achieving the above object is a step of forming an interlayer insulating film having a first contact hole in the substrate, a step of forming a contact plug in the first contact hole, the contact plug is exposed Forming a sacrificial insulating film having a second contact hole so as to form a capacitor lower electrode along the surface of the second contact hole, forming a capacitor dielectric film on the capacitor lower electrode, successively 1 in two steps. And performing a secondary plasma heat treatment and a secondary furnace heat treatment, and forming a capacitor upper electrode on the capacitor dielectric layer.

Hereinafter, a capacitor manufacturing method of a semiconductor device of the present invention will be described with reference to the accompanying drawings.

1A to 1I are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.

2A and 2B are graphs showing the mass distribution according to the temperature of carbon present in the Ta 2 O 5 film, and FIG. 3 is a graph showing the crystal orientation when the Ta 2 O 5 film is post-heat treated in an N 2 O atmosphere.

The present invention relates to a method of effectively post-heating a Ta2O5 thin film deposited on a capacitor having a high aspect ratio and deposited on a three-dimensional capacitor such as a cup or a concave.

In the method of manufacturing a capacitor of a semiconductor device according to the present invention, as shown in FIG. 1A, a contact plug formed of polysilicon in a contact hole is formed after forming an interlayer insulating film 10 having a contact hole in an impurity diffusion region of a silicon substrate. (11) is formed. In this case, the impurity diffusion region means a source region of a transistor having a source region, a drain region, and a gate electrode.

Subsequently, as shown in FIG. 1B, a nitride film is deposited on the interlayer insulating film 10 so as to be in contact with the contact plug 11 so as to serve as a stop layer during oxidation prevention and subsequent etching process of the contact plug. Form layer 12.

As shown in FIG. 1C, a sacrificial insulating film 13 is deposited on the etch stop layer 12 using an oxide film.

At this time, the height of the sacrificial insulating layer 13 determines the height of the capacitor lower electrode.

As shown in FIG. 1D, the sacrificial insulating layer 13 and the etch stop layer 12 are etched to expose the contact plug 11 and the interlayer insulating layer 10 adjacent thereto so as to form the capacitor lower electrode by the dry etching process. The hole 14 is formed.

Thereafter, as illustrated in FIG. 1E, the first polysilicon layer 15 for forming the capacitor lower electrode is deposited on the contact hole 14 and the sacrificial insulating layer 13 adjacent thereto.

As shown in FIG. 1F, a second polysilicon layer 16 having a rough surface is formed on the polysilicon layer 15.

Thereafter, as illustrated in FIG. 1G, the second and first polysilicon layers 16 and 15 are polished or etched by a chemical mechanical polishing process or an etch back process to form the capacitor lower electrode 17 in the contact hole 14. do.

The capacitor lower electrode 17 may also be formed of TiN, Ru, or RuO2.

Next, as shown in FIG. 1H, the capacitor dielectric film 18 is formed on the sacrificial insulating film 13 including the capacitor lower electrode 17.

The capacitor dielectric layer 18 may be formed using Ta 2 O 5, Barium Strontium Titanium Oxide (BSTO), Strontium Titanium Oxide (STO), or PZTO (Pb Zr TiO 3: Lead Zirconium Titanium Oxide). Is formed by Ta2O5 deposition at 250 ~ 450 ℃ using O2, N2O or O2 + N2O gas using Ta (OEt) 5 [Ta (OC2H5) 5] source by MOCVD (Metal Organic Chemical Vapor Deposition) method. do.

Subsequently, the post-heat treatment is performed in two-step, and the first heat treatment forms a plasma in the RF power range of 100 to 700 W in an O 2 or N 2 O atmosphere at 350 to 450 ° C. to remove carbon in the capacitor dielectric film 18 composed of Ta 2 O 5. Secondary heat treatment is Furnace in oxidizing atmosphere using O2, N2O or O2 + N2O gas at 600 ~ 800 ℃ for Ta2O5 crystallization, Oxygen vacancy removal, Stoichiometry control To proceed.

Next, the capacitor upper electrode 19 is formed on the capacitor dielectric film 18 as shown in FIG. 1I.

At this time, the capacitor upper electrode 19 uses a polysilicon layer, TiN, W, Ru, RuO2, TiN / polysilicon layer or Ru / TiN / polysilicon layer.

Next, the thermal behavior of carbon will be described with reference to the drawings in order to remove carbon in the Ta 2 O 5 film more efficiently.

Thermal behavior of carbon in the Ta2O5 film deposited at low temperature was observed by TDS (Thermal Desorption Spectroscopy), as shown in FIG. 2a. ) Is suddenly increased and detached.

The post-heat treatment method of the Ta2O5 film is performed in two steps, which will be described in more detail as follows.

In the first step, as seen in the thermal behavior of carbon in the Ta2O5 film, carbon is desorbed in the form of CO and CO2 bonds in the 350 to 450 ° C section. In the oxidizing atmosphere using N2O gas, RF power is applied in the range of 100 to 700W to form a plasma to minimize the amount of carbon in the Ta2O5 film as much as possible.

The second step is the Furnace in the oxidizing atmosphere using N2O gas at 600 ~ 800 ℃ for removing crystallization oxygen vacancy and controlling stoichiometry of Ta2O5 film after the first heat treatment as described above. As shown in FIG. 3, when the heat treatment is performed for 60 minutes in a furnace in an N 2 O atmosphere, the Ta 2 O 5 film is crystallized with a preferred orientation in the (200) crystal direction.

As described above, the Ta2O5 material may be continuously used in the next-generation device after 256MDRAM by forming the capacitor dielectric film composed of Ta2O5 and performing the heat treatment process twice.

The capacitor manufacturing method of the semiconductor device of the present invention as described above has the following effects.

After the capacitor dielectric film is formed using Ta2O5, a two-step heat treatment process is performed to improve the quality of the Ta2O5 film, thereby improving leakage current characteristics of the capacitor.

Claims (7)

Forming an interlayer insulating film having a first contact hole in the substrate, Forming a contact plug in the first contact hole; Forming a sacrificial insulating film having a second contact hole so that the contact plug is exposed; Forming a capacitor lower electrode along the surface of the second contact hole; Forming a capacitor dielectric film on the capacitor lower electrode, The first plasma heat treatment and the second furnace heat treatment in a two-step continuous, And forming a capacitor upper electrode on the capacitor dielectric layer. The semiconductor device of claim 1, wherein the capacitor dielectric layer is formed using Ta 2 O 5, Barium Strontium Titanium Oxide (BSTO), Strontium Titanium Oxide (STO), or Pb Zr TiO 3: Lead Zirconium Titanium Oxide (PZTO). Capacitor manufacturing method. The method of claim 2, wherein when the capacitor dielectric layer is formed of a Ta 2 O 5 layer, the capacitor dielectric layer is deposited using O 2, N 2 O, or O 2 + N 2 O gas at 250 ° C. to 450 ° C. 4. The semiconductor according to claim 1, wherein the first heat treatment in the two-step heat treatment is performed such that RF power is in the range of 100 to 700 W, and O2, N2O or O2 + N2O is injected at 350 to 450 ° C. Method for manufacturing a capacitor of the device. The method of claim 1, wherein the secondary heat treatment in the two-step heat treatment is performed by injecting O 2, N 2 O, or O 2 + N 2 O in a 600 to 800 ° C. interval. The method of claim 1, wherein the capacitor lower electrode is formed of a TiN, Ru, RuO 2, or a polysilicon layer / rough surface polysilicon layer. The method of claim 1, wherein the capacitor upper electrode is formed of a TiN, Ru, RuO 2, TiN / polysilicon layer, or a Ru / TiN / polysilicon layer.