KR20000041395A - Method for manufacturing capacitor of memory device - Google Patents

Method for manufacturing capacitor of memory device Download PDF

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Publication number
KR20000041395A
KR20000041395A KR1019980057254A KR19980057254A KR20000041395A KR 20000041395 A KR20000041395 A KR 20000041395A KR 1019980057254 A KR1019980057254 A KR 1019980057254A KR 19980057254 A KR19980057254 A KR 19980057254A KR 20000041395 A KR20000041395 A KR 20000041395A
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oxide film
tantalum oxide
forming
capacitor
nitride layer
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KR1019980057254A
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Korean (ko)
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김경민
오경석
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김영환
현대전자산업 주식회사
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Publication of KR20000041395A publication Critical patent/KR20000041395A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes

Abstract

PURPOSE: A capacitor manufacturing of a memory device is to degrease a leakage current by protecting a Ta2O5 thin film from chlorin gas in depositing a TiN thin film. CONSTITUTION: A method for manufacturing a capacitor of memory device comprise the steps of: depositing a polysilicon layer(101) as a lower electrode; forming a first nitride layer(102) on the polysilicon layer by performing a first rapid thermal nitration treatment; forming a Ta2O5 film(103) on the fist nitride layer; forming a second nitride layer(104) on the Ta2O5 film by performing a second rapid thermal nitration treatment; and forming a TiN layer(105) as an upper electrode on the second nitride layer. The second rapid thermal nitration treatment is performed for 10-60 second at temperature of 600-800 degrees by using gas including nitrogen.

Description

메모리소자의 커패시터 제조 방법Capacitor Manufacturing Method of Memory Device

본 발명은 반도체 메모리 소자에 관한 것으로, 특히 Ta2O5를 유전체로 사용하는 고집적 메모리 소자의 커패시터(capacitor) 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a method of manufacturing a capacitor of a highly integrated memory device using Ta 2 O 5 as a dielectric.

현재 반도체 메모리소자는 크게 리드/라이트(read/write) 메모리와 리드전용메모리(ROM)로 구분할 수 있다. 특히 리드/라이트 메모리는 다이나믹램(Dynamic RAM, 이하 DRAM이라 칭함)과 스태틱램(static RAM)으로 나뉘어진다. DRAM은 1개의 트랜지스터(transistor)와 1개의 커패시터로 1개의 단위 셀(unit cell)이 구성되어 집적도에서 가장 앞서고 있는 소자이다.Currently, semiconductor memory devices can be classified into read / write memory and read-only memory (ROM). In particular, the read / write memory is divided into a dynamic RAM (hereinafter referred to as DRAM) and a static RAM. DRAM is one of the most advanced devices in terms of integration density because one unit cell consists of one transistor and one capacitor.

한편, 고집적화의 진전으로 3년에 메모리의 용량이 4배씩 증가되어 현재에는 256Mb(mega bit) DRAM 및 1Gb(giga bit)에 대한 연구에 많은 진전을 보이고 있다. 이와 같이 DRAM의 집적도가 높아질수록 전기 신호를 읽고 기록하는 역할을 하는 셀의 면적은 256Mb의 경우 0.5 μm2 이고, 셀의 기본 구성요소중의 하나인 커패시터의 면적은 0.3 μm2 이하로 작아져야 한다. 이러한 이유로 256Mb 급 이상의 고집적 소자에서는 종래의 반도체 공정에서 사용되는 기술이 한계를 보이기 시작하고 있다.On the other hand, due to the progress of high integration, the capacity of the memory has been increased by four times in three years, and now it is showing a lot of progress in the research on 256Mb (mega bit) DRAM and 1Gb (giga bit). As the density of DRAM increases, the area of a cell that reads and writes an electrical signal is 0.5 in 256Mb. μm 2 One of the basic components of the cell, the area of the capacitor is 0.3 μm 2 Should be smaller than For this reason, the techniques used in the semiconductor process of the 256Mb or higher integrated devices are starting to show a limit.

즉, 64Mb DRAM에서 지금까지 사용되어 온 유전재료인 SiO2/Si3N4등을 사용하여 커패시터를 제조할 경우 필요한 커패시턴스를 확보하기 위해서는 박막의 두께를 최대한 얇게 하더라도 커패시터가 차지하는 면적은 셀 면적의 6배가 넘어야 한다. 이러한 이유로 커패시터를 평탄한 형태로는 이용할 수 없음으로 단면적을 다른 방법으로 늘려야 한다. 단면적을 늘이기 위해서, 즉 커패시터의 스토리지노드 표면적을 증가시키기 위해서 사용되는 기술은, 스택 커패시터구조 또는 트렌치형 커패시터 구조 또는 반구형 폴리실리콘막을 사용하는 기술 등 여러 가지 기술이 제안된바 있다.In other words, in order to obtain the required capacitance when manufacturing a capacitor using SiO 2 / Si 3 N 4 , a dielectric material that has been used in 64 Mb DRAM, the area occupied by the capacitor should be as small as possible. It should be over six times. For this reason, capacitors are not available in flat form, so the cross-sectional area must be increased in other ways. As a technique used to increase the cross-sectional area, that is, increase the storage node surface area of a capacitor, various techniques have been proposed, such as a stack capacitor structure, a trench capacitor structure, or a technique using a hemispherical polysilicon film.

그러나, 256Mb급 이상의 소자에서는 유전율이 낮은 SiO2/Si3N4계 유전물질로는 커패시턴스를 늘이기 위해 더 이상 두께를 줄일 수도 없고, 커패시터의 단면적을 늘이기 위해 그 구조를 더 복잡하게 만드는 경우 공정과정이 너무 복잡하여 제조단가의 상승과 수율이 떨어지는 등의 문제점이 많다. 그러므로 커패시터를 3차원적 입체구조로 형성하여서 커패시터의 단면적을 증가시켜 저장정전용량을 충족시키는 방법은 64Mb급 이상의 DRAM에 적용시키기에는 매우 어렵다.However, in devices above 256Mb, low dielectric constant SiO 2 / Si 3 N 4 -based dielectrics can no longer reduce the thickness to increase the capacitance, and make the structure more complex to increase the cross-sectional area of the capacitor. This is too complicated, and there are many problems such as an increase in manufacturing cost and a drop in yield. Therefore, the method of forming the capacitor in three-dimensional solid structure to increase the cross-sectional area of the capacitor to meet the storage capacitance is very difficult to be applied to DRAM of 64Mb or more.

이와 같은 문제점을 해결하기 위해서, SiO2/Si3N4계 유전체를 대체할 목적으로 Ta2O5유전박막에 대한 연구가 진행되었지만, 커패시턴스가 SiO2/Si3N4계에 비해서 2-3배에 지나지 않아서 이를 DRAM에 적용하기 위해서는 유전박막의 두께를 줄여야 하는데, 이로 인하여 누설 전류가 증가되는 등 Ta2O5유전박막을 실용화하기에는 많은 문제점이 따른다. 따라서, 종래에는 폴리실리콘 하부전극 상에 Ta2O5유전박막을 형성하고 상부 전극으로 폴리실리콘대신 TiN 또는 TiN/폴리실리콘을 사용하는 것이 일반화되어 있다.To solve this problem, Ta 2 O 5 dielectric thin film has been studied for the purpose of replacing SiO 2 / Si 3 N 4 based dielectrics, but the capacitance is 2-3 compared to SiO 2 / Si 3 N 4 based In order to apply this to DRAM, it is necessary to reduce the thickness of the dielectric thin film, which increases the leakage current. Therefore, there are many problems in practical application of the Ta 2 O 5 dielectric thin film. Therefore, it is common to form a Ta 2 O 5 dielectric thin film on a polysilicon lower electrode and to use TiN or TiN / polysilicon instead of polysilicon as the upper electrode.

그러나 TiN 증착시 사용되는 TiCl4개스는 Ti와 Cl로 분해되면서 클로린(Chlorin) 개스를 발생시켜 Ta2O5박막에 데미지(Damage)를 주어 전기적 특성에 영향을 주고 있다.However, TiCl 4 gas used in TiN deposition is decomposed into Ti and Cl to generate chlorine gas, thereby damaging the Ta 2 O 5 thin film to affect the electrical properties.

본 발명은 상기 종래기술의 문제점을 해결하기 위하여 안출된 것으로서, TiN 박막을 증착할 때의 클로린 개스로부터 Ta2O5박막을 보호하여 누설전류를 감소시키기 위한 메모리소자의 커패시터 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, and provides a method of manufacturing a capacitor of a memory device for reducing the leakage current by protecting the Ta 2 O 5 thin film from chlorine gas when depositing a TiN thin film. There is a purpose.

도1a 내지 도1d는 본 발명의 일실시예에 따른 커패시터 제조방법을 나타내는 공정 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor in accordance with an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

101 : 폴리실리콘층 102, 104 : RTN에 의한 질화층101: polysilicon layer 102, 104: nitride layer by RTN

103 : 탄탈늄산화막 105 : TiN층103: tantalum oxide film 105: TiN layer

상기 목적을 달성하기 위한 본 발명은 메모리소자의 커패시터 제조방법에 있어서, 하부전극으로서 폴리실리콘층을 증착하는 단계; 제1열적급속질화 처리하여 상기 폴리실리콘층 상에 제1질화층을 형성하는 단계; 상기 질화층 상에 탄탈늄산화막을 형성하는 단계; 제2열적급속질화 처리하여 상기 탄탈늄산화막 상에 제2질화층을 형성하는 단계; 및 상기 질화층 상에 상부전극으로서 티타늄나이트라이드층을 형성하는 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method of manufacturing a capacitor of a memory device, the method comprising: depositing a polysilicon layer as a lower electrode; Forming a first nitride layer on the polysilicon layer by first thermal rapid nitriding; Forming a tantalum oxide film on the nitride layer; Forming a second nitride layer on the tantalum oxide film by performing a second thermal rapid nitriding treatment; And forming a titanium nitride layer as an upper electrode on the nitride layer.

바람직하게, 상기 제2열적급속열처리는 질소를 포함하는 개스를 사용하여 600∼800℃에서 10∼60sec 동안 실시함을 특징으로 한다.Preferably, the second thermal rapid heat treatment is performed for 10 to 60 sec at 600 to 800 ° C. using a gas containing nitrogen.

상술한 바와 같은 특징적인 구성을 갖는 본 발명은, TiN 증착 전 RTN(Rapid Thermal Nitration)처리하여 Ta2O5박막 표면에 얇은 질화층을 형성하므로 클로린(Chlorin) 개스에 의한 Ta2O5박막을 보호하여 누설전류를 감소시키는 작용효과를 갖는다.The present invention having the characteristics as described above forms a thin nitride layer on the surface of the Ta 2 O 5 thin film by RTN (Rapid Thermal Nitration) treatment before TiN deposition, thereby forming a Ta 2 O 5 thin film by Chlorin gas. It has the effect of reducing leakage current by protecting.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도1a 내지 도1d는 본 발명의 일실시예에 따른 커패시터 제조방법을 나타낸다.1A to 1D show a capacitor manufacturing method according to an embodiment of the present invention.

먼저, 도1a를 참조하면, 커패시터의 하부전극으로서 폴리실리콘층(101)을 증착한 다음, 폴리실리콘층(101) 표면을 HF나 BOE(buffer oxide etchant)로 세정하여 폴리실리콘층 표면에 발생된 자연산화막(native oxide)을 제거한다. 이어서, 상기 폴리실리콘층을 800∼950℃에서 열적급속질화(RTN : Rapid Thermal Nitration) 처리하여 폴리실리콘층 표면에 얇은 질화층(102)을 형성한다. 이 질화층(102)은 후속 공정에서 산소분위기의 열처리시 폴리실리콘층 표면에 SiO2막이 형성되는 것을 억제하여 준다.First, referring to FIG. 1A, a polysilicon layer 101 is deposited as a lower electrode of a capacitor, and then the surface of the polysilicon layer 101 is cleaned by HF or BOE (buffer oxide etchant) to generate the polysilicon layer. Remove native oxide. Subsequently, the polysilicon layer is subjected to rapid thermal nitration (RTN) at 800 to 950 ° C. to form a thin nitride layer 102 on the surface of the polysilicon layer. The nitride layer 102 suppresses the formation of SiO 2 film on the surface of the polysilicon layer during the heat treatment of the oxygen atmosphere in a subsequent process.

이어서, 도1b를 참조하면, 탄탈륨 에칠레이트(Ta(OC2H5)5)를 170∼190℃의 기화기에서 기상 상태로 만들고, 이 기화된 탄탈륨 에칠레이트 소오스(Source) 가스의 양을 0.01∼2cc로 하고, 반응 개스 O2의 양을 10∼1000sccm 정도로 사용하여 저압화학기상증착(LPCVD) 방법으로 탄탈늄산화막(Ta2O5)(103)을 형성한다. 이때, LPCVD 반응로의 압력은 0.1∼1.2Torr로 유지하고 기판의 온도를 350∼450℃로 유지한다.Subsequently, referring to FIG. 1B, tantalum acrylate (Ta (OC 2 H 5 ) 5 ) is brought into a gaseous state in a vaporizer at 170 to 190 ° C., and the amount of the vaporized tantalum acrylate source (0.01) is 0.01 to A tantalum oxide film (Ta 2 O 5 ) 103 is formed by low pressure chemical vapor deposition (LPCVD) using 2 cc of the reaction gas O 2 in an amount of about 10 to 1000 sccm. At this time, the pressure of the LPCVD reactor is maintained at 0.1 ~ 1.2 Torr and the temperature of the substrate is maintained at 350 ~ 450 ℃.

이어서, 후속 열공정으로, 기판 온도 300∼500℃ 및 RF 파워 50∼400Watt에서 N2O 플라즈마 어닐링을 실시하여 박막내에 존재하는 불순물을 제거하고, 750∼900℃에서 30∼60분 동안 O2또는 N2O 퍼니스(Furnace) 어닐링을 실시하여 증착된 탄탈늄산화막(103)을 결정화한다.Subsequently, in a subsequent thermal process, N 2 O plasma annealing is performed at a substrate temperature of 300 to 500 ° C. and an RF power of 50 to 400 Watts to remove impurities present in the thin film, and O 2 or 30 to 60 minutes at 750 to 900 ° C. An N 2 O furnace (annealed) furnace is annealed to crystallize the deposited tantalum oxide film 103.

이어서, 도1c를 참조하면, 상부전극으로서 TiN을 증착하기 전에, 탄탈늄산화막(103)에 영향을 주는 Cl 개스에 의한 영향을 줄이기 위해서, NH3개스를 1∼5slm 사용하여 600∼800℃에서 10∼60sec 동안 열적급속질화(RTN : Rapid Thermal Nitration) 처리하므로써 탄탈늄산화막(103) 상에 얇은 질화막(104)을 형성한다.Next, referring to FIG. 1C, before deposition of TiN as the upper electrode, NH 3 gas is used at 1 to 5 slm at 600 to 800 ° C. in order to reduce the effect of Cl gas affecting the tantalum oxide film 103. A thin nitride film 104 is formed on the tantalum oxide film 103 by a rapid thermal nitration (RTN) treatment for 10 to 60 sec.

이어서, 도1d와 같이 상부전극으로서 TiN층(105)을 형성한다. 상기 TiN층(105)은 TiCl4개스를 소오스 개스로하여 400∼750℃, 0.1∼2 Torr에서 증착한다. Cl 개스에 의한 영향을 보다 효과적으로 줄이기 위해서는 TiN을 2단계로 증착하고 중간 중간에서 NH3개스에 플라즈마를 여기시켜 Cl 개스를 제거할 수 있다. 그리고 상부전극용으로 상기 TiN층 상에 폴리실리콘막을 더 형성할 수 있다.Subsequently, a TiN layer 105 is formed as an upper electrode as shown in FIG. 1D. The TiN layer 105 is deposited at 400 to 750 DEG C and 0.1 to 2 Torr using a TiCl 4 gas as the source gas. To reduce the effects of Cl gas more effectively, TiN can be deposited in two stages and the Cl gas can be removed by exciting the plasma with NH 3 gas in the middle. In addition, a polysilicon film may be further formed on the TiN layer for the upper electrode.

상술한 바와 같은 발명은, TiN 증착 전 RTN(Rapid Thermal Nitration) 처리하여 Ta2O5박막 표면에 얇은 질화층을 형성하는 것을 특징으로 하는 것으로써, 후속 TiN층 형성시 클로린(Chlorin) 개스로부터 Ta2O5박막을 보호하여 누설전류가 감소된 안정적인이고 신뢰성 높은 커패시터가 형성되게 된다.The invention as described above is characterized in that a thin nitride layer is formed on the surface of the Ta 2 O 5 thin film by RTN (Rapid Thermal Nitration) treatment before TiN deposition, so that Ta from Chlorin gas in the subsequent TiN layer formation is formed. The 2 O 5 thin film is protected to form a stable and reliable capacitor with reduced leakage current.

상술한 바와 같은 본 실시예를 적용하여 커패시터의 형상을 실리더형, 핀형 등으로 제조 가능하며, 또한 반구형폴리실리콘을 사용하는 커패시터 구조에도 적용 가능하다.By applying the present embodiment as described above, the shape of the capacitor can be manufactured in a cylinder type, a pin type, and the like, and can also be applied to a capacitor structure using hemispherical polysilicon.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명은 상부전극의 TiN층 형성시 Cl 개스로부터 탄탈늄산화막의 데미지를 방지하여 누설전류를 방지할 수 있어, 고집적 반도체 메모리소자에서 요구되는 커패시턴스를 갖는 그리고 안정적이고 신뢰성이 큰 커패시터를 제조할 수 있다.The present invention can prevent the leakage current by preventing the tantalum oxide film damage from Cl gas when forming the TiN layer of the upper electrode, it is possible to manufacture a capacitor having the capacitance required in the highly integrated semiconductor memory device and stable and reliable have.

Claims (6)

메모리소자의 커패시터 제조방법에 있어서,In the capacitor manufacturing method of the memory device, 하부전극으로서 폴리실리콘층을 증착하는 단계;Depositing a polysilicon layer as a lower electrode; 제1열적급속질화 처리하여 상기 폴리실리콘층 상에 제1질화층을 형성하는 단계;Forming a first nitride layer on the polysilicon layer by first thermal rapid nitriding; 상기 질화층 상에 탄탈늄산화막을 형성하는 단계;Forming a tantalum oxide film on the nitride layer; 제2열적급속질화 처리하여 상기 탄탈늄산화막 상에 제2질화층을 형성하는 단계; 및Forming a second nitride layer on the tantalum oxide film by performing a second thermal rapid nitriding treatment; And 상기 질화층 상에 상부전극으로서 티타늄나이트라이드층을 형성하는 단계Forming a titanium nitride layer as an upper electrode on the nitride layer 를 포함하여 이루어진 커패시터 제조방법.Capacitor manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 제2열적급속열처리는 질소를 포함하는 개스를 사용하여 600∼800℃에서 10∼60sec 동안 실시함을 특징으로 하는 커패시터 제조방법.The second thermal rapid heat treatment is a capacitor manufacturing method characterized in that performed for 10 to 60 seconds at 600 ~ 800 ℃ using a gas containing nitrogen. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 TiN층은 TiCl4개스를 소오스 개스로하여 400∼750℃의 온도와 0.1∼2 Torr에의 압력 하에서 증착함을 특징으로 하는 커패시터 제조방법.The TiN layer is a method for producing a capacitor, characterized in that the deposition of the TiCl 4 gas source gas at a temperature of 400 ~ 750 ℃ and a pressure of 0.1 to 2 Torr. 제3항에 있어서,The method of claim 3, 상기 탄탈늄산화막을 형성하는 단계는,Forming the tantalum oxide film, 기화된 탄탈륨 에칠레이트를 소오스 가스로하여 저압화학기상증착 방법으로 탄탄늄산화막을 증착하는 단계와,Depositing a tantalum oxide film using a low pressure chemical vapor deposition method using vaporized tantalum ethylene as a source gas; 상기 증착된 탄탈늄산화막을 열처리하여 결정화하는 단계로 이루어짐을 특징으로 하는 커패시터 제조방법.Capacitor manufacturing method comprising the step of crystallizing the deposited tantalum oxide film by heat treatment. 제4항에 있어서,The method of claim 4, wherein 상기 증착된 탄탈늄산화막을 열처리하여 결정화하는 단계는,Crystallizing the deposited tantalum oxide film by heat treatment, 기판 온도 300∼500℃ 및 RF 파워 50∼400Watt에서 N2O 플라즈마 어닐링을 실시하여 탄탈륨산화막내에 존재하는 불순물을 제거하는 단계와, 750∼900℃에서 30∼60분 동안 O2또는 N2O 퍼니스(Furnace) 어닐링을 실시하여 증착된 탄탈늄산화막을 결정화하는 단계로 이루어짐을 특징으로 하는 커패시터 제조방법.N 2 O plasma annealing at a substrate temperature of 300 to 500 ° C. and an RF power of 50 to 400 Watts to remove impurities present in the tantalum oxide film, and an O 2 or N 2 O furnace at 750 to 900 ° C. for 30 to 60 minutes. (Furnace) A method for producing a capacitor comprising the step of crystallizing the deposited tantalum oxide film by performing annealing. 제3항에 있어서,The method of claim 3, 상기 TIN을 2단계로 증착하고 증착 중간에 NH3가스에 플라즈마 여기시켜 Cl가스를 제거하는 것을 특징으로 하는 커패시터 제조방법.And depositing the TIN in two steps and removing the Cl gas by plasma exciting the NH 3 gas in the middle of the deposition.
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Publication number Priority date Publication date Assignee Title
KR20030056842A (en) * 2001-12-28 2003-07-04 주식회사 하이닉스반도체 method for fabricating capacitor of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030056842A (en) * 2001-12-28 2003-07-04 주식회사 하이닉스반도체 method for fabricating capacitor of semiconductor device

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