KR20030056207A - capacitor manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to be capable of restraining the generation of defects of a lower electrode due to stress concentration. CONSTITUTION: After sequentially depositing the first metal layer and an arc layer on an interlayer dielectric(20), a lower electrode(21a) and a lower metal line(21b) are formed by selectively etching the resultant structure. Then, an insulating layer(23) is deposited on the resultant structure. After forming a contact hole by selectively etching the insulating layer for exposing the lower electrode, a dielectric layer(24) and the second metal layer(25) are sequentially filled into the contact hole. Then, a planarization is carried out on the resultant structure. Preferably, the lower electrode is formed before depositing the dielectric layer for restraining the failure due to stress concentration.

Description

Capacitor manufacturing method of semiconductor device

The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more specifically, to manufacturing a capacitor of a semiconductor device capable of securing device reliability through defect prevention when manufacturing a metal-insulator-metal (MIM) capacitor in a composite semiconductor device. It is about a method.

Recently, in order to improve multimedia functions, semiconductor devices have been developed in a form in which a memory cell array unit and peripheral circuits are mounted together, and a capacitor suitable for high-speed processing of high-capacity information has emerged as a core technology.

On the other hand, in the case of PIP (Polysilicon-Insulator-Polysilicon) capacitors, since the upper and lower electrodes are formed of polysilicon, the specific resistance is large and parasitic capacitance due to the depletion phenomenon works, whereas the MIM capacitor In this case, it is evaluated that the implementation of a high speed, highly integrated composite semiconductor device is very suitable because it does not cause the above problem.

In addition, a MIM capacitor applied to a highly integrated semiconductor device for RF is embedded between metal wiring layers in order to reduce interference with a lower transistor, and the lower metal wiring layer and the lower electrode of the MIM are generally placed on the same layer.

A method of manufacturing such a conventional MIM capacitor is described with reference to FIGS. 1A-1D, where the process prior to the generation of the MIM lower electrode is considered to follow the conventional method.

First, as shown in FIG. 1A, an interlayer insulator 10 is formed on an upper portion of a substrate on which a semiconductor device and some metal wiring layers are formed, and the first metal film 11 and the arc ARC ( 12), CVD (Chemical Vapor Deposition) dielectric 13 and the second metal film 14 are sequentially stacked. Here, the arc 12 is formed of Ti / TiN or TiN.

Subsequently, as shown in FIG. 1B, a photoresist patterning and dry etching process is performed on the second metal film 14 and the dielectric 13.

Subsequently, as shown in FIG. 1C, the MIM lower electrode 11 a and the metal wiring layer 11 b are simultaneously formed by the patterning and dry etching processes.

Subsequently, as shown in FIG. 1D, in order to connect the resultant with the upper metal wiring layer, deposition of the interlayer insulator 15 and planarization by chemical mechanical polishing (CMP) are performed, and via holes are formed in the interlayer insulator 15. After the metal buried and planarization processes are sequentially performed, the via electrode 16 is formed, and then the upper wiring layer is formed by patterning and etching after the deposition of the third metal layer 17 and the arc 18 on the resultant metal layer. Complete the built-in MIM capacitor.

This conventional technique has the advantage of embedding a MIM capacitor between metal wiring layers through a relatively simple process, while the lower electrode 11a, which is finally subjected to patterning and etching in the MIM capacitor, is very weak due to the peripheral stress relationship. Have

That is, the arc 12a formed by depositing Ti / TiN or TiN on the lower electrode 11a made of aluminum (Al) by PVD (Physical Vapor Deposition) is subjected to compressive stress conditions at the interface with the lower electrode 11a. When the upper part of the arc 12a is completely exposed, a relatively uniform stress distribution is achieved, while a new upper layer (for example, the interlayer dielectric 13 is formed and partially constrained by the notch effect at the boundary area). Stress concentrations occur, making them very vulnerable.

That is, as shown in FIG. 2, after the formation of the upper dielectric 13 and the upper electrode 14, the arc 12a of the lower electrode 11a is subjected to a strong compressive stress condition at the side portion of the dielectric 13. In a subsequent process including patterning and dry etching of the lower electrode 11a, the interface strength between the arc 12a and the lower electrode 11a due to the temperature rise decreases, thereby increasing the possibility of separation of the interface. This phenomenon may cause defects in MIM capacitors and lower process capability, and thus, new technologies are required to improve the MIM capacitors.

Therefore, the present invention has been made to solve the above-mentioned conventional problems, the object of the present invention is to suppress the occurrence of defects in the lower electrode caused by the stress concentration to ensure the reliability of the semiconductor device, the semiconductor device that can be applied in mass production It is to provide a capacitor manufacturing method of.

1A to 1D are sequential explanatory diagrams showing a method of manufacturing a capacitor of a conventional semiconductor device.

2 is a cross-sectional view showing a bad state of a conventional capacitor manufacturing method.

3A to 3F are cross-sectional views showing a capacitor manufacturing method of a semiconductor device according to the present invention.

-Description of the main symbols in the drawings-

20; Interlayer insulators 21; First metal film

21a; Lower electrode 21b; Metal wiring layer

22; Arc 23, 26; Insulation layer

24; Dielectric 25; Second metal film, upper electrode

28; third metal film 29; Arc

In order to achieve the above object, a method of manufacturing a capacitor of a semiconductor device according to the present invention may include forming a lower metal wiring layer and a lower electrode by laminating a first metal film and an arc on an interlayer insulator and etching the same; Depositing an interlayer insulator on the resultant, forming a contact hole so that a predetermined region of the lower electrode is exposed upward, and subsequently filling the dielectric and the second metal film in sequence and then planarizing it; And depositing an interlayer insulator on the resultant, forming a via hole by selective etching of the insulator, forming and planarizing via electrodes, and forming an upper metal wiring layer by patterning and etching after the third metal film and the arc deposition. It features.

Here, the lower electrode is patterned before dielectric deposition to suppress defects due to stress concentration.

In addition, the dielectric and upper electrode forming process may also be applied to the Cu / damascene process.

As described above, according to the method of manufacturing a capacitor of a semiconductor device according to the present invention, since the occurrence of defects in the lower electrode caused by stress concentration can be suppressed, there is an advantage of enabling reliability and mass production of the semiconductor device.

In addition, the process of forming the dielectric and the upper electrode can be applied to the formation of the capacitor of the Cu / damascene process.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

3A to 3F are cross-sectional views showing a capacitor manufacturing method of a semiconductor device according to the present invention.

First, as shown in FIG. 3A, an interlayer insulator 20 is formed on an upper portion of a substrate on which a semiconductor device and some metal wiring layers are formed, and the first metal film 21 is made of aluminum (US) on the surface of the insulator 20. After the deposition, the arc 22 is deposited on the surface of the first metal film 21 by Ti / TiN or TiN.

At this time, the deposition method of TiN is CVD using PVD and Ti-Cl compounds, but in order to be applied as an electrode of MIM, Cl component causing deterioration of dielectric properties should be excluded.

Subsequently, as shown in FIG. 3B, the MIM lower electrode 21a and the lower metal wiring layer 21b are formed by applying the photoresist patterning and dry etching process on the resultant, and then HDP (High Density Plasma) on the top. The insulating layer 23 is formed using an oxidizing CVD method, and the surface of the insulating layer 23 is planarized by a planarization process.

At this time, since the arc 22a of the MIM lower electrode 21a is entirely exposed until the insulation layer 23 is embedded, the interface separation phenomenon due to the notch effect does not occur.

Subsequently, as shown in FIG. 3C, a contact hole in which the MIM dielectric and the second metal film are embedded is formed in the insulator 23.

Subsequently, as shown in FIG. 3D, the dielectric 24 and the second metal film 25 are sequentially filled in the contact hole. At this time, as the material of the second metal film 25 to be applied to the upper electrode 25, TiN, Ti / Tin, W, etc. are suitable, and the thickness is limited because of being embedded between metal layers.

Subsequently, a flattening process is performed on the resultant product as shown in FIG. 3E. The planarization process is performed in two steps of removing the second metal film 25 and the dielectric material 24 except for the contact hole. When the dielectric 24 is removed, a part of the lower insulator 23 is polished. In this case, the thickness of the lower insulator 23 is set in consideration of the relative polishing rates of the dielectric 24 and the lower insulator 23 before the process. Should be.

Finally, as illustrated in FIG. 3F, an interlayer insulator 26 is deposited on the resultant by plasma enhanced CVD, and via holes are formed by selective etching of the insulator 26. The via electrode 27 is formed by being buried and planarized. In addition, a third metal film 28 and an arc 29 are deposited on the resultant, and the MIM capacitor embedded between the metallization layers is completed by sequential process of forming the upper metallization layer by patterning and etching the resultant. .

As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.

Therefore, according to the method for manufacturing a capacitor of a semiconductor device according to the present invention, since the occurrence of defects in the lower electrode caused by stress concentration can be suppressed, there is an effect of ensuring the reliability and mass production of the semiconductor device.

In addition, the process of forming the dielectric and the upper electrode can be applied to the formation of the capacitor of the Cu / damascene process.

Claims (3)

Stacking and etching the first metal film and the arc on the interlayer insulator to form a lower metal wiring layer and a lower electrode; Depositing an interlayer insulator on the resultant, forming a contact hole so that a predetermined region of the lower electrode is exposed upward, and subsequently filling the second metal film as a dielectric and an upper electrode, and then planarizing it; Forming an upper metal wiring layer by interlayer insulator deposition, via hole formation by selective etching of the insulator, via electrode formation and planarization, and patterning and etching after the third metal film and arc deposition. Capacitor manufacturing method of device. The method of claim 1, wherein the lower electrode is patterned before dielectric deposition to suppress defects due to stress concentration. The method of claim 1, wherein the dielectric and upper electrode forming process is also applied to a Cu / damascene process.