KR20040009790A - Semiconductor device and fabrication method of thereof - Google Patents
Semiconductor device and fabrication method of thereof Download PDFInfo
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- KR20040009790A KR20040009790A KR1020020043852A KR20020043852A KR20040009790A KR 20040009790 A KR20040009790 A KR 20040009790A KR 1020020043852 A KR1020020043852 A KR 1020020043852A KR 20020043852 A KR20020043852 A KR 20020043852A KR 20040009790 A KR20040009790 A KR 20040009790A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010410 layer Substances 0.000 claims abstract description 70
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 239000003990 capacitor Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 230000004888 barrier function Effects 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims 1
- 239000007769 metal material Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 35
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 239000012212 insulator Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 금속/ 절연체/ 금속 (MIM) 구조의 커패시터를 포함하는 반도체 소자 및 그 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device comprising a capacitor of a metal / insulator / metal (MIM) structure and a method of manufacturing the same.
최근 등장하는 복합 반도체장치(MML:Merged Memory Logic)는 하나의 칩 내에 메모리 셀 어레이부, 예컨대 디램(DRAM :dynamic random access memory)과 아날로그 또는 주변회로가 함께 집적화된 소자이다. 이러한 복합 반도체장치의 등장으로 인해 멀티미디어 기능이 크게 향상되어 종전보다 반도체장치의 고집적화 및 고속화를 효과적으로 달성할 수 있게 되었다.BACKGROUND ART Recently, a merged memory logic (MML) is a device in which a memory cell array unit such as dynamic random access memory (DRAM) and an analog or peripheral circuit are integrated together in one chip. Due to the emergence of such composite semiconductor devices, multimedia functions have been greatly improved, and high integration and speed of semiconductor devices can be effectively achieved.
한편, 고속 동작을 요구하는 아날로그 회로에서는 고용량의 커패시터를 구현하기 위한 반도체소자 개발이 진행 중에 있다. 일반적으로, 커패시터가 다결정실리콘(polysilicon)/ 절연체(insulator)/ 다결정실리콘(polysilicon)의 PIP 구조일 경우에는 상부전극 및 하부전극을 도전성 다결정실리콘으로 사용하기 때문에 상,하부전극과 유전체 박막 계면에서 산화반응이 일어나 자연산화막이 형성되어 전체커패시턴스의 크기가 줄어들게 되는 단점이 있다.Meanwhile, in an analog circuit requiring high speed operation, development of a semiconductor device for implementing a high capacitance capacitor is underway. In general, when the capacitor is a PIP structure of polysilicon / insulator / polysilicon, the upper electrode and the lower electrode are used as the conductive polysilicon, so that the oxides are oxidized at the upper and lower electrodes and the dielectric thin film interface. The reaction occurs to form a natural oxide film has the disadvantage that the size of the total capacitance is reduced.
이를 해결하기 위해 커패시터의 구조를 금속/절연체/실리콘 (metal/insulator/silicon : MIS) 또는 금속/절연체/금속(metal/insulator/metal : MIM)으로 변경하게 되었는데, 그 중에서도 MIM 구조의 커패시터는 비저항이 작고 내부에 공핍(deplection)에 의한 기생 커패시턴스가 없기 때문에 고성능 반도체 장치에 주로 이용되고 있다.To solve this problem, the structure of the capacitor was changed to metal / insulator / silicon (MIS) or metal / insulator / metal (MIM). Because of its small size and no parasitic capacitance due to depletion inside, it is mainly used for high performance semiconductor devices.
그러면, 종래 반도체 소자 제조방법에 따라 MIM 구조의 커패시터를 제조하는 방법을 첨부된 도면을 참조하여 설명한다. 도 1은 종래 방법에 따라 형성된 반도체 소자를 도시한 단면도이다.Next, a method of manufacturing a capacitor having a MIM structure according to a conventional semiconductor device manufacturing method will be described with reference to the accompanying drawings. 1 is a cross-sectional view showing a semiconductor device formed according to a conventional method.
먼저, 반도체 기판(1)의 상부에 통상의 반도체 소자 공정을 진행하고 하부산화막(2)을 형성한 다음, 하부산화막(2) 상에 하부전극(3)을 형성하고, 하부전극(3) 상에 감광막 패턴(미도시)을 형성한 후 감광막 패턴을 마스크로 하여 하부전극(3)을 식각하여 소정폭을 남긴다.First, a normal semiconductor device process is performed on the semiconductor substrate 1, and a lower oxide film 2 is formed. Then, a lower electrode 3 is formed on the lower oxide film 2, and the lower electrode 3 is formed on the lower electrode 3. After the photoresist pattern (not shown) is formed on the lower electrode 3 by etching the photoresist pattern as a mask, a predetermined width is left.
다음, 하부전극(3)을 포함하여 하부산화막(2)의 상부전면에 산화막(4)을 두껍게 증착하고 화학기계적 연마하여 상면을 평탄화한 후, 산화막(4) 상에 하부전극(3) 상부의 소정영역이 오프닝된 감광막 패턴을 형성하고, 그 감광막 패턴을 마스크로 하여 하부전극(3) 상의 산화막(4)을 소정영역 식각함으로써, 하부전극(3)의 표면을 개방하는 소정폭의 홀(100)을 형성한다. 그러나, 이러한 홀(100) 형성을 위한 산화막(4) 식각시, 하부전극(3)의 표면, 특히 홀의 하단 양 모서리와 인접한 부분(도 1에서 A로 표시됨)이 손상되는 언더컷 현상이 발생하기가 쉽다.Next, the oxide film 4 is thickly deposited on the upper surface of the lower oxide film 2 including the lower electrode 3 and chemically mechanically polished to planarize the upper surface, and then the upper surface of the lower electrode 3 is deposited on the oxide film 4. A hole 100 having a predetermined width that opens the surface of the lower electrode 3 by forming a photoresist pattern in which a predetermined region is opened and etching the predetermined region of the oxide film 4 on the lower electrode 3 using the photoresist pattern as a mask. ). However, when etching the oxide film 4 to form the hole 100, an undercut phenomenon occurs in which the surface of the lower electrode 3, in particular, the portions adjacent to both bottom edges of the hole (indicated by A in FIG. 1) are damaged. easy.
다음, 홀(100)의 내벽에 유전체층(5)을 형성하고, 유전체층(5) 상에 상부전극(6)을 홀(100) 내부가 매립되도록 형성함으로써, 하부전극(3), 유전체층(5) 및 상부전극(6)으로 이루어진 MIM 구조의 커패시터 제조를 완료한다.Next, the dielectric layer 5 is formed on the inner wall of the hole 100, and the lower electrode 3 and the dielectric layer 5 are formed by forming the upper electrode 6 on the dielectric layer 5 so that the inside of the hole 100 is embedded. And to complete the manufacturing of the capacitor of the MIM structure consisting of the upper electrode (6).
그러나, 상기한 바와 같은 종래 방법에서는 언더컷에 의해 A 부분 상에는 유전체층이 균일하게 형성되지 않기 때문에, 결과적으로 A 부분에서 유전체층이 끊어지고 끊어진 부분을 통해 상부전극이 하부전극과 상호 도통하여 커패시터의 역할을 못하게 되는 문제점이 있었다.However, in the conventional method as described above, since the dielectric layer is not uniformly formed on the portion A by the undercut, as a result, the upper electrode is electrically connected to the lower electrode through the portion where the dielectric layer is broken and broken in the portion A, thereby serving as a capacitor. There was a problem that prevented.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 홀 형성을 위한 산화막 식각시 하부전극이 손상되는 언더컷으로 인해 커패시터가 파괴되는 것을 방지하는 데 있다.The present invention is to solve the problems as described above, the object is to prevent the capacitor from being destroyed by the undercut damage to the lower electrode during the etching of the oxide film for hole formation.
도 1은 종래 반도체 소자를 도시한 단면도이다.1 is a cross-sectional view showing a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 커패시터의 하부전극 상에 유전체층을 형성한 후, 비아홀을 형성하고 비아홀 내에 상부금속을 매립하는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized in that after forming a dielectric layer on the lower electrode of the capacitor, forming a via hole and filling the upper metal in the via hole.
이하, 본 발명에 따른 반도체 소자 및 그 제조 방법에 대해 상세히 설명한다. 도 2a 내지 도 2c는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail. 2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
본 발명에 따라 제조된 반도체 소자는 도 2c에 도시되어 있으며, 이에 도시된 바와 같이, 본 발명에 따른 반도체 소자에서는, 반도체 기판(11)의 구조물 상에는 하부절연막(12)이 형성되어 있고, 하부절연막(12) 상에는 소정폭의 하부전극(13) 및 유전체층(15)이 형성되어 있으며, 유전체층(15) 상에는 이보다 좁은 폭의 비아홀(200)이 형성되어 있고, 비아홀(200)의 내부에는 텅스텐 등으로 이루어진 상부전극(20)이 매립되어 있으며, 비아홀(200)의 외측방, 하부전극(13)과 유전체층(15)의 외부, 및 하부절연막(12) 상에는 층간절연막(17)이 형성되어 있고, 상부전극(20) 및 층간절연막(17) 상에는 소정폭의 금속배선(22)이 형성되어 있다.The semiconductor device manufactured according to the present invention is illustrated in FIG. 2C. As shown in FIG. 2, in the semiconductor device according to the present invention, a lower insulating film 12 is formed on a structure of the semiconductor substrate 11, and a lower insulating film is provided. The lower electrode 13 and the dielectric layer 15 having a predetermined width are formed on the 12, and the via hole 200 having a narrower width is formed on the dielectric layer 15, and the tungsten or the like is formed inside the via hole 200. The upper electrode 20 is buried, and the interlayer insulating film 17 is formed on the outer side of the via hole 200, the outside of the lower electrode 13 and the dielectric layer 15, and the lower insulating film 12. Metal wires 22 of a predetermined width are formed on the electrode 20 and the interlayer insulating film 17.
이 때, 하부전극(13) 상에는 반사방지막(14)이 추가로 형성될 수 있으며, 비아홀(200)의 내벽에는 제1베리어금속막(19)이, 금속배선(22)의 하면에는 제2베리어금속막(21)이 형성될 수 있다.In this case, an anti-reflection film 14 may be further formed on the lower electrode 13, and the first barrier metal film 19 is formed on the inner wall of the via hole 200, and the second barrier is formed on the bottom surface of the metal wiring 22. The metal film 21 may be formed.
또한, 비아홀(200)의 폭은 유전체층(15) 폭의 1/2 보다 크면서 유전체층(15) 폭보다 좁은 것이 바람직하다.In addition, the width of the via hole 200 is preferably greater than 1/2 of the width of the dielectric layer 15 and narrower than the width of the dielectric layer 15.
유전체층(15)은 400~800Å의 두께를 가지는데, 이러한 유전체층은 산화물, 실리콘나이트라이드, 및 실리콘옥시나이트라이드 중의 어느 한 물질로 이루어질 수도 있고, 산화물층, 실리콘나이트라이드층, 및 실리콘옥시나이트라이드층 중에서 선택된 2종 이상의 층이 적층된 구조로 이루어질 수도 있다.Dielectric layer 15 has a thickness of 400 ~ 800Å, such dielectric layer may be made of any one of oxide, silicon nitride, and silicon oxynitride, oxide layer, silicon nitride layer, and silicon oxynitride Two or more types selected from the layers may be laminated.
그러면, 상기한 바와 같은 본 발명의 반도체 소자를 제조하는 방법에 대해 상세히 설명한다.Then, the method of manufacturing the semiconductor device of the present invention as described above will be described in detail.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판(11)의 상부에 통상의 반도체 소자 공정을 진행하고 하부절연막(12)을 형성한 다음, 하부절연막(12) 상에 하부전극(13) 및 유전체층(15)을 차례로 형성한다. 이 때 하부전극(13) 상에는 반사방지막(14)을 형성한 후, 반사방지막(14) 상에 유전체층(15)을 형성할 수도 있다.First, as shown in FIG. 2A, a normal semiconductor device process is performed on the semiconductor substrate 11, and a lower insulating layer 12 is formed. Then, the lower electrode 13 and the dielectric layer are formed on the lower insulating layer 12. (15) are formed in sequence. In this case, after forming the anti-reflection film 14 on the lower electrode 13, the dielectric layer 15 may be formed on the anti-reflection film 14.
또한, 유전체층(15)은 400~800Å의 두께로 형성하는 것이 바람직하며, 이러한 유전체층(15)은 산화물, 실리콘나이트라이드, 및 실리콘옥시나이트라이드 중의 어느 한 물질을 사용하여 형성하거나, 또는 산화물층, 실리콘나이트라이드층, 및 실리콘옥시나이트라이드층 중에서 선택된 2종 이상의 층이 적층된 구조로 형성할 수 있다.In addition, the dielectric layer 15 is preferably formed to a thickness of 400 ~ 800Å, such a dielectric layer 15 is formed using any one of an oxide, silicon nitride, and silicon oxynitride, or an oxide layer, The silicon nitride layer and the silicon oxynitride layer may be formed in a stacked structure of two or more kinds of layers.
이어서, 유전체층(15)의 상부 전면에 감광막을 도포하고 노광 및 현상하여 소정폭의 감광막만을 남기고 나머지를 식각함으로써 감광막 패턴(16)을 형성한다.Subsequently, a photoresist film is coated on the entire upper surface of the dielectric layer 15, and the photoresist pattern 16 is formed by etching and exposing the photoresist film, leaving only the photoresist film having a predetermined width.
다음, 감광막 패턴(16)을 마스크로 하여 상면이 노출된 유전체층(15), 반사방지막(14), 및 하부전극(13)을 소정부분을 식각하여, 도 2b에 도시된 바와 같이 유전체층(15), 반사방지막(14), 및 하부전극(13)을 소정폭으로 남긴 후, 감광막 패턴(16)을 제거하고 세정공정을 수행한다.Next, the upper portion of the dielectric layer 15, the antireflection film 14, and the lower electrode 13 are etched using the photoresist pattern 16 as a mask, and the dielectric layer 15 is etched as shown in FIG. 2B. After leaving the antireflection film 14 and the lower electrode 13 at a predetermined width, the photoresist pattern 16 is removed and a cleaning process is performed.
이어서, 유전체층(15)을 포함하여 하부절연막(12)의 상부 전면에 산화막 등으로 이루어진 층간절연막(17)을 두껍게 증착한다. 층간절연막(17)의 증착 후에는 화학기계적 연마하여 그 상면을 평탄화할 수 있으며, 평탄화 후에는 400~600℃의온도로 열처리할 수 있다.Subsequently, an interlayer insulating film 17 made of an oxide film or the like is thickly deposited on the entire upper surface of the lower insulating film 12 including the dielectric layer 15. After the deposition of the interlayer insulating film 17, the upper surface of the interlayer insulating film 17 may be flattened by chemical mechanical polishing, and the planarized heat treatment may be performed at a temperature of 400 to 600 ° C.
이어서, 평탄화된 층간절연막(17)의 상면에 감광막을 도포하고 노광 및 현상하여 비아로 예정된 부분의 제2층간절연막(17) 상면을 노출시키는 감광막 패턴(18)을 형성한다.Subsequently, a photosensitive film is coated on the top surface of the planarized interlayer insulating film 17, and exposed and developed to form a photosensitive film pattern 18 exposing the top surface of the second interlayer insulating film 17 in a portion intended to be a via.
다음, 감광막 패턴(18)을 마스크로 하여 상면이 노출된 층간절연막(17) 부분을 건식식각하여 유전체층(15)의 표면을 개방하는 소정폭의 비아홀(200)을 형성한다.Next, the photoresist pattern 18 is used as a mask to dry-etch the portion of the interlayer insulating layer 17 having the upper surface exposed to form a via hole 200 having a predetermined width opening the surface of the dielectric layer 15.
다음, 감광막 패턴(18)을 제거하고 세정공정을 수행한 다음, 비아홀(200)의 내벽에 제1베리어금속막(19)을 증착하고, 제1베리어금속막(19) 상에 텅스텐 등의 상부전극(20)을 증착하여 비아홀(200)의 내부를 완전히 매립한다. 상부전극(20)의 증착 후에는 층간절연막(17)의 상면이 노출될 때까지 화학기계적 연마하여 상면을 평탄화시킬 수 있으며, 평탄화 후에는 400~600℃의 온도로 열처리할 수 있다.Next, the photoresist layer pattern 18 is removed and a cleaning process is performed. Then, the first barrier metal layer 19 is deposited on the inner wall of the via hole 200, and an upper portion of tungsten or the like is formed on the first barrier metal layer 19. The electrode 20 is deposited to completely fill the inside of the via hole 200. After the deposition of the upper electrode 20, the upper surface of the interlayer insulating layer 17 may be chemically polished until the upper surface is exposed to planarize the upper surface, and after the planarization, the upper electrode 20 may be heat treated at a temperature of 400 to 600 ° C. FIG.
상기한 구조에서, 하부전극(13), 유전체층(15), 및 상부전극(20)은 MIM 구조의 커패시터에 해당된다.In the above structure, the lower electrode 13, the dielectric layer 15, and the upper electrode 20 correspond to a capacitor of the MIM structure.
이어서, 평탄화된 상면에 제2베리어금속막(21) 및 금속배선막(22)을 차례로 증착하고 이들을 패터닝하여 금속배선을 형성한다. 이 때 제2베리어금속막(21) 형성 이전에, 플라즈마 식각을 수행하여 상부전극(20) 표면의 이물질을 제거할 수 있다.Subsequently, the second barrier metal film 21 and the metal wiring film 22 are sequentially deposited on the flattened top surface and patterned to form metal wirings. In this case, before the formation of the second barrier metal layer 21, plasma etching may be performed to remove foreign substances on the surface of the upper electrode 20.
상술한 바와 같이, 본 발명에서는 커패시터의 하부전극 상에 유전체층을 형성한 후, 비아홀을 형성하고 비아홀 내에 상부금속을 매립하기 때문에, 종래 비아홀 식각시 하부전극이 손상되는 언더컷 현상이 방지되는 효과가 있으며, 따라서, 유전체층을 안정된 구조로 형성하는 효과가 있다.As described above, in the present invention, since the dielectric layer is formed on the lower electrode of the capacitor, the via hole is formed and the upper metal is buried in the via hole, thereby preventing the undercut phenomenon in which the lower electrode is damaged during the conventional via hole etching. Therefore, there is an effect of forming the dielectric layer into a stable structure.
또한, 언더컷으로 인해 커패시터가 파괴되는 일이 방지되는 효과가 있다.In addition, there is an effect that the capacitor is prevented from being destroyed by the undercut.
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