KR20030056185A - Circuit for driving wordline of semiconductor device - Google Patents

Circuit for driving wordline of semiconductor device Download PDF

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KR20030056185A
KR20030056185A KR1020010086359A KR20010086359A KR20030056185A KR 20030056185 A KR20030056185 A KR 20030056185A KR 1020010086359 A KR1020010086359 A KR 1020010086359A KR 20010086359 A KR20010086359 A KR 20010086359A KR 20030056185 A KR20030056185 A KR 20030056185A
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word line
level
sub
enabled
signal
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KR1020010086359A
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Korean (ko)
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KR100567023B1 (en
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안기용
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주식회사 하이닉스반도체
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

PURPOSE: A word line driving circuit of a semiconductor memory is provided to prevent the loss of data due to the word line coupling noise generated during the active operation of DRAM by transiently applying the voltage Vbb to the word line selected during the word line enable of the DRAM, thereby improving the performance of the device. CONSTITUTION: A word line driving circuit of a semiconductor memory includes a plurality of main word lines(MWL), a plurality of sub word lines(WL) and a plurality of sub word line drivers placed between each of the plurality of main word lines(MWL) and the plurality of sub word lines(WL). In the word line driving circuit of the semiconductor memory, a first and a second word line level down signals(wl_down) are alternately applied to each of the plurality of sub word line drivers, thereby preventing the level rising of the adjacent word line which is not enabled.

Description

반도체 메모리의 워드라인 구동 회로{Circuit for driving wordline of semiconductor device}Word line driving circuit of a semiconductor memory {Circuit for driving wordline of semiconductor device}

본 발명은 반도체 메모리에 관한 것으로, 구체적으로 선택 워드 라인에 인접한 워드 라인에 순간적으로 음전위가 인가되도록 하여 워드라인 커플링 노이즈 개선할 수 있도록한 반도체 메모리의 워드라인 구동 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a word line driving circuit of a semiconductor memory capable of improving a word line coupling noise by applying a negative potential to a word line adjacent to a selected word line.

일반적으로 반도체 메모리의 서브 워드라인 구동회로는 상위 프리 디코딩신호를 인가받아 디코딩하는 로우 디코더의 출력 신호인 글로벌 워드라인 인에이블신호와 반전 글로벌 워드라인 인에이블 신호에 따라 구동되어, 하위 프리 디코딩신호를 반도체 메모리의 특정 워드라인을 통해 출력하여 특정 열의 메모리 셀을 인에이블시키는 동작을 한다.In general, a sub word line driving circuit of a semiconductor memory is driven according to a global word line enable signal and an inverted global word line enable signal, which are output signals of a row decoder that receives and decodes an upper pre-decoded signal, thereby driving a lower pre-decoded signal. Outputs through a specific word line of the semiconductor memory to enable the memory cells of a specific column.

이하에서 일반적인 DRAM 및 그의 구동 회로에 관하여 설명한다.Hereinafter, a general DRAM and its driving circuit will be described.

도 1은 일반적인 DRAM의 기본 셀(cell) 구성도이고, 도 2는 일반적인 DRAM 회로의 블록 다이어그램이다.1 is a block diagram illustrating a basic cell of a general DRAM, and FIG. 2 is a block diagram of a general DRAM circuit.

그리고 도 3은 비트라인 센스 앰프의 동작을 나타낸 타이밍도이고, 도 4는 종래 기술에서의 워드라인 커플링 노이즈에 의한 오동작 타이밍도이다.3 is a timing diagram showing an operation of a bit line sense amplifier, and FIG. 4 is a timing diagram of malfunction due to word line coupling noise in the prior art.

그리고 도 5는 종래 기술의 DRAM의 워드 드라이버 블록의 구성도이다.5 is a block diagram of a word driver block of a conventional DRAM.

DRAM은 커패시터를 저장 수단으로 사용하여 고집적화를 이룬 반도체 메모리 소자이다.DRAM is a highly integrated semiconductor memory device using a capacitor as a storage means.

도 1은 DRAM 기본 셀구조를 나타낸 것으로 1개의 커패시터와 1개의 NMOS 트랜지스터로 구성된다.1 shows a DRAM basic cell structure, which is composed of one capacitor and one NMOS transistor.

NMOS 트랜지스터 게이트에는 기본 셀을 배열하여 셀 어레이를 구성하였을때 로우(Row)에 해당하는 워드라인이 연결되고, NMOS 트랜지스터의 정션(junction)에는 각각 데이터 저장 장치인 커패시터와 컬럼에 해당하는 비트 라인이 연결된다.When a cell array is formed by arranging a base cell, a word line corresponding to a row is connected to the gate of the NMOS transistor, and a bit line corresponding to a capacitor and a column, which are data storage devices, is respectively connected to a junction of the NMOS transistor. Connected.

DRAM의 어레이를 중심으로 한 구동 회로의 구성은 도 2에서와 같이, 복수개의 워드라인((WL0),(WL1),(WL2),......(WLn)들과 비트라인(BL0)(BLb0),(BL1)(BLb1),....(BLn)(BLbn)쌍들이 수직으로 교차하여 복수개의 메모리 셀들이 구성되고, 각각의 워드라인과 비트라인에 구동신호를 인가하기 위한 블록들로 RAS 버퍼(21),로우 어드레스 버퍼(22),로우 프리디코더(23),로우 디코더(24) 그리고 CAS 버퍼(25),컬럼 어드레스 버퍼(26),컬럼 프리디코더(27),컬럼 디코더(28)가 구성된다.As shown in FIG. 2, a driving circuit centering on an array of DRAMs includes a plurality of word lines WL0, WL1, WL2,..., WLn and a bit line BL0. (BLb0), (BL1) (BLb1), ..... (BLn) (BLbn) pairs vertically intersect to constitute a plurality of memory cells, and apply a driving signal to each word line and bit line. RAS buffer 21, row address buffer 22, row predecoder 23, row decoder 24 and CAS buffer 25, column address buffer 26, column predecoder 27, column Decoder 28 is configured.

DRAM의 기본 동작은 X 어드레스의 최종 디코딩 신호에 의해 워드라인이 인에이블("H")되어 커패시터에 저장된 데이터가 비트라인에 실리면 비트라인 S/A가 이를 증폭하여 데이터 버스에 전달하고 최종단인 데이터 출력 버퍼(30)를 통해 데이터를 외부에 출력하는 방식이다.The basic operation of DRAM is that the word line is enabled (“H”) by the final decoded signal of X address, and the data stored in the capacitor is loaded on the bit line. Then, the bit line S / A amplifies it and delivers it to the data bus. The data is output to the outside through the in-data output buffer 30.

도 2를 참조하여 DRAM에서 워드라인을 선택하여 인에이블 시키는 과정을 설명하면 다음과 같다.A process of selecting and enabling a word line in a DRAM will be described with reference to FIG. 2.

외부 신호 RASb가 인에이블("L")되면 RAS 버퍼(21)를 거쳐 내부 ras 신호(int_ras)를 생성하고 이 내부 ras 신호에 의해 로우 어드레스 버퍼(22)에서 캡춰된 X 어드레스는 로우 프리 디코더(23)을 거쳐 로우 디코더(24)에서 최종적으로 1개의 워드라인을 선택하여 인에이블시키게 된다.When the external signal RASb is enabled ("L"), the internal ras signal int_ras is generated via the RAS buffer 21, and the X address captured by the row address buffer 22 by this internal ras signal is a low-free decoder ( 23, the row decoder 24 finally selects and enables one word line.

셀 트랜지스터 게이트에 연결되는 최종 워드라인은 폴리를 사용하고 큰 로딩을 갖기 때문에 X 디코더의 출력(MWL)이 바로 셀 트랜지스터 게이트에 연결하지 않고, 일반적으로 도 5와 같이 셀 어레이 중간 중간에 sub 워드라인 드라이버를 사용하여 서브 워드라인 드라이버에 의해 최종적으로 워드라인을 구동하게 한다.Because the final wordline connected to the cell transistor gate uses poly and has a large loading, the output of the X decoder (MWL) does not directly connect to the cell transistor gate, but generally the sub wordline in the middle of the cell array as shown in FIG. The driver is used to finally drive the word line by the sub word line driver.

셀 어레이의 워드라인과 워드라인 사이에는 커플링 커패시턴스가 존재하는데 DRAM이 미세화, 고집적화되어 가면서 이 워드라인 사이에 커플링 커패시턴스도 더 이상 무시할 수 없게 되었다.Coupling capacitance exists between the word lines and the word lines of the cell array. As DRAM becomes finer and more dense, the coupling capacitance between the word lines can no longer be ignored.

이 워드라인간의 커플링 노이즈로 인해 도 4에서의 타이밍도에서와 같이, 워드라인 인에이블("H")시 선택된 워드라인의 인접 워드라인의 레벨이 셀 트랜지스터의 Vt 이상으로 동반 상승할 경우에 인접 워드라인에 해당하는 셀 데이터의 손실이 발생하게 된다.Due to the coupling noise between these word lines, as shown in the timing diagram of FIG. 4, when the level of the adjacent word line of the selected word line rises together with Vt of the cell transistor at the time of word line enable ("H"), Loss of cell data corresponding to adjacent word lines occurs.

그러나 이와 같은 종래 기술의 반도체 메모리의 워드라인 구동 장치는 다음과 같은 문제가 있다.However, the word line driving apparatus of the semiconductor memory of the prior art has the following problems.

워드라인 사이에 커플링 커패시턴스를 고려하지 않고 워드 라인을 구동하여 워드라인간의 커플링 노이즈로 인해 워드라인 인에이블("H")시 선택된 워드라인의 인접 워드라인의 레벨이 셀 트랜지스터의 Vt 이상으로 동반 상승할 경우에 인접 워드라인에 해당하는 셀 데이터의 손실이 발생하게 된다.Drives the word lines without considering the coupling capacitance between the word lines so that the level of adjacent word lines of the selected word lines is higher than the Vt of the cell transistor when the word lines are enabled ("H") due to the coupling noise between the word lines. In the case of a rise together, cell data corresponding to adjacent word lines is lost.

이는 출력 데이터의 신뢰성을 저하시켜 제품의 경쟁력을 떨어뜨린다.This decreases the reliability of the output data, making the product less competitive.

본 발명은 이와 같은 종래 기술의 반도체 메모리 구동 회로의 문제를 해결하기 위한 것으로, 선택 워드 라인에 인접한 워드 라인에 순간적으로 음전위가 인가되도록 하여 워드라인 커플링 노이즈 개선할 수 있도록한 반도체 메모리의 워드라인 구동 회로를 제공하기 위한 것이다.The present invention is to solve the problem of the conventional semiconductor memory driving circuit, a word line of the semiconductor memory to improve the word line coupling noise by applying a negative potential to the word line adjacent to the selected word line instantaneously It is for providing a driving circuit.

도 1은 일반적인 DRAM의 기본 셀 구성도1 is a basic cell configuration diagram of a typical DRAM

도 2는 일반적인 DRAM 회로의 블록 다이어그램2 is a block diagram of a typical DRAM circuit

도 3은 비트라인 센스 앰프의 동작을 나타낸 타이밍도3 is a timing diagram illustrating an operation of a bit line sense amplifier.

도 4는 종래 기술에서의 워드라인 커플링 노이즈에 의한 오동작 타이밍도4 is a malfunction timing diagram due to word line coupling noise in the prior art.

도 5는 종래 기술의 DRAM의 워드 드라이버 블록의 구성도5 is a block diagram of a word driver block of a conventional DRAM

도 6은 본 발명에 따른 워드라인 드라이버 블록의 구성도6 is a block diagram of a word line driver block according to the present invention.

도 7은 도 6의 서브 워드라인 드라이버의 상세 구성도FIG. 7 is a detailed configuration diagram of a sub word line driver of FIG. 6.

도 8은 워드라인 레벨 다운 신호(wl_down)발생 블록의 구성도8 is a block diagram of a word line level down signal wl_down generation block;

도 9는 본 발명에 따른 워드라인 드라이버의 동작 타이밍도9 is an operation timing diagram of a word line driver according to the present invention.

-도면의 주요 부분에 대한 부호의 설명-Explanation of symbols on main parts of drawing

80. RAS 버퍼 81. 어드레스 버퍼80.RAS Buffer 81.Address Buffer

82. 로우 프리디코더 83. 워드라인 레벨 다운 신호 발생 제어부82. Low predecoder 83. Word line level down signal generation control

84. 로우 디코더 85a.85b. 제 1,2 VBB 레벨 변환부84. Row Decoder 85a.85b. First and second VBB level converter

86a.86b.86c.86d. 인버터 87a.87b. 제 1,2 NAND 게이트86a.86b.86c.86d. Inverter 87a.87b. 1st and 2nd NAND gate

이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 메모리의 워드라인 구동 회로는 복수개의 서브 셀 어레이를 포함하고, 복수개의 메인 워드 라인들과 복수개의 서브 워드 라인들을 갖는 메모리를 구동하는 회로에 있어서,각각의 메인 워드 라인과 서브 워드 라인들 사이에 그들에 대응하여,서로 직렬 연결되어 게이트가 공통으로 메인 워드 라인에 연결되고 출력단은 워드 라인에 공통으로 연결되는 PMOS 트랜지스터와 NMOS 트랜지스터 그리고 출력단에 일측 전극이 연결되고 타측 전극에는 음전위 vbb가 인가되고 게이트에 워드 라인 레벨 다운 신호가 인가되는 다른 NMOS 트랜지스터를 포함하여 서브 워드 라인 드라이버가 구성되고,상기 서브 워드 라인 드라이버에는 제 1,2 워드 라인 레벨 다운 신호(wl_down<0>) (wl_down<1>)이 교번적으로 인가되어 인에이블되지 않은 인접 워드 라인의 레벨 상승을 억제하는 것을 특징으로 한다.In the circuit for driving a memory of a word line driving circuit of a semiconductor memory according to the present invention for achieving the above object includes a plurality of sub-cell array, a plurality of main word lines and a plurality of sub word lines, Corresponding to each other between each of the main word lines and the sub word lines, the PMOS transistor and the NMOS transistor connected to each other in series so that the gate is commonly connected to the main word line and the output terminal is commonly connected to the word line, and one electrode at the output The sub word line driver is configured to include the other NMOS transistor connected to the other electrode and a negative potential vbb is applied to the other electrode, and a word line level down signal is applied to the gate, and the sub word line driver has a first and second word line level down signals. (wl_down <0>) (wl_down <1>) are alternately authorized It characterized in that for suppressing the rise of the level of the adjacent word line block are not.

이하에서 본 발명에 따른 반도체 메모리의 워드라인 구동 회로에 관하여 상세히 설명한다.Hereinafter, a word line driving circuit of a semiconductor memory according to the present invention will be described in detail.

도 6은 본 발명에 따른 워드라인 드라이버 블록의 구성도이고, 도 7은 도 6의 서브 워드라인 드라이버의 상세 구성도이다.6 is a configuration diagram of a word line driver block according to the present invention, and FIG. 7 is a detailed configuration diagram of the sub word line driver of FIG.

그리고 도 8은 워드라인 레벨 다운 신호(wl_down)발생 블록의 구성도이고, 도 9는 본 발명에 따른 워드라인 드라이버의 동작 타이밍도이다.8 is a configuration diagram of a word line level down signal wl_down generation block, and FIG. 9 is an operation timing diagram of a word line driver according to the present invention.

본 발명에서는 DRAM의 워드라인 인에이블시 선택된 워드라인의 인접 워드라인에 순간적으로 Vbb 전위를 가하여 DRAM의 액티브 동작시 발생되는 워드라인 커플링 노이즈를 개선할 수 있도록한 것이다.In the present invention, when the word line of the DRAM is enabled, Vbb potential is instantaneously applied to an adjacent word line of the selected word line to improve word line coupling noise generated during active operation of the DRAM.

도 6은 본 발명에 의한 서브 워드라인 드라이버 구동 방식의 셀 어레이 구조를 나타낸 것으로 서브 워드라인 드라이버의 구조를 벌크 바이어스(bulk bias) 전위로 사용되며 음전위인 Vbb 전위로의 풀 다운 트랜지스터를 포함하는 도 7과 같이 변경한 것이다.FIG. 6 illustrates a cell array structure of a sub word line driver driving method according to the present invention, wherein the structure of the sub word line driver is used as a bulk bias potential and includes a pull down transistor having a negative potential Vbb potential. The change is as shown in 7.

그 구성은 복수개의 서브 셀 어레이를 포함하고, 복수개의 메인 워드 라인((MWL0),(MWL1),(MWL2),....(MWLn))과 복수개의 서브 워드 라인((WL0), (WL1),....(WLn))이 구성되고, 각각의 메인 워드 라인과 서브 워드 라인들 사이에는 그들에 대응하여 서브 워드 라인 드라이버가 구성되고, 각각의 서브 워드 라인 드라이버에는 제 1,2 워드 라인 레벨 다운 신호(wl_down<0>)(wl_down<1>)이 교번적으로 인가된다.The configuration includes a plurality of subcell arrays, and includes a plurality of main word lines (MWL0), (MWL1), (MWL2), ..., (MWLn) and a plurality of subword lines (WL0), ( WL1),... (WLn)), sub word line drivers are configured between each of the main word lines and the sub word lines corresponding to them, and each of the first and second sub word line drivers is provided. The word line level down signal wl_down <0> (wl_down <1>) is alternately applied.

그리고 서브 워드 라인 드라이버는 도 7에서와 같이, 소오스에 Vpp가 인가되는 PMOS 트랜지스터와 소오스에 접지전압이 인가되는 NMOS 트랜지스터가 직렬 연결되어 게이트는 메인 워드 라인에 공통으로 연결되고 출력단은 워드라인에 연결된다.In the sub word line driver, as shown in FIG. 7, the PMOS transistor to which the Vpp is applied to the source and the NMOS transistor to which the ground voltage is applied to the source are connected in series so that the gate is connected to the main word line and the output terminal is connected to the word line. do.

그리고 출력단에 일측 전극이 연결되고 타측 전극에는 vbb가 인가되고 게이트에 워드 라인 레벨 다운 신호가 인가되는 NMOS 트랜지스터가 포함된다.An NMOS transistor includes one electrode connected to an output terminal, a vbb applied to the other electrode, and a word line level down signal applied to the gate.

본 발명의 워드라인 구동 회로는 특정 워드라인 인에이블시 워드 라인 레벨 다운(wl_down) 펄스 신호가 인접 워드라인을 Vbb 전위로 레벨 다운시킴으로써 워드라인 커플링 커패시턴스에 의한 비선택 인접 워드라인의 레벨 상승을 억제하도록 한 것이다.The word line driver circuit of the present invention prevents a word line level down (wl_down) pulse signal from increasing the level of an unselected adjacent word line by a word line coupling capacitance when the word line level down (wl_down) pulse signal levels down the adjacent word line to the Vbb potential. It was to be suppressed.

이와 같은 워드 라인 레벨 다운 신호를 발생하기 위한 구성은 도 8에서와 같이, RAS 버퍼(80)에 의한 내부 RAS 신호(int_ras)에 의해 레벨 다운 펄스를 발생하는 워드라인 레벨 다운 신호 발생 제어부(83)와, 어드레스 버퍼(81)를 거쳐 로우 프리 디코더(82)에서 출력되는 로우 어드레스 최하위 비트 디코딩 신호(ax0<0:1>)를 반전하는 제 1,2 인버터(86a)(86b)와, 상기 각각의 제 1,2 인버터(86a)(86b)의 출력 신호와 레벨 다운 펄스를 NAND 연산하는 제 1,2 NAND 연산부(87a)(87b)와, 제 1,2 NAND 연산부(87a)(87b)의 출력 신호를 반전하는 제 3,4 인버터(86c)(86d)와, 제 3,4 인버터(86c)(86d)의 반전 신호에 의해 각각 제 1,2 워드라인 레벨 다운 신호(wl_down<0>)(wl_down<1>)를 출력하는 제 1,2 VBB 레벨 변환부(85a)(85b)로 구성된다.As shown in FIG. 8, the word line level down signal generation controller 83 generates a level down pulse by the internal RAS signal int_ras by the RAS buffer 80. And first and second inverters 86a and 86b for inverting the row address least significant bit decoded signal ax0 <0: 1> output from the row free decoder 82 via the address buffer 81, Of the first and second NAND calculation units 87a and 87b for NAND operation of the output signals and the level down pulses of the first and second inverters 86a and 86b of the first and second inverters 86a and 86b; First and second word line level down signals wl_down <0> respectively by the inverted signals of the third and fourth inverters 86c and 86d and the third and fourth inverters 86c and 86d that invert the output signal. The first and second VBB level converters 85a and 85b output (wl_down <1>).

상기 제 1,2 VBB 레벨 변환부(85a)(85b)에서 출력되는 wl_down<0:1> 신호는 로우 어드레스를 디코딩하여 선택된 워드라인의 로우 어드레스의 최하위 비트인 x0가 0("L")인 경우 wl_down<1>이 인에이블되고 wl_down<0>는 인에이블되지 않으며, 반대로 x0가 1("H")인 경우 wl_down<0>이 인에이블되고 wl_down<1>은 인에이블되지 않는다.The wl_down <0: 1> signal output from the first and second VBB level converters 85a and 85b decodes a row address such that x0, the least significant bit of the row address of the selected word line, is 0 (“L”). If wl_down <1> is enabled and wl_down <0> is not enabled, on the contrary, if x0 is 1 ("H"), wl_down <0> is enabled and wl_down <1> is not enabled.

로우 어드레스 스크램블에 따라 로우 어드레스 최하위 비트인 x0에 의해 워드라인은 번갈아 위치하고 있기 때문에 특정 워드라인이 인에이블될때 항상 인접 워드라인의 서브 워드라인 드라이버에 wl_down신호가 인에이블되게 된다.Since the word lines are alternately positioned by the row address least significant bit x0 according to the row address scramble, when a specific word line is enabled, the wl_down signal is always enabled in the sub word line driver of the adjacent word line.

따라서, 도 9의 타이밍도에 나타낸 바와 같이 워드라인 인에이블시 커플링 커패시턴스에 의한 인접 워드라인의 순간적인 레벨 상승을 막아 셀 데이터 손실을 방지할 수 있다.Therefore, as shown in the timing diagram of FIG. 9, cell data loss can be prevented by preventing an instantaneous level rise of adjacent word lines due to coupling capacitance when word lines are enabled.

이와 같은 본 발명에 따른 반도체 메모리의 워드라인 구동 회로는 다음과 같은 효과가 있다.The word line driving circuit of the semiconductor memory according to the present invention has the following effects.

본 발명은 DRAM의 워드라인 인에이블시 선택된 워드라인에 순간적으로 Vbb 전위를 가하여 DRAM의 액티브 동작시 발생되는 워드라인 커플링 노이즈에 의한 데이터 손실을 방지함으로써 디바이스의 성능을 향상시킬 수 있다.The present invention can improve the performance of the device by preventing the data loss caused by word line coupling noise generated during the active operation of the DRAM by instantaneously applying the Vbb potential to the selected word line at the word line enable of the DRAM.

이는 인접 워드라인에 해당하는 셀 데이터의 손실을 막아 소자의 신뢰성을높이는 효과가 있다.This prevents the loss of cell data corresponding to adjacent word lines, thereby increasing the reliability of the device.

Claims (4)

복수개의 서브 셀 어레이를 포함하고, 복수개의 메인 워드 라인들과 복수개의 서브 워드 라인들을 갖는 메모리를 구동하는 회로에 있어서,A circuit for driving a memory comprising a plurality of sub cell arrays, the plurality of main word lines and a plurality of sub word lines, 각각의 메인 워드 라인과 서브 워드 라인들 사이에 그들에 대응하여,Corresponding to them between each main word line and sub word lines, 서로 직렬 연결되어 게이트가 공통으로 메인 워드 라인에 연결되고 출력단은 워드 라인에 공통으로 연결되는 PMOS 트랜지스터와 NMOS 트랜지스터 그리고 출력단에 일측 전극이 연결되고 타측 전극에는 음전위 vbb가 인가되고 게이트에 워드 라인 레벨 다운 신호가 인가되는 다른 NMOS 트랜지스터를 포함하여 서브 워드 라인 드라이버가 구성되고,PMOS transistor, NMOS transistor, and output terminal are connected to the main word line in common, and the output terminal is connected to the main word line in common, one electrode is connected to the output terminal, and the negative electrode is applied to the other electrode, and the word line level down to the gate. A sub word line driver is configured including other NMOS transistors to which a signal is applied, 상기 서브 워드 라인 드라이버에는 제 1,2 워드 라인 레벨 다운 신호 (wl_down<0>)(wl_down<1>)이 교번적으로 인가되어 인에이블되지 않은 인접 워드 라인의 레벨 상승을 억제하는 것을 특징으로 하는 반도체 메모리의 워드라인 구동 회로.The first and second word line level down signals wl_down <0> and wl_down <1> are alternately applied to the sub word line driver, thereby suppressing the level rise of adjacent word lines that are not enabled. Word line driver circuit in semiconductor memory. 제 1 항에 있어서, PMOS 트랜지스터의 소오스에는 vpp 전압이 인가되고 NMOS 트랜지스터의 소오스에는 vss 전압이 인가되는 것을 특징으로 하는 반도체 메모리의 워드라인 구동 회로.The word line driver circuit of claim 1, wherein a voltage of vpp is applied to a source of the PMOS transistor and a voltage of vss is applied to a source of the NMOS transistor. 제 1 항에 있어서, 워드 라인 레벨 다운 신호를 발생하기 위한 블록으로,The block of claim 1, further comprising: a block for generating a word line level down signal; 내부 RAS 신호(int_ras)에 의해 레벨 다운 펄스를 발생하는 워드라인 레벨 다운 신호 발생 제어부와,A word line level down signal generation controller configured to generate a level down pulse by an internal RAS signal int_ras; 로우 프리 디코더에서 출력되는 로우 어드레스 최하위 비트 디코딩 신호(ax0<0:1>)를 반전하는 제 1,2 인버터와,First and second inverters for inverting the row address least significant bit decoded signal ax0 <0: 1> output from the row free decoder; 상기 각각의 제 1,2 인버터의 출력 신호와 레벨 다운 펄스를 NAND 연산하는 제 1,2 NAND 연산부와,First and second NAND calculation units configured to perform NAND operations on output signals and level down pulses of the first and second inverters; 제 1,2 NAND 연산부의 출력 신호를 반전하는 제 3,4 인버터와,Third and fourth inverters for inverting output signals of the first and second NAND calculating units, 상기 제 3,4 인버터의 반전 신호에 의해 각각 제 1,2 워드라인 레벨 다운 신호(wl_down<0>)(wl_down<1>)를 출력하는 제 1,2 VBB 레벨 변환부로 구성되는 워드 라인 레벨 다운 신호 발생 블록을 포함하는 것을 특징으로 하는 반도체 메모리의 워드라인 구동 회로.Word line level down configured by first and second VBB level converters which output first and second word line level down signals wl_down <0> and wl_down <1> respectively by inverted signals of the third and fourth inverters. And a signal generation block. 제 3 항에 있어서, 제 1,2 VBB 레벨 변환부에서 출력되는 wl_down<0:1> 신호는 로우 어드레스를 디코딩하여 선택된 워드라인의 로우 어드레스의 최하위 비트인 x0가 0("L")인 경우 wl_down<1>이 인에이블되고 wl_down<0>는 인에이블되지 않으며, 반대로 x0가 1("H")인 경우 wl_down<0>이 인에이블되고 wl_down<1>은 인에이블되지 않는 것을 특징으로 하는 반도체 메모리의 워드라인 구동 회로.4. The method of claim 3, wherein the wl_down <0: 1> signal output from the first and second VBB level converters decodes a row address and x0, which is the least significant bit of the row address of the selected word line, is 0 ("L"). wl_down <1> is enabled and wl_down <0> is not enabled; conversely, if x0 is 1 ("H"), wl_down <0> is enabled and wl_down <1> is not enabled. Word line driver circuit in semiconductor memory.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100802057B1 (en) * 2006-08-11 2008-02-12 삼성전자주식회사 Word line driving circuit and method in semiconductor memory device
KR100884262B1 (en) * 2007-03-21 2009-02-17 엠텍비젼 주식회사 Word line decoder capable of preventing current from leaking
US7668014B2 (en) 2007-04-24 2010-02-23 Samsung Electronics Co., Ltd. Non-volatile memory device and program method
KR100980606B1 (en) * 2008-09-08 2010-09-07 주식회사 하이닉스반도체 Circuit and method for wordline driving
US8559227B2 (en) 2010-07-07 2013-10-15 Hynix Semiconductor Inc. Nonvolatile memory device
KR20200010884A (en) * 2018-07-23 2020-01-31 삼성전자주식회사 Memory device scrambling address

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6011746A (en) * 1997-02-06 2000-01-04 Hyundai Electronics America, Inc. Word line driver for semiconductor memories
KR100253277B1 (en) * 1997-02-19 2000-05-01 김영환 Hierarchy word line structure
JP3478953B2 (en) * 1997-09-03 2003-12-15 Ｎｅｃエレクトロニクス株式会社 Semiconductor storage device
KR100300031B1 (en) * 1997-11-11 2001-09-06 김영환 Circuit for driving word sine of semiconductor memoty
KR20010055932A (en) * 1999-12-13 2001-07-04 박종섭 A semiconductor memory device for stable sub-word line driving operation

Cited By (8)

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Publication number Priority date Publication date Assignee Title
KR100802057B1 (en) * 2006-08-11 2008-02-12 삼성전자주식회사 Word line driving circuit and method in semiconductor memory device
US7561488B2 (en) 2006-08-11 2009-07-14 Samsung Electronics Co., Ltd. Wordline driving circuit and method for semiconductor memory
KR100884262B1 (en) * 2007-03-21 2009-02-17 엠텍비젼 주식회사 Word line decoder capable of preventing current from leaking
US7668014B2 (en) 2007-04-24 2010-02-23 Samsung Electronics Co., Ltd. Non-volatile memory device and program method
KR100980606B1 (en) * 2008-09-08 2010-09-07 주식회사 하이닉스반도체 Circuit and method for wordline driving
US8559227B2 (en) 2010-07-07 2013-10-15 Hynix Semiconductor Inc. Nonvolatile memory device
KR20200010884A (en) * 2018-07-23 2020-01-31 삼성전자주식회사 Memory device scrambling address
US10957380B2 (en) 2018-07-23 2021-03-23 Samsung Electronics Co., Ltd. Memory device scrambling address

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