KR100300031B1 - Circuit for driving word sine of semiconductor memoty - Google Patents

Abstract

PURPOSE: A word line driving circuit of a semiconductor memory is provided to enhance an integration degree by reducing the number of signals needed to a word line driver, and simplify a circuit structure. CONSTITUTION: A row decoder(10) decodes upper predecoding signals(P4-Px), and generates a global word line enable signal(GWL). OR-gate(OR1) receives lower predecoding signals(P2,P3), performs OR operation about the signals(P2,P3), and generates an output signal(P23). A first word line driver(20) selects lower predecoding signals(P0,P1) or a ground potential, and outputs the selected one to a predetermined word line of a memory cell(40). The lower predecoding signals(P0,P1) are applied according to word line enable signals(WL0,WL1). An OR gate(OR2) receives the lower predecoding signals(P0,P1), performs OR operation about them, and outputs an output signals(P01). A second word line driver(30) selects lower predecoding signals(P2,P3) or a ground potential, and outputs the selected one to a predetermined word line of a memory cell(40). The lower predecoding signals(P2,P3) are applied according to word line enable signals(WL2,WL3). The OR gate(OR2) receives the lower predecoding signals(P0,P1).

Description

Word line driving circuit of semiconductor memory {CIRCUIT FOR DRIVING WORD SINE OF SEMICONDUCTOR MEMOTY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a word line driving circuit of a semiconductor memory, and more particularly, to improve the degree of integration by minimizing a line into which an input signal required for the operation of the word line driving circuit is input, and to a word line driving circuit of a semiconductor memory that is easy to arrange. will be.

In general, a semiconductor memory drives a word line to store data in a specific memory cell or to output data stored in the specific memory cell through a bit line according to a decoder for decoding an address of input data and an output of the decoder. The word line driver is configured to include a word line driver. The word line driver circuit of the conventional semiconductor memory will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a word line driver circuit of a conventional semiconductor memory. As shown in FIG. 10); Among the global word line enable signals of the row decoder 10, specific word line enable signals WL0, WL2, WL5, and WL7 and inverted word line enable signals WLB0, WLB2, and ( A first word line driver 20 for selectively outputting the lower predecoding signals P0 and P1 input in accordance with WLB5 and WLB7; Among the global word line enable signals GWL of the row decoder 10, specific word line enable signals WL1, WL3, (WL4), (WL6) and inverted word line enable signals WLB1, ( A second word line driver 30 for selectively outputting the lower pre-coded signals P2 and P3 according to WLB3), WLB4, and WLB6; A specific memory cell is enabled according to the lower pre-coding signal selected and output from the first word line driver 20 and the second word line driver 30 to store or store data in the enabled memory cell. The memory cell part 40 outputs through the lines BL0 to BL3.

The first and second word line drivers 20 and 30 and the memory cell unit 40 may be connected in plural as one unit as necessary.

FIG. 2 is a detailed configuration diagram of the first and second word line drivers 20 and 30 in FIG. 1, and as shown in FIG. 1, the first word line driver 20 is a word line enable signal WL0. And a first selector 21 for outputting a lower predecoding signal P0 or a ground potential to a specific word line of the memory cell unit 40 according to the inverted word line enable signal WLB0; The second selector 22 outputs the lower predecoding signal P1 or the ground potential to a specific word line of the memory cell unit 40 according to the word line enable signal WL1 and the inverted word line enable signal WLB1. Wow; The third selector 23 outputs the lower predecoding signal P0 or the ground potential to a specific word line of the memory cell unit 40 according to the word line enable signal WL0 and the inverted word line enable signal WLB0. Wow; The fourth selector 22 outputs the lower predecoding signal P1 or the ground potential to a specific word line of the memory cell unit 40 according to the word line enable signal WL1 and the inverted word line enable signal WLB1. It consists of.

The first selector 21 applies the lower predecoding signal P0 applied to each source and drain according to the word line enable signal WL0 and the inverted word line enable signal WLB0 applied to each gate. A pull-up PMOS transistor PM1 and a pull-up NMOS transistor NM1 which flow to each drain and source side; And a pull-down NMOS transistor NM2 having the drain and source sides of the pull-up PMOS transistor PM1 and the pull-up NMOS transistor NM1 grounded according to the word line enable signal WL0 applied to a gate. The second to fourth selectors 22 to 24 also include pull-up PMOS transistors P1-1 to P1-3, pull-up NMOS transistors NM1-1 to NM-3, and pull-down NMOS transistors NM2-1. It has the same structure as the said 1st selection part 22 including -NM2-3).

In addition, the second word line driver 30 includes four selectors 31 to 34, similarly to the first word line driver 20.

Hereinafter, the operation of the word line driver circuit of the conventional semiconductor memory configured as described above is limited to the operation of the first and second selectors 21 and 22 of the first word line driver 20 for convenience of description.

First, an address signal is input from a predecoder (not shown) to predecode the predecoded signals P0 to Px.

Next, higher predecoding signals P4 to Px of the predecoded signals P0 to Px of the predecoder are input to the row decoder 10, decoded, and output as the global word line enable signal GWL. As such, the global word line enable signal GWL is a set of a plurality of word line enable signals and is illustrated as one line for convenience of description.

At the same time, the lower pre-coded signals P0 to P3 of the pre-coded signals P0 to Px are inputted to the first and second word line drivers 20 and 30 to provide a plurality of selectors 21 respectively. 24, 31, and 34, respectively.

At this time, when the word line enable signal WL0 and the inverted word line enable signal WLB0 input to the first selector 21 provided in the first word line driver 20 are respectively input at high potential and low potential, The pull-up PMOS transistor PM1 and the pull-up NMOS transistor NM1, which receive the word line enable signal WL0 and the inverted word line enable signal WLB0 to their respective gates, are turned off to lower pre-coding signals. The application of P0 is blocked, and the pull-down NMOS transistor NM2 is turned on by the high potential word line enable signal WL0. Thus, a low potential signal is applied to a specific word line of the memory cell unit 40. Is applied. That is, the memory cell receiving the low potential signal output from the first selector 21 through the specific word line is not enabled.

When the inverted word line enable signal WLB0 is applied at a high potential, the pull-up PMOS and NMOS transistors PM1 and NM1 are turned on when the word line enable signal WL0 inverts the low potential. The MOS transistor NM2 is turned off, and the first selector 21 selects and outputs the high pre-lower predecoding signal P0.

Accordingly, certain memory cells of the memory cell unit 40 that receive the lower pre-coding signal P0, which is an output signal of the first selector 21, are enabled to store data or to store the stored data. It is output through the bit lines BL0 to BL3 to the outside.

As described above, when the word line enable signal WL1 is applied with the low potential and the inverted word line enable signal WLB1 with the high potential, the pull-up PMOS and the pull-up NMOS transistor PM1 are applied. -1) and (NM1-1) are turned on, and the pull-down NMOS transistor NM2-1 is turned off to output the lower predecoding signal P1.

3 is another embodiment of a word line driving circuit of a conventional semiconductor memory. As shown in FIG. 3, the upper predecoding signals P4 to Px are received and decoded to output a global word line enable signal GWL. A row decoder 10; Among the global word line enable signals GWL, the lower pre-coded signals P0 and P1 or ground potentials applied according to specific word line enable signals WL0 and WL1 and the inverted lower pre-coded signals PB0 and PB1 may be applied. A first word line driver 20 for selecting and outputting the selected word; Among the global word line enable signals GWL, the lower pre-coded signals P2 and P3 or ground potentials applied according to specific word line enable signals WL2 and WL3 and the inverted lower pre-coded signals PB2 and PB3 are applied. And a second word line driver 30 for selecting and outputting the selected word.

FIG. 4 is a detailed configuration diagram of the first and second word line drivers 20 and 30 in FIG. 3. As shown in FIG. 3, the first word line driver 20 is a word line enable signal ( When WL0 is applied at low potential and the inverted low predicate coding signal PB0 is applied at low potential, it outputs a high potential low predicate coding signal P0, and grounds when the word line enable signal WL0 is at high potential. A first selector 21 for outputting a potential; When the word line enable signal WL1 is applied at a low potential and the inverted low predicoding signal PB1 is applied at a low potential, the word line enable signal WL1 is outputted, and the word line enable signal WL1 is output. A second selector 22 which outputs a ground potential when Δ is a high potential; When the word line enable signal WL0 is applied at a low potential and the inverted low predecoding signal PB0 is applied at a low potential, a low potential pre-coding signal P0 is output, and the word line enable signal WL0 is output. A third selector 23 which outputs a ground potential when Δ is a high potential; When the word line enable signal WL1 is applied at a low potential and the inverted low predicoding signal PB1 is applied at a low potential, the word line enable signal WL1 is outputted, and the word line enable signal WL1 is output. ) Is configured as a fourth selector 24 for outputting a ground potential when each of the high potentials is high. Each of the selectors 21 to 24 may include one pull-up PMOS transistor (PM1, PM1-1 to PM1-3). Two pull-down NMOS transistors NM1, NM1-1 through NM1-3 and NM2, NM2-1 through NM2-3 are configured.

The second word line driver 30 includes four selectors 31 to 34, similarly to the first word line driver 20.

Hereinafter, for convenience of description of the operation of another embodiment of the word line driving circuit of the conventional semiconductor memory configured as described above, the operation of the first and second selection units 21 and 22 will be described.

First, a predecoder (not shown) receives an address signal and decodes it to output predecoded signals P0 to Px.

Next, the row decoder 10 decodes the higher predicate coded signals P4 to Px among the precoded signals P0 to Px and outputs a global word line enable signal GWL.

Next, the word line enable signal WL0 of the global word line enable signal GWL of the row decoder 10 is input to the first selector 21. That is, the pull-up PMOS transistor PM1 and the pull-down NMOS transistor NM1 are applied to the gates, and the inverted lower predecoding signal PB0 is applied to another pull-down NMOS transistor NM2, and the pull-up PMOS transistor ( When the lower predecoding signal P0 is applied to the source of PM1 so that the word line enable signal WL0 has a high potential, it is related to the lower preprecoding signal P0 and the inverted lower predecoding signal P1. When the first selector 21 outputs the ground potential to a specific word line of the memory cell unit 40, and the word line enable signal WL1 is low potential and the inverted lower predicoding signal PB0 is low potential. The pull-up PMOS transistor PM1 is turned on, and both the pull-down NMOS transistors NM1 and NM2 are turned off, so that the high-precision lower predecoding signal P0 is applied to a specific word line of the memory cell unit 40. Is output.

Similar to the operation of the first selector 21, the second selector 22 also has a high potential Freddie when the word line driving signal WL1 is applied with a low potential and an inverted lower predicoding signal PB1 with a low potential. The coded signal P1 is output through a specific word line of the memory cell unit 40.

As described above, six signals must be input to the word line driver of the word line driver circuit of the conventional semiconductor memory for its operation.

As described above, in the word line driver circuit of the conventional semiconductor memory, the number of signals required for the operation of the word line driver is large, resulting in a complicated circuit and a reduction in the degree of integration.

It is an object of the present invention to provide a word line driving circuit of a semiconductor memory which reduces the number of signals required by a word line driver.

1 is a view showing an embodiment of a word line driver circuit of a conventional semiconductor memory.

2 is a detailed configuration diagram of a word line driver in FIG.

Figure 3 is another embodiment of the word line driver circuit of the conventional semiconductor memory.

4 is a detailed configuration diagram of a word line driver in FIG.

Fig. 5 is a word line driver circuit diagram of the semiconductor memory of the present invention.

FIG. 6 is a diagram of one embodiment of a word line driver in FIG. 5; FIG.

7 is another embodiment of the word line driver in FIG. 5;

8 is another embodiment of the word line driver in FIG. 5;

*** Description of the symbols for the main parts of the drawings ***

10: low decoder 20: first word line driver

30: second word line driver 40: memory cell unit

21 to 24: first to fourth selectors 31 to 34: fifth to eighth selectors

The purpose of the above is to receive and decode the upper pre-coded signal to output a global word line enable signal; A first ora gate configured to receive the lower pre-coded signal and combine the ordinal signals to output an output signal; A first word line that selects a lower pre-coding signal or ground potential applied according to two word line enable signals among the output signal of the first or gate and the global word line enable signal and outputs the same through a specific word line of a memory cell unit; A drive unit; A second oar gate configured to receive the lower pre-coded signal and combine them or output the output signal; The second word line driver is configured to output a lower predecoding signal or ground potential applied according to a word line enable signal among the output signal of the second or gate and the global word line enable signal through a specific word line. This is achieved by using the output signals of the first and second oA gates as a means for controlling the output signals of the first and second word line drivers. The present invention will be described in detail with reference to the accompanying drawings. As follows.

FIG. 5 is a word line driving circuit diagram of the semiconductor memory of the present invention. As shown in FIG. 5, the row decoder 10 that receives and decodes the upper predecoding signals P4 to Px and outputs the global word line enable signal GWL. Wow; An OR gate OR1 for receiving the lower pre-coding signals P2 and P3 and performing oral combination to output the output signal P23; Lower predecoding signals P0 and P1 or ground potentials applied according to word line enable signals WL0 and WL1 of the output signal P23 of the OR gate OR1 and the global word line enable signal GWL. A first word line driver 20 for selecting and outputting the selected word line through the specific word line of the memory cell unit 40; An OR gate OR2 which receives the lower pre-coding signals P0 and P1 and outputs an output signal P01 by combining or receiving them; The lower pre-decoding signal P2, P3 or ground potential applied according to the word line enable signals WL2 and WL3 among the output signal P01 of the oragate OR2 and the global word line enable signal GWL The second word line driver 30 outputs a specific word line of the memory cell unit 40, and further includes a plurality of word line driver units and a memory cell unit as necessary.

FIG. 6 is a diagram illustrating an embodiment of the first and second word line drivers 20 and 30 in FIG. 5, and as shown therein, the first word line driver 20 outputs the OR gate OR1. A first selector 21 outputting a lower predecoding signal P0 or a ground potential applied according to the signal P23 and the word line enable signal WL0 through a specific word line of the memory cell unit 40; The lower pre-decoding signal P1 or ground potential applied according to the output signal P23 of the OR gate OR1 and the word line enable signal WL1 is selected to be output through a specific word line of the memory cell unit 40. A second selection unit 22; A second pre-coding signal P0 or ground potential applied according to the output signal P23 of the OR gate OR1 and the word line enable signal WL0 through a specific word line of the memory cell unit 40. 3 selector 23; The lower pre-decoding signal P1 or ground potential applied according to the output signal P23 of the OR gate OR1 and the word line enable signal WL1 is selected to be output through a specific word line of the memory cell unit 40. Is composed of a fourth selector 24.

The first selector 21 includes a pull-up PMOS transistor PM1 that receives a lower pre-decoding signal P0 from a source and is electrically controlled according to a word line enable signal WL0 applied to a gate thereof; A pull-down NMOS transistor NM1 whose drain is connected to the drain of the pull-up PMOS transistor PM1 and which is electrically controlled according to the enable signal WL0 applied to a gate; A drain is connected to the drain of the pull-up PMOS transistor PM1, and constitutes a pull-down NMOS transistor NM2 that is electrically controlled according to the output signal P23 of the OR gate OR1. Also, the first selector 21 includes pull-up PMOS transistors PM1-1 to PM1-3, pull-down NMOS transistors NM1-1 to NM1-3, and NM2-1 to NM2-3. It is configured the same as).

The second word line driver 30 also includes four selectors 31 to 34 to be configured in the same manner as the first word line driver 30.

Hereinafter, the word line driver circuit of the semiconductor memory of the present invention configured as described above will be described in detail with reference to the operations of the first and second selectors 21 and 22 provided in the first word line driver 20 for convenience of description. As follows.

First, the predecoder (not shown) decodes the input address signal and outputs the predecoded signals P0 to Px.

Next, the row decoder 10 receives and decodes the higher predicate coded signals P4 to Px among the predecoded signals P0 to Px and outputs the global word line enable signal GWL.

At this time, the OR gate, which receives the lower pre-code signals P2 and P3 among the pre-code signals P0 to Px, outputs an output signal P23 by combining the input signals.

Next, the first word line driver 20 receiving the output signal P23 of the oragate OR1 and the global word line enable signal GWL is applied to the lower predecoding signal applied according to the input signal. (P0, P1) or ground potential is selected and output through the specific word line of the memory cell unit 40.

That is, in the case of the first selector 21, when the word line enable signal WL0 is applied at a high potential, the pull-down NMOS transistor NM1 is turned on so that the oragate OR1 output signal P23 and the lower predye are turned on. Regardless of the value of the coding signal P0, the ground potential is output through a specific word line. When the word line enable signal WL0 is applied at a low potential, the pull-up PMOS transistor PM1 is turned on and pulled down. The NMOS transistor NM1 is turned off so that the lower predecoding signal P0 applied through the pull-up PMOS transistor PM1 is output through the word line, but the value is represented by the output signal of the OR gate OR1. P23).

That is, when the output signal P23 of the OR gate OR1 is applied at high potential, the pull-down NMOS transistor NM2 is turned on so that the lower predecoding signal P0 applied to a specific word line flows to ground. As a result, the ground potential is applied to the specific word line, and if the output signal P23 of the OR gate OR1 is low, the lower pre-decoding signal is applied to the specific word line, thereby enabling the memory cells connected to the word line. Let's do it.

The second selector 22 also selectively selects a lower pre-decoding signal P1 or ground potential according to a word line enable signal WL1 and an output signal P23 of the OR gate OR1. To apply.

By this operation, the word line driver does not need to use the inverted global word line enable signal or the inverted signal applied to control the operation of the pull-down transistor of each complementary word line driver. The number of signals to be reduced can be reduced.

Similarly to the operations of the first and second selectors 21 and 22, the third and fourth selectors 23 and 24 also specify a lower predecoding signal P0 or P1 or a ground potential in a word line. The second word line driver also performs the same operation to enable a specific memory cell included in the memory cell unit 40.

The data applied through the bit lines BL0 to BL3 are stored in the enabled memory cells, or the data already stored is output through the bit lines BL0 to BL3.

FIG. 7 is a diagram showing another embodiment of the first and second word line drivers 20 and 30 in FIG. 5, and as shown in FIG. 5, the first word line driver 20 is formed of the oragate OR1. A first selector 21 for outputting a lower predecoding signal P0 or ground potential applied according to the output signal P23 and the word line enable signal WL0 through a specific word line of the memory cell unit 40; ; A second selector 22 that selects a lower pre-coding signal P1 or ground potential applied according to the word line enable signal WL1 and outputs the selected pre-coding signal P1 or ground potential through a specific word line of the memory cell unit 40; A third selector 23 outputting a lower predecoding signal P0 or a ground potential applied according to the word line enable signal WL0 through a specific word line of the memory cell unit 40; An NMOS transistor NM4 which is electrically controlled according to the output signal of the OR gate to make the output signals of the second selector 22 and the third selector 23 equal to each other; A fourth selector 24 which selects a lower pre-decoding signal P1 or ground potential applied according to the word line enable signal WL1 and outputs the selected pre-coding signal P1 or ground potential through a specific word line of the memory cell unit 40; The NMOS transistor NM7 is electrically controlled according to the output signal of the OR gate OR1 to make the output signal of the fourth selector 24 and the subsequent selector (not shown) the same value. .

The first selector 21 includes a pull-up PMOS transistor PM1 that receives a lower pre-decoding signal P0 from a source and is electrically controlled according to a word line enable signal WL0 applied to a gate thereof; A pull-down NMOS transistor NM1 whose drain is connected to the drain of the pull-up PMOS transistor PM1 and which is electrically controlled according to the enable signal WL0 applied to a gate; A drain is connected to the drain of the pull-up PMOS transistor PM1, and is composed of a pull-down NMOS transistor NM2 that is electrically controlled according to the output signal P23 of the OR gate OR1, and the second to fourth selections are selected. The units 22 to 24 are pull-up PMOS transistors PM1-1 to PM1-3 and pull-down NMOS transistors NM1- that are conductively controlled according to word line enable signals WL1, WL0, and WL1, respectively. 1 ~ NM1-3).

The second word line driver 30 includes a plurality of selectors 31 to 34 and an NMOS transistor NM to have the same configuration as that of the first word line driver 30. The signal GWL is applied through a signal line formed in the memory cell unit 40 to operate.

FIG. 8 is another embodiment of the first and second word line drivers 20 and 30 in FIG. 5, which has the same structure as that shown in FIG. The global word line enable signal GWL passing through the line driver 20 is intersected in the memory cell unit 40 and applied to the second word line driver 30.

The operation of the word line driver circuit of the semiconductor memory of the present invention as described above will be described.

The basic operation is the same as that of the embodiment shown in Fig. 5, and the second selector 22 and the third selector 22 provided in the first wordline driver 20 whose output signals are controlled according to the same wordline enable signal. The output signal of the selector 23 is maintained at the same value through the NMOS transistor NM4, which is electrically controlled according to the output signal P23 of the OR gate OR1 which combines the predicoding signals P2 and P3. .

That is, the predecoder (not shown) which precodes the address signal selects one of the lower predecoded signals P0 to P4 and outputs them at high potential to output the output signal P23 of the oragate OR1 or the oragate OR2. Output signal P01 is output at high potential.

If the pre-coding signal P1 is applied at a high potential and the word line enable signal WL1 is at a low potential, the second selector 22 supplies the high-precision pre-coding signal P1 to the memory cell unit 40. The third selector 23 also outputs a predicoding signal P1 having a high potential in the same operation as the second selector 22. At this time, the NMOS transistor NM4 having the source and the drain connected to the output terminal of the second selector 22 and the third selector 23 is turned off because the output signal P23 of the OR gate OR1 is low potential. It is a state.

At this time, since the pull-down NMOS transistor NM2 provided in the first selector 21 is also in an off state, the word line connected to the first selector 21 is in a floating state and is coupled according to the potential of another wordline. You are more likely to receive ring noise.

However, the first selection is performed by the pull-down NMOS transistor NM5 provided in the fifth selector 31 of the second word line driver 30 and connected to the output signal P01 of the high-order OA gate OR1. Since the word line closest to the word line connected to the selector 21 is in a ground state, coupling noise does not occur, and noise may occur due to the operation of the bit lines BL0 to BL3, but the bit line pair BL0, Since BL1) and BL2 and BL3 always operate in opposite directions, there is no average noise of the word line connected to the first selector 21.

In this state, when the precoding signal P2 is applied at high potential and the word line enable signal WL1 is applied at high potential, the pull-down NMOS of the second selector 22 and the third selector 23 is applied. The transistors NM1-1 and NM1-2 are turned on, and their output is grounded. In this case, conventionally, the speed of the word line to the ground is increased by using two pull-down NMOS transistors having the specific word line as the ground. However, in the present invention, the conduction is conducted by the high potential output signal P23 of the OR gate OR1. By using the controlled NMOS transistor NM4, the output side of the second and third selectors 22, 23 can be quickly grounded.

That is, a pull-down MOS connected to each word line driver is connected by connecting the output side of the word line driver receiving different global word line enable signals GWL to one NMOS transistor and controlling the result by the combined pre-coding signal. The number of transistors can be reduced.

As described above, the word line driver circuit of the present invention includes an ora gate to orthically combine lower pre-coded signals, and use the combined signal as a means for limiting an output signal of the word line driver to thereby limit the number of pulldown transistors and words. By reducing the number of signals input to the line driver, there is an effect of simplifying the circuit and improving the degree of integration.

Claims (10)

A row decoder which receives the upper precoded signals P4 to Px and decodes them to output a global word line enable signal; A first ora gate which receives lower pre-coding signals P2 and P3 and combines or outputs an output signal; A specific word of the memory cell unit is selected by selecting a lower pre-decoding signal P0 or P1 or a ground potential applied according to the word line enable signals WL0 and WL1 among the output signal of the first or gate and the global word line enable signal. A first word line driver to output the line; A second oar gate that receives the lower pre-coded signals P0 and P1 and outputs an output signal by combining the lower pre-coded signals P0 and P1; Among the output signals of the second or gate and the global word line enable signal, the lower pre-coding signals P2 and P3 or the ground potential applied according to the word line enable signals WL2 and WL3 are transmitted through a specific word line of the memory cell unit. And a second word line driver for outputting the word line driver circuit of the semiconductor memory. The specific word line of the memory cell unit according to claim 1, wherein the first word line driver comprises a lower pre-decoding signal P0 or a ground potential applied according to the output signal of the first or gate and the word line enable signal WL0. A first selector for outputting through; A second selector configured to select a lower pre-decoding signal P1 or ground potential applied according to the output signal of the first or gate and the word line enable signal WL1 and output the selected pre-coding signal through a specific word line of the memory cell unit; A third selector configured to output a lower predecoding signal P0 or a ground potential applied according to the output signal of the first or gate and the word line enable signal WL0 through a specific word line of the memory cell unit; And a fourth selector configured to select a lower pre-decoding signal P1 or ground potential applied according to the output signal of the first or gate and the word line enable signal WL1, and output the same through a specific word line of the memory cell unit. And a word line driving circuit of a semiconductor memory. 2. The word line driver of claim 1, wherein the second word line driver comprises a lower pre-decoding signal P2 or a ground potential applied according to the output signal of the second or gate and the word line enable signal WL2. A fifth selector for outputting through; A sixth selector which selects a lower pre-coding signal P3 or ground potential applied according to the output signal of the second or gate and the word line enable signal WL3 and outputs the selected voltage line through a specific word line of the memory cell unit; A seventh selector configured to output the lower predecoding signal P2 or the ground potential applied according to the output signal of the second or gate and the word line enable signal WL2 through a specific word line of the memory cell unit; And an eighth selector which selects a lower pre-decoding signal P3 or ground potential applied according to the output signal of the second or gate and the word line enable signal WL3 and outputs it through a specific word line of the memory cell unit. And a word line driving circuit of a semiconductor memory. 4. The apparatus of claim 2 or 3, wherein the first to eighth selectors include: a pull-up PMOS transistor and a pull-down NMOS transistor, each of which is electrically controlled by a global word line enable signal of the row decoder; And a pull-down NMOS transistor conductingly controlled by the output signal of the first or second OA gate. The word pre-coding signal P0 or ground potential of the first word line driver is applied according to the output signal of the first or gate and the word line enable signal WL0. A first selector outputting the line; A second selector which selects a lower pre-decoding signal P1 or a ground potential applied according to the word line enable signal WL1 and outputs the selected pre-coding signal P1 through a specific word line; A third selector for outputting a lower predecoding signal P1 or a ground potential applied according to the word line enable signal WL1 through a specific word line of the memory cell unit; And a first NMOS transistor configured to equalize an output signal of the second selector and the third selector according to the output signal of the first oragate. 2. The word line driver of claim 1, wherein the second word line driver comprises a lower pre-decoding signal P2 or a ground potential applied according to the output signal of the second or gate and the word line enable signal WL2. A fourth selector for outputting through; A fifth selector which selects the lower pre-decoding signal P3 or the ground potential according to the word line enable signal WL3 and outputs the selected pre-coding signal through the specific word line of the memory cell unit; A sixth selector configured to output a lower predecoding signal P3 or a ground potential applied according to the word line enable signal WL3 through a specific word line of the memory cell unit; And a second NMOS transistor configured to be conductively controlled in accordance with the output signal of the second OA gate to equalize the output signal of the fifth and sixth selectors. 6. The apparatus of claim 5, wherein the first selector comprises: a pull-up PMOS transistor and a pull-down NMOS transistor electrically controlled by a word line enable signal WL0; And a pull-down NMOS transistor conductingly controlled by the output signal of the first OA gate. 6. The word line drive circuit of a semiconductor memory according to claim 5, wherein the second and third selectors comprise a pull-up PMOS transistor and a pull-down NMOS transistor which are electrically controlled according to the word line enable signal WL1. in. 7. The device of claim 6, wherein the fourth selector comprises: a pull-up PMOS transistor and a pull-down NMOS transistor that are electrically controlled by a word line enable signal (WL2); And a pull-down NMOS transistor conductingly controlled by the output signal of the second OA gate. 7. The word line driving circuit of the semiconductor memory according to claim 6, wherein the fifth and sixth selectors comprise a pull-up PMOS transistor and a pull-down NMOS transistor that are electrically controlled according to the word line enable signal WL3. in.