KR100399975B1 - A positive charge pumping voltage switching circuit and a row decoder circuit of a flash memory using the same - Google Patents

Abstract

The present invention relates to a positive charge pumping voltage switching circuit capable of improving write time characteristics of a flash memory and a row decoder circuit of the flash memory using the same.

The present invention uses a positive charge pumping circuit for inputting a power supply voltage and outputting a positive charge pumping voltage according to a positive charge pumping enable signal, and the power supply voltage and the positive charge pumping voltage as inputs, and according to the VPPY enable signal. A VPPY switching block for outputting a pumping voltage, the power supply voltage and the positive charge pumping voltage are respectively input, and outputting even and odd VPPX pumping voltages according to a VPPX enable signal, even sector selection signal and odd sector selection signal. It provides a positive charge pumping voltage switching circuit including a VPPX switching block for.

Description

Positive charge pumping voltage switching circuit and a row decoder circuit of a flash memory using the same}

The present invention relates to a positive charge pumping voltage switching circuit capable of improving write time characteristics of a flash memory and a row decoder circuit of the flash memory using the same.

In general, a higher voltage level than the power supply voltage VCC is required in the program mode and the program verify mode in the write mode of the flash memory. Since the power supply of the chip uses a single power, the pumping operation is performed in the chip, and the pumping voltage is selectively switched to supply the selected cell. In particular, the program time in the flash memory is an important parameter of the write characteristic, and it is important to reduce the program time. Methods for reducing program time include device aspects that improve the characteristics of unit devices and design aspects that reduce pumping time.

1 is a diagram of a conventional positive charge pumping voltage switching circuit.

The positive charge pumping circuit 1 having the power supply voltage VCC as an input outputs the positive charge pumping voltage VPP according to the positive charge pumping enable signal VPPEN. The VPPY switching block 2 inputs the power supply voltage VCC and the positive charge pumping voltage VPP, respectively, and outputs the VPPY pumping voltage VPPY according to the VPPY enable signal VPPYEN.

In addition, the VPPX switching block 3 receives the power supply voltage VCC and the positive charge pumping voltage VPP, respectively, and according to the sector signal SECTOR <0: n> and the VPPX enable signal VPPXEN. The pumping voltage VPPX <0: n> is outputted.

For example, the first sector signal SECTOR <0> of the sector signals SECTOR <0: n> is enabled, and all other sector signals SECTOR <1: n> are disabled. Assuming that both the state and the VPPY enable signal VPPYEN and the VPPX enable signal VPPYEN are enabled, the VPPY switching block 2 is pumped VPPY by the VPPY enable signal VPPYEN. Outputs the voltage VPPY.

In addition, the VPPX switching block 3 enables only the first VPPX switching block VPPX0 by the first sector signal SECTOR <0> and the VPPX enable signal VPPXEN, and all other VPPX switching blocks. (VPPX <1: n>) is disabled.

Therefore, the first VPPX switching block VPPX <0> outputs the VPPX pumping voltage VPPX0, and the other VPPX switching blocks VPPX <1: n> output the VCC voltage. That is, loading of the output VPP of the positive charge pumping circuit 1 is determined by the loading of the selected VPPX switching block and the VPPY switching block, thereby increasing the loading.

3 is a row decoder circuit diagram using a conventional positive charge pumping voltage switching circuit.

One sector 5 is composed of a main row decoder 6 composed of a plurality of row decoder drivers <0: n> and a redundancy row decoder 7, respectively.

The main row decoder 6 and the redundancy row decoder 7 in the sector 5 are the outputs of the first and second voltage sources VPPX and VEEX, the reset signal XRSTb and the low pre-decoder (not shown). A control signal XPREDA <0: n> is input, respectively, and second and third control signals XPREDB <0: m> and XPREDC <0: k>, which are outputs of the low pre-decoder, and sector selection The output signals XCOMb0 and XCOMbkm of the three-input NAND gates I0 and Iokm, which respectively input signals SECTOR, are input.

In the conventional row decoder circuit, the second and third control signals XPREDB <0: m> and XPRDC <0: k>, which are outputs of a row pre-decoder (not shown), which are a combination of row addresses, have three input NAND. The output signals XCOMb0 and XCOMbkm of the three input NAND gates I0 and Iokm are used as inputs of the gates I0 and Iokm, and the inputs of the main row decoder and the redundancy row decoders 6 and 7 of the sector 5 are used. Since it is used as a load, the loading of the second and third control signals XPREDB <0: m> and XPRDC <0: k>, which are output signals of the low pre-decoder, becomes large, thereby pumping time. This takes a long time.

Accordingly, the present invention configures two or more positive charge pumping voltage switching circuits in one sector to enable only selected switching blocks in a selected sector, and the row decoder driver is driven by a voltage output from the enabled selected switching blocks. It is an object of the present invention to provide a switching circuit of a positive charge pumping voltage and a row decoder circuit of a flash memory using the same which can solve the above disadvantages.

The positive charge pumping voltage switching circuit according to the present invention for achieving the above object is a positive charge pumping circuit for inputting a power supply voltage and outputting a positive charge pumping voltage according to a positive charge pumping enable signal, and the power supply voltage and A positive charge pumping voltage is input and a VPPY switching block for outputting the VPPY pumping voltage according to the VPPY enable signal, the power supply voltage and the positive charge pumping voltage, respectively, and a VPPX enable signal, an even sector selection signal, and And a VPPX switching block for outputting even and odd VPPX pumping voltages according to the odd sector selection signal.

In addition, the row decoder circuit of the flash memory using the positive charge pumping voltage switching circuit according to the present invention for achieving the above object is a logic means for inputting each control signal and sector selection signal output from the low pre-decoder, respectively. And any of the even and odd VPPX pumping voltages supplied from the precharge pumping voltage switching circuit and the voltage supplied from either voltage source according to the control signal output from the logic means and another control signal output from the low pre-decoder. And a main row decoder and a redundancy row decoder for selectively outputting a voltage.

According to the present invention, a positive charge pumping voltage is applied to a selected word line (W / L) of a selected sector in a program and a program check mode of a flash memory, and a 0V voltage is applied to other word lines (W / L). The word line is selected.

That is, by configuring a switching circuit for delivering the positive charge pumping voltage only to a portion where the selected word lines are grouped, the pumping time can be shortened by reducing the output loading of the positive charge pump.

signal Standby Read Program Pgm.Ver Erase Recovery Erase Ver Remarks VPP GEN. Print VCC VCC VPP VPP VPE VCC VCC VCC> VPE VPPY VCC VCC VPP VCC VCC VCC VCC VPPX selected VCC VCC VPP VPP VPE VCC VCC Non-selected VPPX VCC VCC VCC VCC VCC VCC VCC

[Table 1] summarizes the output level and selection of positive charge pumping according to each mode, and the levels of VPPX and VPPY that are not selected.The output of the VPPX switching block selected in the program mode and program check mode is the positive charge pumping voltage level. It can be seen that the output of the other non-selected VPPX switching block is at the VCC voltage level.

1 is a conventional positive charge pumping voltage switching circuit diagram.

2 is a positive charge pumping voltage switching circuit in accordance with the present invention.

3 is a row decoder circuit diagram using a conventional positive charge pumping voltage switching circuit.

4 is a row decoder circuit using a positive charge pumping voltage switching circuit in accordance with the present invention.

5 is a detailed circuit diagram of a row decoder driver applied to the prior art and the present invention.

6 is a waveform diagram of a simulation result of a row decoder circuit according to the related art and the present invention;

<Explanation of symbols for the main parts of the drawings>

11: Positive charge pumping circuit 12: VPPY switching block

13: VPPX switching blocks 14, 15: storm and odd switching blocks

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a positive charge pumping voltage switching circuit in accordance with the present invention.

The positive charge pumping circuit 11 having the power supply voltage VCC as an input outputs the positive charge pumping voltage VPP according to the positive charge pumping enable signal VPPEN. The VPPY switching block 12 receives the power supply voltage VCC and the positive charge pumping voltage VPP, respectively, and outputs the VPPY pumping voltage VPPY according to the VPPY enable signal VPPYEN.

In addition, the VPPX switching block 13 receives the power supply voltage VCC and the positive charge pumping voltage VPP, respectively, and the VPPX enable signal VPPXEN and the even (even) and odd (odd) sector selection signals ( It consists of an even switching block 14 and an odd switching block 15 for outputting even and odd VPPX pumping voltages VPPX0_Even to VPPX0_Odd to VPPXn_Odd according to SECTOR0_Even to SECTORn_Even and SECTOR0_Odd to SECTORn_Odd.

In the present invention, for the convenience of description, the first even switching block VPPX0_Even; ) And the odd switching block VPPX0_Odd 15 will be described as an example.

The even sector selection signal SECTOR0_Even is enabled, the odd sector selection signal SECTOR0_Odd is disabled, and both the VPPY enable signal VPPYEN and the VPPX enable signal VPPXEN are enabled. Assuming the Enable state, the VPPY switching block 12 outputs a VPPY pumping voltage VPPY by the VPPY enable signal VPPYEN.

In addition, only the even switching block 14 is enabled by the even sector selection signal SECTOR0_Even and the VPPX enable signal VPPXEN, and the odd switching block 15 is disabled in the VPPX switching block 13. .

That is, the positive charge pumping voltage switching circuit of the present invention separates the VPPX switching block 13 into an even and odd switching blocks 14 and 15, respectively, and each sector selection signal (SECTOR0 to SECTORn in FIG. 1) is excellent. And the odd sector selection signals SECTOR0_Even to SECTORn_Even and SECTOR0_Odd to SECTORn_Odd to reduce the loading of the output node of the positive charge pumping circuit 11 to 1/2. This is because the even and odd row decoder drivers driven can be separated by outputting the sector signal separated by even and odd numbers and the VPP pumping voltage supplied to the low decoder through the VPPX switching block 13 by being divided into even and odd numbers. to be. Hereinafter, the row decoder will be described based on the drawings.

4 is a row decoder circuit diagram using a positive charge pumping voltage switching circuit according to the present invention.

One sector 18 includes a main row decoder 19 composed of a plurality of row decoder drivers XDECDRV0 to XDECDRVn and a redundancy row decoder 20, respectively.

The main row decoder 19 and the redundancy row decoder 20 in the sector 18 are the first control signal XPREDA which is the output of the second voltage source VEEX, the reset signal XRSTb, and a low pre-decoder (not shown). <0: n> are input, respectively, and the second and third control signals XPREDB <0: m> and XPREDC <0: k> and the sector selection signal SECTOR, which are outputs of the low pre-decoder, are input. The output signals XCOMb0 and XCOMbkm of the logic means In0 and Inkm, respectively, as inputs, are input. The logic means In0 and Inkm consist of three input NAND gates. In addition, the main row decoder 19 and the redundancy row decoder 20 are composed of even and odd row decoder drivers, and the even and odd VPPX pumping voltages VPPX_Even and are supplied from the precharge pumping voltage switching circuit of FIG. 2. VPPX_Odd) is supplied.

For example, when the least significant bit LSB of the address for selecting the row decoder is selected as the low level, and the first sector Sector 0 is selected to perform the program and the program check operation, The even VPPX pumping voltage VPPX0_Even, which is the output of the even VPPX switching block VPPX0_Even, is supplied to the even low decoder driver of FIG. And all other outputs of the VPPX switching block are output with the VCC voltage. Therefore, the positive charge pumping voltage is supplied to the word line (W / L) of the even-lower decoder driver of FIG. 4, and the OV voltage is applied to the word line (W / L) of the even-decoder driver of the non-selected even-lower decoder. Is supplied. In addition, the odd VPPX pumping voltage VPPX_Odd, which is a VCC level, is supplied to the word line W / L of the odd row decoder to be unselected.

Finally, according to the present invention, during the loading of the positive charge pumping voltage switching circuit of the selected sector, the positive charge pumping circuit is reduced by reducing the loading to the positive charge pumping voltage switching circuit of the unselected word line (W / L) by half. This will improve the loading of the output.

5 is a detailed circuit diagram of a row decoder driver applied to the prior art and the present invention.

The output terminal of the row decoder driver includes a third PMOS transistor P3 in the form of an inverter and a triple-P well NMOS transistor TN1 for finally driving the word line W / L. A gate of the triple P-well NMOS transistor TN1 is connected to a first node K1, and a source is connected to a second P-well along with a triple P-well of the triple P-well NMOS transistor TN1. It is connected to the voltage source VEEX and is biased to a negative bias during erasing operation and to a ground potential (0 V) during program or read operation.

The triple N-well of the triple P-well NMOS transistor TN1 is connected to a third voltage source VCC. The gate of the third PMOS transistor P3 is connected to the first node K1, and the N-well of the third PMOS transistor P3 is connected to the first voltage source VPPX.

In addition, the N-well and the source of the second PMOS transistor P2 having the word line (W / L) voltage as a gate input are connected to the first voltage source VPPX, and the drain is connected to the first node K1. Is connected to.

The source and the N-well of the first PMOS transistor P1 are connected to the first voltage source VPPX, the drain is connected to the first node K1, and the reset signal XRSTb is supplied to the gate.

A source of the NMOS transistor N1 is connected to the first node K1, a gate of which is connected to the first control signal XPREAI, and a drain of the NMOS transistor N1 is connected to the fourth voltage source XCOMb.

The VPPX loading of the row decoder selected in FIG. 4 is similar to that of the row decoder driver circuit of FIG. 5. The source junction of the PMOS transistor P1 and the gate of the PMOS transistor P2 and the triple P-well NMOS transistor TN1 of FIG. The drain junction and the N-well of the PMOS transistors P1 to P3 and the loading to the word line W / L. The load is not large because only one of the row decoders is included.

The VPPX loading of the unselected row decoder includes the gate loading of the PMOS transistors P1 and P2 and the drain junction of the NMOS transistor N1, the gate and source junction of the PMOS transistor P2, and the triple P-well NMOS transistor TN1. The total unselected VPPX loading is the VPPX loading of the unselected row decoder and the number of unselected row decoders as the sum of the gates of N and the N-well loadings of the PMOS transistors P1 to P3 becomes the unselected row decoder 1 VPPX loading. Becomes the product of.

In turn, the overall VPPX loading is the sum of the VPPX loading of the selected row decoder and the VPPX loading of the entire unselected row decoder. Thus, reducing the number of unselected row decoders is most efficient to reduce the selected VPPX loading.

FIG. 6 is a waveform diagram of simulation results of a row decoder circuit according to the related art and the present invention, and it can be seen that the positive charge pumping time A according to the present invention is improved by about twice as much as the conventional positive charge pumping time B. FIG. .

As described above, according to the present invention, the present invention configures two or more positive charge pumping voltage switching circuits in one sector to enable only selected switching blocks in the selected sector, and the voltage output from the enabled selected switching blocks. By enabling the row decoder driver to be driven, the loading of the row decoder can be reduced, and the program and program check time can be shortened.

Claims (6)

A positive charge pumping circuit for inputting a power supply voltage and outputting a positive charge pumping voltage according to a positive charge pumping enable signal; A VPPY switching block configured to input the power supply voltage and the positive charge pumping voltage and output a VPPY pumping voltage according to a VPPY enable signal; And And a VPPX switching block for outputting even and odd VPPX pumping voltages to the low decoder of the flash memory according to the VPPX enable signal, the even sector selection signal, and the odd sector selection signal, respectively. Positive charge pumping voltage switching circuit comprising a. The method of claim 1, The VPPX switching block is an even switching block for outputting a good VPPX pumping voltage according to the VPPX enable signal and the good sector selection signal; And a radix switching block configured to output an odd VPPX pumping voltage according to the VPPX enable signal and the odd sector selection signal. In the row decoder of the flash memory, Logic means for inputting respective control signals and sector selection signals output from the low pre-decoder respectively; And According to the control signal outputted from the logic means and another control signal outputted from the low pre-decoder, either the voltage supplied from one of the voltage sources and the even and odd VPPX pumped voltages supplied from the precharge pumping voltage switching circuit can be obtained. A row decoder circuit of a flash memory using a positive charge pumping voltage switching circuit comprising a main row decoder and a redundancy row decoder for selectively outputting. The method of claim 3, wherein And the sector selection signal is any one of an even sector selection signal or an odd sector selection signal. The low decoder circuit of a flash memory using a positive charge pumping voltage switching circuit. The method of claim 3, wherein And the logic means comprises three input NAND gates each of which receives a control signal and a sector selection signal output from a low pre-decoder, respectively. The low decoder circuit of a flash memory using a positive charge pumping voltage switching circuit. The method of claim 3, wherein Each of the main row decoder and the redundancy row decoder includes a positive and odd row decoder driver having an even and an odd VPPX pumping voltage supplied from the precharge pumping voltage switching circuit, respectively. Row decoder circuit of the used flash memory.