JP3265291B2 - Output buffer circuit and semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit and a semiconductor integrated circuit, and more particularly to an output buffer circuit whose drive capability can be changed and a semiconductor integrated circuit having the same.

[0002]

2. Description of the Related Art In recent years, devices driven by a semiconductor integrated circuit have been diversified, and accordingly, the situation in which output buffer circuits of various output current standards must be developed in a short period of time has increased. On the other hand, the power supply current at the time of simultaneous output operation has increased drastically due to the increase in output speed and the increase in the number of output pins, and the danger of power supply noise resulting in malfunction of the semiconductor integrated circuit has increased. In order to prevent this, it has become necessary to adjust the current driving capability of the output buffer circuit. Under such circumstances, man-hours for designing and developing the output buffer circuit are rapidly increasing.

[0003] For the purpose of reducing the number of development steps, an output buffer capable of changing the driving capability in accordance with various output current standards has been proposed. In particular, the driving capability is changed even after the semiconductor integrated circuit is housed in a package. Japanese Patent Application Laid-Open No. 10-275895 discloses an output buffer circuit capable of selecting a driving capability by an external selection signal.

FIG. 8 is a circuit diagram of this conventional example. The output buffer circuit includes a pre-buffer unit 81 and a main buffer unit 82. The main buffer unit 82 includes a P-channel MOS transistor (hereinafter abbreviated as PMOS) 83
And a first partial buffer comprising an N-channel MOS transistor (hereinafter abbreviated as NMOS) 84 and a PMOS 85
A second partial buffer comprising:
A third partial buffer including an OS 87 and an NMOS 88 and a fourth partial buffer including a PMOS 89 and an NMOS 90 are provided. The pre-buffer unit has a current selection function. After shaping the waveform of the output data signal input from the output data input terminal IN, a predetermined one of the four partial buffers is selected according to the logical combination of the selected data signals SS1 and SS2. The output data signal is transmitted by selecting the number of partial buffers.

For example, when the selection data signals SS1 and SS2 are logic 0 and logic 0, respectively, the PMOS 83 and N
Only the first partial buffer composed of the MOS 84 is driven by the pre-buffer unit 81. At this time, assuming that the driving capability for the load connected to the output terminal OUT of the main buffer unit 82 is 1, the selection data signals SS1 and SS2 are respectively At the time of logic 1 and logic 0, the PMOS 83 and NM
First partial buffer composed of OS84 and PMOS 8
The second partial buffer including the NMOS transistor 5 and the NMOS 86 is driven by the pre-buffer unit 81. At this time, the driving capability of the main buffer unit 82 with respect to the load connected to the output terminal OUT is doubled.

Similarly, select data signals SS1, SS
2 is a logic 0 and a logic 1, respectively, the PMOS 87 and N are provided in addition to the first partial buffer and the second partial buffer.
The third partial buffer including the MOS 88 is also driven by the pre-buffer unit 81, and the main buffer unit 8 at this time is also driven.
2 is tripled, and the select data signals SS1, S
When S2 is logic 1 and logic 1, respectively, the PMOS 8
9 and the fourth partial buffer including the NMOS 90 are driven by the pre-buffer unit 81, and the driving capability of the main buffer unit 82 is 4 at this time.
Double.

As described above, in the conventional example of FIG. 8, by specifying the logical combination of the selection data signals SS1 and SS2 from outside the semiconductor integrated circuit, the main buffer 82
Can be changed to 1 to 4 times, so that one output buffer circuit can also serve as an output buffer circuit of a plurality of output current standards, and even after assembly, the occurrence of power supply noise during simultaneous output operation is reduced. It is possible to adjust the driving ability as described above.

[0008]

In the prior art shown in FIG. 8, in order to set the number of partial buffers in accordance with the maximum driving capability to be covered, the driving capability of the majority of output buffer circuits may be small. In this case, the same output buffer cell as that of the output buffer circuit of the maximum current standard is used, and a large number of transistors that do not actually operate exist on the semiconductor integrated circuit. For example, 4 out of 50 output buffer circuits mounted on a semiconductor integrated circuit
If the eight output buffer circuits are appropriate for the drive capacity of one partial buffer, the area of 48 × 3 = 144 partial buffers is occupied as a waste area unrelated to the operation.

In recent years, where the proportion of the buffer area in the semiconductor integrated circuit is increasing as the number of pins increases, it is required to reduce such a waste area and reduce the output buffer cell size. I have. SUMMARY OF THE INVENTION It is an object of the present invention to provide a compact output buffer circuit capable of changing and adjusting a driving capability even after assembling and having a small waste area regardless of the driving capability, and a high-density semiconductor integrated circuit suitable for increasing the number of pins. It is to provide a circuit.

[0010]

According to a first aspect of the present invention, there is provided an output buffer circuit having a first amplitude of an amplitude from a voltage selected by a voltage selection signal to a ground potential among a plurality of voltages having different amplitudes of an input signal. A pre-buffer unit for converting the signal into a signal and outputting a second signal having an inverse relationship with the signal; and two N-channel MOS transistors connected in series between the power supply and the ground and having a connection point as an output terminal. A main buffer unit that inputs the first signal to one gate of the two N-channel MOS transistors and inputs the second signal to the other gate;

An output buffer circuit according to a second invention is a first N-channel MOS transistor having a drain connected to a power supply of a first voltage and a source connected to the output terminal, and a source connected to the output terminal and having a drain connected to the output terminal. Is grounded
And N (N is a positive integer) different level conversion voltages which are higher than the first voltage and are different from each other, and one of the level conversion voltages is supplied by N voltage selection signals. A voltage selection circuit for selecting and outputting one of the two voltages as a second voltage, the second voltage being supplied, receiving an output data signal having an amplitude from the first voltage to the ground potential, A level shift circuit for outputting a first signal having an amplitude up to the ground potential and a second signal having an inversion relationship with the first signal;
Is input to the gate of the first N-channel MOS transistor, and the other signal is input to the second N-channel MOS transistor.
Input to the gate of S transistor.

An output buffer circuit according to a third aspect of the invention is a first N-channel MOS transistor having a drain connected to a power supply of a first voltage and a source connected to the output terminal, and a source connected to the output terminal and having a drain connected to the output terminal. Is grounded
And N (N is a positive integer) different level conversion voltages which are higher than the first voltage and are different from each other, and one of the level conversion voltages is supplied by N voltage selection signals. A voltage selection circuit for selecting and outputting one as a second voltage, and L (a positive integer of L ≧ log ₂ N)
A selection data signal decoding circuit for inputting a plurality of selection data signals and activating one of the N voltage selection signals to output to the voltage selection circuit in accordance with a logical combination thereof; An output data signal having an amplitude from the first voltage to the ground potential is supplied, and a first signal having an amplitude from the second voltage to the ground potential and a second signal having an inversion relationship with the signal. A level shift circuit for outputting a signal, wherein one of the first and second signals is input to the gate of the first N-channel MOS transistor, and the other is input to the gate of the second N-channel MOS transistor. You are typing.

In the second or third invention, the level conversion voltage may be a voltage value higher than a value obtained by adding a threshold voltage of the first N-channel MOS transistor to the first voltage. More preferred. Further, in the voltage selection circuits according to the second and third aspects of the present invention, the source and the back gate are connected to the first terminal and the gate is connected to the second terminal, and the source is the first P-channel MOS transistor. And the gate of the P-channel MOS transistor is connected to the second terminal, and the drain and the back gate are connected to the third terminal.
Has N selection switches each including a second P-channel MOS transistor connected to a corresponding one of the terminals, and each of the selection switches is supplied with one of the level conversion voltages to the first terminal. The voltage selection signal may be input to the second terminal and the third terminals of the N selection switches may be commonly connected to output the second voltage. Or a selection switch composed of a P-channel MOS transistor having a source connected to the first terminal, a gate connected to the second terminal, a drain connected to the third terminal, and a back gate connected to the fourth terminal. One of the level conversion voltages is supplied to the first terminal of each of the selection switches, and the corresponding voltage selection signal is input to the second terminal. In each case, the third terminals of the N selection switches are commonly connected to each other to output the second voltage, and the highest voltage of the level conversion voltages is supplied to each of the fourth terminals. It may be something.

A semiconductor integrated circuit according to a fourth aspect of the present invention comprises:
A plurality of output buffer circuits according to the second invention; N number of level conversion power supply terminals for supplying N number of level conversion voltages to the voltage selection circuits of the respective output buffer circuits; N voltage selection signal input terminals for supplying N voltage selection signals to the voltage selection circuit.

According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit comprising a plurality of output buffer circuits according to the third aspect of the present invention and N levels for supplying N level conversion voltages to the voltage selection circuits of the output buffer circuits. The conversion power supply terminal and the selected data signal decode circuit of each output buffer circuit
And L selection data signal input terminals for supplying the selection data signals.

According to a sixth aspect of the present invention, there is provided a semiconductor integrated circuit having M (M is a positive integer) buffer groups each including a plurality of the output buffer circuits according to the third aspect of the present invention, and a voltage selection circuit of the output buffer circuit. N level conversion power supply terminals for supplying N level conversion voltages, and L × M selection data for supplying L selection data signals to the output buffer circuit for each of the buffer groups A signal input terminal.

According to a seventh aspect of the present invention, there is provided a semiconductor integrated circuit comprising M (M is a positive integer) output buffer circuits according to the third aspect of the invention, and N voltage conversion circuits for each of the output buffer circuits. N power supply terminals for level conversion, and an L × M bit output selection memory for supplying L selection data signals to each of the output buffer circuits;
A serial input / memory write control circuit for serially inputting L × M voltage selection signal generation data from a selection data signal input terminal and writing the data at a predetermined address of the selection memory; More preferably, the selection memory is an electrically writable and erasable nonvolatile memory.

[0018]

Next, the present invention will be described in detail. FIG. 1 is a block diagram of an output buffer circuit according to the present invention. The output buffer circuit converts the amplitude of the output data signal input from the output data input terminal IN to the selected data signals SS1 to SS1 out of a plurality of different level conversion voltages V1 to VN.
A pre-buffer unit 1 for converting a voltage selected from SSL to a first signal having an amplitude from a ground potential and outputting a second signal having an inverse relationship to this signal, and a series connection between a power supply VDD and the ground; Connected to the output terminal OUT
And a main buffer unit 2 in which a first signal is input to the gate of one NMOS 14 and a second signal is input to the gate of the other NMOS 15. It is configured.

More specifically, the pre-buffer unit 1
(L is a positive integer) is input pieces of selection data signal SS1~SSL, N (N ≦ 2 positive integer ^L) pieces of the voltage selection signal SV1
To SVN, and N level conversion voltages V1 to VN different from each other and higher than the first voltage VDD1, which is the voltage of the power supply VDD, are supplied to the N voltage selection signals SV1 to SVN. A voltage selection circuit 11 for selecting and outputting one of the level conversion voltages V1 to VN as the second voltage VDD2, and a second voltage VDD
2, an output data signal having an amplitude from the first voltage VDD1 to the ground potential is input from the output data input terminal IN, and a first signal OT having an amplitude from the second voltage VDD2 to the ground potential and this signal And the second having a reversal relationship
And a level shift circuit 12 that outputs the signal OB of

In the output buffer circuit of FIG. 1, one of the level conversion power supplies V1 to VN is selected by designating the logical combination of the selection data signals SS1 to SSL, and the voltage is changed to the power supply voltage of the level shift circuit 12. By setting VDD2, the first signal input to the gate of the NMOS 14
And the high-level voltage of the second signal OB input to the gate of the NMOS 15 can be changed, so that the drive capability of the main buffer unit 2 can be changed. The second voltage VDD2 is equal to the power supply VDD.
Since the voltage is higher than the first voltage VDD1 supplied from D, even if transistors having a small channel width are used as the NMOSs 14 and 15, a large driving force is provided, and the occupation area of the main buffer unit 2 can be reduced. . When the number N of selectable level conversion voltages is small, the decoding circuit 13 is omitted and the voltage selection signal S
V1 to SVN may be directly input to the pre-buffer unit 1.

FIG. 2 is a circuit diagram of an embodiment of the present invention, in which three level conversion voltages V1 to V3 (VD1 <VD2 <VD3) by two selection data signals SS1 and SS2.
) Is selected as the second voltage VDD2.

The selection data signals SS1 and SS2 are supplied from a decoder circuit 13 to first, second and third voltage selection signals SV.
1, SV2 and SV3. When the selection data signals SS1 and SS2 are both logic 0, only the first voltage selection signal SV1 becomes active (low level, that is, the ground potential), and the second and third voltage selection signals SV2
2, SV3 is at a high level (ie, V3 potential).
Similarly, the selection data signal SS1 is logic 1 and SS2 is logic 0
In this case, only the second voltage selection signal SV2 becomes active low level, and the first and third voltage selection signals SV2
1, SV3 is at a high level. Select data signal SS1
Is logic 0 and SS2 is logic 1, only the third voltage selection signal SV3 is active low, and the first and second voltage selection signals SV1 and SV2 are high.

The voltage selection circuit 11 includes a PMOS 21 which is supplied with a first level conversion voltage V1 to a source and a back gate and inputs a first voltage selection signal SV1 to the gate.
And the source is connected to the drain of the PMOS 21, the first voltage selection signal SV1 is input to the gate, and the PMOS 22 is connected to the drain and the back gate to become the first output terminal.
And a PMOS 23 that is supplied with a second level conversion voltage V2 to a source and a back gate, and inputs a second voltage selection signal SV2 to the gate.
And the source is connected to the drain of the PMOS 23, the second voltage selection signal SV2 is input to the gate, and the PMOS 24 is connected to the drain and the back gate and becomes the second output terminal.
And a PMOS 25 that is supplied with a third level conversion voltage V3 to the source and the back gate, and inputs a third voltage selection signal SV3 to the gate.
And the source is connected to the drain of the PMOS 25, the gate is supplied with the third voltage selection signal SV3, and the drain and the back gate are connected and the PMOS 26 is connected to the third output terminal.
And a first output terminal, a second output terminal, and a third output terminal are commonly connected to each other to output a second voltage VDD2. .
The PMOS 22, PMOS 24, and PMOS 26 output the third level conversion voltage V3 as the second voltage VDD2, for example.
When 3 is selected, generation of a current path from V3 to V1 and V2 is prevented.

The voltage selection circuit 11 outputs a voltage / voltage selection signal S
V1, SV2, and SV3 determine the level conversion voltages V1, V
2 and V3 are selected and output as the second voltage VDD2. To output the first level conversion voltage V1 as VDD2, the first voltage selection signal SV1 is set to low level (VSS potential), and the second voltage selection signal S1 is set to the low level.
V2, the third voltage selection signal SV3 is set to a high level (V3 voltage level). PM constituting the first switch circuit
The OS 21 and the PMOS 22 are turned on, and the second and third
PMOS23, PMOS2 constituting the switch circuit of FIG.
4, the PMOS 25 and the PMOS 26 are turned off, so that the first level converting voltage V1 becomes the second voltage VDD2.
Is selected and output.

A second level conversion voltage V is set as VDD2.
2 is selected and output, the second voltage selection signal SV2
At a low level (ground potential), and the first and third voltage selection signals SV1 and SV3 at a high level (V3 potential). Similarly, the third level conversion voltage V is set as VDD2.
3 is selected and output, the third voltage selection signal SV3
At a low level (ground potential), and the first and second voltage selection signals SV1 and SV2 at a high level (V3 potential).

The level shift circuit 12 has a source and a back gate connected to a power supply terminal VDD and connected to a first voltage V
An NMOS 28 having a supply terminal DD1, a gate connected to the output data input terminal IN, a drain connected to the drain of the PMOS 27, a gate connected to the output data input terminal IN, and a source and a back gate grounded.
And a second voltage VDD2 at the source and the back gate.
Is supplied, the gate is connected to the drain of the PMOS 29, the gate is connected to the drain of the PMOS 27, and the gate is connected to the drain of the PMOS 27.
An NMOS 30 having a source and a back gate grounded, a PMO having a second voltage VDD2 supplied to the source and the back gate, and a gate connected to the drain of the PMOS 29
S31, the drain is connected to the drain of the PMOS 31, the output terminal of the second signal OB is connected, the gate is connected to the output data input terminal IN, and the source and the back gate are grounded. 2 is supplied and the gate is a PMOS.
An NMOS 33 connected to the drain of the PMOS 33, the drain connected to the drain of the PMOS 33, and the output terminal of the first signal OT; the gate connected to the drain of the PMOS 33;
4.

Next, the operation of the embodiment of FIG. 2 will be described with reference to the operation timing chart of FIG. The voltage selection circuit 11 causes the level conversion voltages V1, V2, V3 (VDD
Any voltage of 1 <V1 <V2 <V3) is supplied to the level shift circuit 12 as the power supply voltage VDD2.

When a low level (ground potential) is input to the output data input terminal IN of the level shift circuit 12, the drain of the PMOS 27 goes high (VDD1 potential) and the drain of the PMOS 29 goes low (ground potential). Therefore, the second signal OB is at a high level (V
DD2 potential), and the first signal OT becomes low level (ground potential). In the main buffer unit 2, the NMO
S15 is turned on, and the output terminal OUT connects the NMOS
A current flows through 15 to the ground. The second signal OB, that is, the NMOS1 is selected according to which of the level conversion voltages V1, V2, and V3 is selected by the voltage selection circuit 11.
The gate voltage of No. 5 increases in the order of S1B corresponding to V1, S2B corresponding to V2, and S3B corresponding to V3, and the driving capability of the NMOS 15 increases accordingly. Therefore, when a predetermined voltage is applied to the output terminal, Output current IOUT flowing
Increases in absolute values as IOL1, IOL2, and IOL3.

Similarly, when a high level (VDD1 potential) is input to the output data input terminal IN of the level shift circuit 12, the drain of the PMOS 27 goes low (ground potential) and the drain of the PMOS 29 goes high (VDD2 potential). ), The second signal OB goes low (ground potential) and the first signal OT goes high (VDD2 potential). In the main buffer section 2, the NMOS 14 is turned on, and a current flows from the power supply terminal VDD to the output terminal OUT through the NMOS 15. The first signal OT, that is, the gate voltage of the NMOS 14 is S1 corresponding to V1, S2 and V3 corresponding to V2.
In the order of S3 corresponding to.
, The output current IOUT flowing when a predetermined voltage is applied to the output terminal is
OH2, IOH3.

By setting all of the level conversion voltages V1, V2, and V3 to be higher than the first voltage VDD1 by at least the threshold voltage of the NMOS 14, the high level of the output signal from the output terminal OUT can be changed. , Conventional CMO
The potential can be set to VDD1 as in the main buffer section having the S configuration.

The voltage of the power supply VDD is set to 3.3 V, and the main buffer unit has a PMO having a total channel width of 200 μm.
In the case where the same driving capability as the maximum driving capability obtained by the conventional output buffer circuit of FIG. 8 constituted by S and NMOS having a total channel width of 200 μm is realized by the output buffer circuit of FIG. If the level conversion voltage V3 is 5 V, the channel width of the NMOS 14 is 80 μm and the NMO
The channel width in S15 can be reduced to 160 μm. That is, there is an effect that the total channel width of the main buffer section occupying the largest area among the output buffer cells in which the output buffer circuit is laid out in a pattern is reduced by 40% and the entire output buffer cell can be downsized.

FIG. 4 is a circuit diagram of another configuration example of the voltage selection circuit. The voltage selection circuit 11a includes a first switch circuit composed of a PMOS 41 to which a first level conversion voltage V1 is supplied to a source and a gate to which a first voltage selection signal SV1 is input, and a second level conversion voltage V2. Is supplied to the source, the second switch circuit composed of the PMOS 42 that inputs the second voltage selection signal SV2 to the gate, the third voltage V3 for level conversion is supplied to the source, and the third voltage is supplied to the gate.
And a third switch circuit including a PMOS 43 for inputting the voltage selection signal SV3. Back gate of PMOS 41, back gate of PMOS 42 and PMO
Level conversion voltages V1 to V3 are provided to the back gate of S43.
, Which is the highest voltage among them, is supplied to the PMOS 41
Drain, PMOS 42 drain and PMOS 4
The drains 3 are commonly connected to output a second voltage VDD2.

The details of the operation are substantially the same as those of the voltage selection circuit 11 of FIG. The voltage selection circuit 11a of FIG.
Since the number of transistors is small and the well potentials of the transistors are the same, the area occupied by the output buffer circuit when mounted on a semiconductor integrated circuit can be further reduced.

FIG. 5 is a schematic layout diagram of the first embodiment of the semiconductor integrated circuit of the present invention. The semiconductor integrated circuit 51 has power supply terminals for level conversion 52-1, 52-2,
52-3, selection data input terminals 53-1 and 53-2
And output buffer circuits 54-1 to 54-M are mounted,
Each output buffer circuit has a selection data input terminal 53-
The signal lines from the power supply terminals 1 and 53-2 and the voltage supply lines from the power supply terminals for level conversion 52-1, 52-2 and 52-3 are connected in common. Each of output buffer circuits 54-1 to 54-M is basically the same as the output buffer circuit described in FIG. 1, and pre-buffer section 55 corresponds to pre-buffer section 1 in FIG. Reference numeral 56 corresponds to the main buffer unit 2 in FIG. 1, and output terminal 57 corresponds to the output terminal OUT in FIG.

In the semiconductor integrated circuit 51 of FIG. 5, the power supply terminals 52-1, 52-2, 52 for level conversion are determined by the logical combination of the selection data signals SS1, SS2 input from the selection data signal terminals 53-1, 53-2. -3 of the level conversion voltages V1, V2, V3 supplied from
3 is selected, the output buffer circuits 54-1 to 54-1 are output.
All of the transistors 54-M operate with the driving force corresponding to the level conversion voltage V3. This configuration is suitable, for example, when a large number of output buffer circuits operating at the same time are mounted and it is necessary to adjust the output buffer circuits so that malfunction does not occur. When the number of selectable level conversion voltages is small, the pre-buffer unit 55 is connected to the pre-buffer unit 1 in FIG.
, Except that the decoding circuit is omitted from the configuration, three selection voltage signal terminals are provided in place of the two selection data signal terminals 53-1 and 53-2 and directly input to the voltage selection circuit in the pre-buffer unit. Good.

FIG. 6 is a schematic layout diagram of a second embodiment of the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 61 includes a first buffer group 62-1 including output buffer circuits 54-1 to 54-3 and a second buffer group 62 including output buffer circuits 54-4 to 54-6.
-2, a third buffer group 62-3 including output buffer circuits 54-7 to 54-9, and an output buffer circuit 5
The power supply terminals 52-1, 52-2, 52-3 for level conversion commonly connected to all of 4-1 to 54-9 and the output buffer circuits belonging to the first buffer group 62-1 are connected and selected. Selection data input terminals 63-1 and 63-2 for inputting data signals SS1 and SS2, and selection data input for inputting selection data signals SS3 and SS4 connected only to output buffer circuits belonging to second buffer group 62-2. Terminals 63-3 and 63-4 and selection data input terminals 63-5 and 63-6 connected to only the output buffer circuits belonging to the third buffer group 62-3 and inputting the selection data signals SS5 and SS6 are mounted. Have been. Each output buffer circuit is basically the same as the buffer circuit described in FIG. 1 as in the case of FIG.

In the semiconductor integrated circuit of FIG. 6, the voltage for level conversion can be selected for each buffer group. Therefore, even in a semiconductor integrated circuit in which different types of output buffer circuits of different output current standards are mounted, the same output buffer cell can be used. Can be used for both purposes.

FIG. 7 is a schematic layout diagram of a semiconductor integrated circuit according to a third embodiment of the present invention. The semiconductor integrated circuit 71 includes output buffer circuits 54-1 to 54-M, power supply terminals 52-1, 52-2, 52-3 for level conversion,
A selection data input terminal 73, a serial input / memory write control circuit 73, and a memory 74 are mounted.

Each of output buffer circuits 54-1 to 54-M is basically the same as the output buffer circuit shown in FIG. 1, and each output buffer circuit receives a selection data signal from memory 74. , Level conversion power supply terminal 5
The respective voltage supply lines from 2-1 to 52-2 and 52-3 are commonly connected.

Prior to the start of the operation of the semiconductor integrated circuit 71, the selection data is serially input from the selection data input terminal 72, and the serial input / memory write control circuit 73 receives the selection data and stores it in a predetermined address of the memory 74. Write. The memory 74 includes a first output buffer circuit 54
-1, the selection data signals SS1-1, SS2-1
And outputs selection data signals SS1-2 and SS2-2 to the second output buffer circuit 54-2, and selects the selection data signal SS1 for the M-th output buffer circuit 54-M hereinafter. −M, SS2-M, and selects one of the level conversion voltages V1, V2, V3 for each output buffer circuit. When the number of selected data signals to each output buffer circuit is L and the number of output buffer circuits is M, the serial input / memory write control circuit 7
3 is for selecting L × M selection data into the selection data input terminal 72
The memory 74 outputs a total of L × M selection data signals for each of the M output buffer circuits, L for each output buffer circuit. In FIG. 7, since two selection data signals are used for one output buffer, the memory 74 outputs a total of 2M selection data signals.

In the semiconductor integrated circuit shown in FIG. 7, a voltage for level conversion can be selected for each output buffer circuit.
By rewriting the selected data, the driving capabilities of the M output buffer circuits can be individually changed, so that one semiconductor integrated circuit can correspond to various output current standards. Further, since the selection data is input serially, the number of input terminals can be reduced to one. The selection data once written in the memory 74 is continuously used unless it is necessary to change the data. Therefore, if the memory 74 is a nonvolatile memory which can be electrically written and erased, the selection data is written to the memory prior to the start of each operation. There is no need to perform writing, which is more preferable.

[0042]

As described above, the output buffer circuit of the present invention can greatly reduce the channel width of the transistor in the main buffer section as compared with the conventional example of FIG. Has the effect of being able to reduce the size.

The semiconductor integrated circuit of the present invention equipped with this output buffer circuit is suitable for high integration and high pin count because the output buffer circuit is small. In addition, the semiconductor integrated circuit of FIG. In the semiconductor integrated circuit of FIG. 7, the driving capability can be set for each output buffer circuit, so that the output current standard can be changed according to the application field,
There is an effect that adjustment can be flexibly performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an output buffer circuit according to the present invention.

FIG. 2 is a circuit diagram of one embodiment of the present invention.

FIG. 3 is an operation timing chart of the circuit of FIG. 2;

FIG. 4 is a circuit diagram of another configuration example of the voltage selection circuit.

FIG. 5 is a schematic layout diagram of the first embodiment of the semiconductor integrated circuit of the present invention.

FIG. 6 is a schematic layout diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 7 is a schematic layout diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram of a conventional output buffer circuit capable of selecting a driving capability.

[Explanation of symbols]

1, 55, 81 Pre-buffer section 2, 56, 82 Main buffer section 11, 11a Voltage selection circuit 12 Level shift circuit 13 Decoding circuit 14, 15, 28, 30, 32, 34, 84, 86, 8
8,90 N-channel MOS transistor (NMO
S) 21, 22, 23, 24, 25, 26, 27, 29, 3
1,33,41,42,43,83,85,87,89
P-channel MOS transistors (PMOS) 51, 61, 71 Semiconductor integrated circuits 52-1, 52-2, 52-3 Level conversion power supply terminals 53-1, 53-2, 63-1, 63-2, 63-3 ,
63-4, 63-5, 63-6, 72 Selection data input terminals 54-1, 54-2, 54-3, 54-4, 54-5
54-6, 54-7, 54-8, 54-9, 54-M
Output buffer circuit 57 Output terminal 62-1, 62-2, 62-3 Buffer group 73 Serial input / memory write control circuit 74 Memory

Claims (11)

(57) [Claims] A second signal having an inversion relationship with the first signal having an amplitude ranging from a voltage selected by a voltage selection signal to a ground potential among a plurality of voltages having different amplitudes of an input signal; A pre-buffer unit that outputs a signal, and a connection point that is connected in series between the power supply and the ground and has a connection point as an output terminal
Having two N-channel MOS transistors.
The first gate is connected to one gate of the channel MOS transistor.
And a main buffer section to which the second signal is input and the other signal is input to the other gate. 2. A first N-channel MOS having a drain connected to a power supply of a first voltage and a source connected to an output terminal.
A transistor, a second N-channel MOS transistor having a drain connected to the output terminal and a source grounded, and N (N is a positive integer) different level conversion voltages higher than the first voltage and different from each other. A voltage selection circuit that selects and outputs one of the level conversion voltages as a second voltage according to the supplied N voltage selection signals, and the second voltage is supplied, and the first voltage is grounded. A level shift circuit for receiving an output data signal having an amplitude up to a potential and outputting a first signal having an amplitude from the second voltage to the ground potential and a second signal having an inverse relationship to the signal; And one of the first and second signals is the first signal.
An output buffer circuit, wherein the input is applied to the gate of the N-channel MOS transistor of the first embodiment and the other is applied to the gate of the second N-channel MOS transistor. 3. A first N-channel MOS having a drain connected to a power supply of a first voltage and a source connected to an output terminal.
A transistor, a second N-channel MOS transistor having a drain connected to the output terminal and a source grounded, and N (N is a positive integer) different level conversion voltages higher than the first voltage and different from each other. A voltage selection circuit that selects and outputs one of the level conversion voltages as a second voltage according to the supplied N voltage selection signals, and L (a positive integer of L ≧ log ₂ N) selection data signals And a selection data signal decoding circuit that activates one of the N voltage selection signals and outputs the selected voltage selection signal to the voltage selection circuit in accordance with the logical combination thereof, and the second voltage is supplied, An output data signal having an amplitude from the first voltage to the ground potential is input, and a first signal having an amplitude from the second voltage to the ground potential and a second signal having an inversion relationship with the signal are output. And a level shift circuit for outputting one of the first and second signals.
An output buffer circuit, wherein the input is applied to the gate of the N-channel MOS transistor of the first embodiment and the other is applied to the gate of the second N-channel MOS transistor. 4. The output buffer according to claim 2, wherein the level conversion voltage has a voltage value higher than a value obtained by adding a threshold voltage of the first N-channel MOS transistor to the first voltage. circuit. 5. A voltage selection circuit comprising: a first P-channel MOS transistor having a source and a back gate connected to a first terminal and a gate connected to a second terminal; and a source connected to the first P-channel MOS transistor. N selection switches each including a second P-channel MOS transistor having a gate connected to the second terminal, a drain connected to the second terminal, and a back gate connected to the third terminal; One of the level conversion voltages is supplied to the first terminal of the switch, the corresponding voltage selection signal is input to the second terminal, and N
4. The output buffer circuit according to claim 2, wherein the third terminals of the plurality of selection switches are commonly connected to be an output terminal of the second voltage. 5. 6. The voltage selection circuit according to claim 1, wherein the source is connected to the first terminal, the gate is connected to the second terminal, the drain is connected to the third terminal, and the back gate is connected to the fourth terminal. One of the level conversion voltages is supplied to the first terminal of each of the selection switches, and the corresponding voltage selection signal is supplied to the second terminal of the second terminal. Enter and N
The third terminal of each of the selection switches is connected in common to serve as an output terminal of the second voltage, and the highest voltage of the level conversion voltages is supplied to each of the fourth terminals. An output buffer circuit according to claim 2 or claim 3. 7. A plurality of output buffer circuits according to claim 2, N number of level conversion power supply terminals for supplying N number of level conversion voltages to a voltage selection circuit of each of said output buffer circuits, A semiconductor integrated circuit, comprising: N voltage selection signal input terminals for supplying N voltage selection signals to the voltage selection circuit of the output buffer circuit. 8. A plurality of output buffer circuits according to claim 3, N level conversion power supply terminals for supplying N level conversion voltages to voltage selection circuits of each of said output buffer circuits, A semiconductor integrated circuit comprising: L selection data signal input terminals for supplying L selection data signals to a selection data signal decoding circuit of the output buffer circuit. 9. M (M is a positive integer) buffer groups each including a plurality of output buffer circuits according to claim 3; and N level conversion circuits common to a voltage selection circuit of said output buffer circuits. N level power supply terminals for supplying a voltage, and L × M selection data signal input terminals for supplying L selection data signals to the output buffer circuit for each of the buffer groups. Characteristic semiconductor integrated circuit. 10. N number of level conversion circuits for supplying N level conversion voltages to M (M is a positive integer) output buffer circuits according to claim 3, and N voltage conversion circuits to voltage selection circuits of each of said output buffer circuits. A power supply terminal, an L × M-bit output selection memory for supplying L selection data signals to each of the output buffer circuits, and L × M voltage selection signal generation data from the selection data signal input terminal. And a serial input / memory write control circuit for inputting the data to a predetermined address of the selection memory and writing the data to a predetermined address of the selection memory. 11. The semiconductor integrated circuit according to claim 10, wherein said selection memory is an electrically writable and erasable nonvolatile memory.