KR100228769B1 - Semiconductor memory device word line driver - Google Patents

Abstract

The present invention relates to a word line driving circuit for obtaining a pair of signals required for controlling a word line from a word line boosting signal generator rather than a word decoder, . To this end, the word line driving circuit of the present invention comprises a first Loo decoder for receiving a part of an address signal to generate a word line enable signal MWi, and a second Loo decoder for receiving a boosting signal pxi, And a word line driver for selecting a word line by receiving an output of the first and second read decoders as input signals.

Description

A word line driving circuit

[0001] The present invention relates to a word line driving circuit of a semiconductor memory device, and in particular, by deriving a pair of signals in pairs required for control of a word line from a word line boosting signal generator, To a word line driving circuit in which a pitch is secured and a standby current is reduced.

The present invention is applicable to semiconductor design techniques that reduce the output line of a decoder in a semiconductor memory device and reduce the input line of a circuit that is constantly repeated, such as a hierarchical word line driver circuit.

A word decoder is used to control word lines in semiconductor memory devices. However, as memory devices become more highly integrated, there is not much room to lay out one decoder on one word line. Therefore, at present, most of the word lines are driven by a hierarchical word line driving circuit that shares several word line driving circuits with the output of one of the RO decoders and is separated by a subroodecoder (pxi generator). However, this method also frequently occurs when the pitch between the outputs of the RO decoder is not sufficiently ensured to cause a short / open between the outputs, or when the line width is narrow, sufficient current can not be supplied . However, in the case where the output of the RO decoder is used as a pair having a different state from that of the conventional method, the level 'high' and the level 'low', as in the second figure, The potential difference between the adjacent wires always maintains the potential difference of the power source voltage Vdd, so that it becomes more serious when a bridge between the wires due to the defect occurs.

Therefore, in the present invention, a pair of signals required for controlling a word line is derived from a word line boosting signal generator rather than a word decoder, thereby ensuring a metal pitch in the row decoder out, The purpose of this paper is to provide

In order to achieve the above object, a word line driving circuit of a semiconductor memory device according to the present invention includes: a first row decoder for receiving a part of an address signal to generate a word line enable signal MWi; A second row decoder for receiving the other part of the address signal as an input to generate a boosting signal pxi and a boosting bar signal pxib; And a word line driver for receiving the output of the first RO decoder and the output of the second RO decoder to select the word line.

According to another aspect of the present invention, there is provided a word line driving circuit for a semiconductor memory device, comprising: a first row decoder for receiving a part of an address signal to generate a word line enable signal MWi; A second row decoder for receiving the other part of the address signal as an input to generate a boosting signal pxi and a boosting bar signal pxib; Charging means for selecting a word line by taking as inputs the output of the first level of the first decoder and the output of the first level of the second decoder; And discharging means for discharging the word line by receiving the output of the second level of the first RO decoder and the output of the second level of the second RO decoder.

FIG. 1 is a conventional word line driving circuit diagram. FIG.

FIG. 2 is a configuration diagram of the word line driver circuit used in FIG. 1; FIG.

FIG. 3 is a circuit diagram of a word line driving circuit according to an embodiment of the present invention; FIG.

FIG. 4 is a schematic arrangement view of the word line driving circuit used in FIG. 3; FIG.

FIG. 5 is a conceptual diagram illustrating differences between a conventional decoder array and a conventional decoder array; FIG.

FIG. 6 is an operation timing diagram of FIG. 3; FIG.

7 is a conceptual diagram of operation of the word line driving circuit used in FIG. 3; FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

100, 110: ROODE decoder unit 200, 210: Word line boosting signal generator

300, 310: Word line driver section

The above objects, features and advantages will become more apparent from the following detailed description in conjunction with the accompanying drawings. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, the output of the RO decoder is used as a signal and the output of the subroodecoder (pxi) is used as a pair in order to secure the pitch between the outputs of the RO decoder outputs (MWi) due to the high integration of semiconductor memory devices. The circuit diagram of the present invention is shown in FIG. 3, and a simple implementation is shown in FIG.

FIG. 3 is a block diagram of a word line driving circuit according to an embodiment of the present invention, which includes a first row decoder (see FIG. 3 (b)) for generating a word line enable signal MWi with a part of an address signal as an input A third row decoder (see FIG. 3 (a)) for generating a boosting signal pxi and a boosting bar signal Pxib with another part of the address signal as an input, And an output of the first level of the second row decoder and an output of the second level of the second row decoder are input to the first row decoder and the second row decoder, And a word line driving circuit (third (c) view) configured as dis charging means for discharging the word line as an input.

4, the 'wlc' signal has a phase inverted to a / RAS delay signal, and the 'rx' signal is a signal that is used as a redundancy detection signal Quot; low " state to turn off the operation of the second row decoder (pxi generating circuit). The 'XAi' signal remains in the 'high' state only when some of the row addresses (mainly LSB (Least Significant Bit) to consecutive 2 bits are used). When 'XAi' is selected, the state changes from the ground voltage (Vss) to the power supply voltage (Vcc), and the level of the 'pxi' signal changes to the ground voltage (Vss). The 'xdpb' signal of the RO decoder becomes 'high' only at chip enable and stops the pre-charge of the RO decoder. At this time, the output 'MWi' signal changes from the ground voltage (Vss) to the power supply voltage (Vcc) when the row address XA23 / 45/67 enters 'high'. In the word line driver, the 'MWi' signal is a row decoder output, the 'pxi / pxib' signal is the output of the second row decoder, and 'WL' is a word line. The operation of the word line driver according to each situation is as follows: MWi = 'Vcc (H)', pxi0 / pxi0b = Vpp / Vss, pxi1 / pxi1b = pxi2 / pxi2b = pxi3 / pxi3b = Vss / In the case of Vcc, only the block 'A' of the four word line drivers is selected and wl0 only has the high state and the remaining three are turned off to the ground voltage (Vss). 7, the first and second N-MOS transistors MN1 and MN2 are turned on and the third and fourth N-MOS transistors MN3 and MN4 are turned off so that the word line 'wl0' The fourth N-MOS transistor MN4 is turned off so that the word line = 'wl1' is the ground voltage Vss (Vss), and the first through third N-MOS transistors MN1 through MN3 are turned on, ) State. Blocks C and D have the same state as block B.

The first and fourth N-MOS transistors MN1 and MN2 are turned on when MWi = 'Vcc (L)' and pxi0 / pxi0b = Vpp / Vss and pxi1 / pxi1b = pxi2 / pxi2b = pxi3 / pxi3b = Vss / MN4 are turned off and the second and third N-MOS transistors MN2 and MN3 are turned off so that the word line 'wl4' is turned off, and block B is turned on when the first and third N-MOS transistors MN1 and MN3 are turned on and the second and fourth N-MOS transistors MN2 and MN4 are turned off, the word lines are all at the ground voltage (Vss) state as in Blocks C and D. As shown in FIG. 4, since the same potential is maintained between adjacent control lines, unlike the conventional method, leakage current is not generated even if a bridge occurs in the process in the standby state. a leakage current does not flow in a line that is not selected even in the operating state. The operation timing of FIG. 4 is shown in FIG. 6 for the detailed description of the present invention, and FIG. 7 shows the states of the word line driver being turned on and off for each transistor.

As described above, the word line driving circuit according to the present invention is a semiconductor memory device in which a row decoding input of a word line driver is paired in a semiconductor memory device, thereby securing line pitch, which is a problem due to high integration, , Open, etc.), and maintains the same potential between adjacent lines, it has a great effect on the improvement of product yield and performance improvement, such as reduction of leakage current between lines.

It will be apparent to those skilled in the art that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. You should see.

Claims (13)

A word line driving circuit of a semiconductor memory device, comprising: a first row decoder for receiving a part of an address signal to generate a word line enable signal (MWi); A second row decoder for receiving the other part of the address signal as an input to generate a boosting signal pxi and a boosting bar signal pxib; And a word line driver for selecting the word line by taking the output of the first RO decoder and the output of the second RO decoder as inputs. The word line driving circuit according to claim 1, wherein the first row decoder generates a word line enable signal by inputting a predetermined number of address signals including a most significant bit of all address signals. 3. The word line driving circuit of claim 2, wherein the first row decoder generates only a word line enable signal and does not generate a complement signal. 2. The word line driving circuit of claim 1, wherein the boosting bar signal of the second row decoder is an inverted signal delayed by a predetermined period from the boosting signal. 2. The semiconductor memory device according to claim 1, wherein the second row decoder generates a boosting signal and a complement signal thereof by receiving a predetermined number of address signals including the least significant bit among all address signals, . 2. The semiconductor memory device according to claim 1, wherein the word line driver comprises: charging means for enabling a predetermined word line by receiving a first level word line enable signal and a first level boosting signal; And a discharging means for discharging a predetermined word line by receiving a second level word line enable signal and a second level boosting signal as inputs. 7. The word line driving circuit of claim 6, wherein the dis charging means is another enabled word line. A word line driving circuit of a semiconductor memory device, comprising: a first row decoder for receiving a part of an address signal to generate a word line enable signal (MWi); A second row decoder for receiving the other part of the address signal as an input to generate a boosting signal pxi and a boosting bar signal pxib; Charging means for selecting a word line by taking as inputs the output of the first level of the first decoder and the output of the first level of the second decoder; And a discharging means for discharging the word line by receiving the output of the second level of the first row decoder and the output of the second level of the second row decoder as a word, Line drive circuit. 9. The word line driving circuit of claim 8, wherein the first row decoder generates a word line enable signal by receiving a predetermined number of address signals including a most significant bit of all address signals. 10. The word line driving circuit of claim 9, wherein the first row decoder generates only a word line enable signal and does not generate a complement signal. 9. The word line driving circuit of claim 8, wherein the boosting bar signal of the second row decoder is an inverted signal delayed by a predetermined period from the boosting signal. 9. The semiconductor memory device according to claim 8, wherein the second row decoder generates a boosting signal and a complement signal thereof by receiving a predetermined number of address signals including the least significant bit among all address signals, . 9. The word line driving circuit of claim 8, wherein the dis charging means is another enabled word line.