KR100268945B1 - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to the yield and to reduce the entire area of a chip by reducing the generation of open/short of a word line in a manufacturing process. CONSTITUTION: A low detector(41) applies a plurality of GWLB(Global Word Line Bar) signal decoded with MSB(Most Significant Bit) address to a multiple SWD(Sub Word Line Driver) blocks(42). A sub-word line enabling unit(40) outputs an SWLE(Sub Word Line Enable) select signal decoded with LSB(Least Significant Bit) address. A low-decoding-precharging-signal generating unit(RDPRi/VBFi)(43) applies Vbb voltage to a precharge signal with the MSB address(PXb) from the row decoder(41) and the GWLB signals.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of driving a plurality of sub word line drivers by using output signals GWLB and SWLE of a row decoder.

Hereinafter, a semiconductor memory device according to the related art will be described with reference to the accompanying drawings.

1 is a configuration diagram of a conventional semiconductor memory device, and FIG. 2 is a detailed configuration diagram of a SWD block of the prior art. 3 is an operation timing diagram according to the driving of the semiconductor memory device of the prior art.

As shown in FIG. 1, a plurality of sub word line driver (SWD) blocks 3 and a plurality of global word line bars (GWLb) and GWL (decoded with MSB (most significant bit) addresses are decoded in the SWD block 3). A row decoder 2 for generating a global word line signal, and a sub word line enable unit for outputting a sub word line enable (SWLE) selection signal decoded with a LSB (Least Significant Bit) address; It is configured to include 1).

Detailed configuration of the SWD block is the same as in FIG.

A PMOS transistor P20 to which the GWLb signal of the row decoder 2 is applied to the gate, an NMOS transistor N22, and an NMOS transistor N21 connected to a source terminal of the sub word line SWL are configured.

The drain of the PMOS transistor P20 and the drain of the NMOS transistor N22 are connected to a sub word line.

The SWLE signal of the western word line enable unit 1 is applied to the source of the PMOS transistor P20 and the drain of the NMOS transistor N21, and the GWL signal of the row decoder 2 is applied to the gate of the NMOS transistor N21. do.

The source of the NMOS transistor N22 is connected to Vss.

The operation of the conventional semiconductor memory device configured as described above is the same as in FIG. 3.

In the t1 section, all GWL signals and SWLE signals are supplied with low voltage.

The GWLb signal is then supplied at the boosted voltage.

Therefore, the PMOS transistor P20 connected to the GWLb line is turned off and the NMOS transistor N22 is turned on to maintain the SWL in a low voltage state. At this time, the NMOS transistor N21 is turned off.

Subsequently, in the period t2, the SWLE signal decoded by the LSB address supplies the boosted voltage.

The GWLb signal decoded by the MSB address supplies a low voltage and the GWLb signal supplies a high voltage.

Accordingly, the PMOS transistor P20 and the NMOS transistor N21 are turned on and the NMOS transistor N22 is turned off to transfer the boosted voltage of the SWLE signal to the SWL to generate the SWL signal.

The semiconductor memory device of the prior art has the following problems.

The GWL and GWLb signals that control the multiple sub word lines are output from the row decoder, respectively, and are connected to four SWDs. This means that there are two metal lines, GWLb and GWL signal lines, for every four polysilicon word lines. it means.

Accordingly, there is a problem in that the yield is reduced by generating word line defects due to a lack of design rule margin in the manufacturing process.

In addition, in such a semiconductor memory device, coupling noise or the like is generated between the word line and the word line and between the word line and the bit line, thereby degrading chip performance.

The present invention has been made to solve the problems of the conventional semiconductor memory device, and a semiconductor memory device capable of driving a plurality of sub word line drivers using output signals (GWLB, SWLE) of a row decoder. Its purpose is to provide.

1 is a configuration diagram of a conventional semiconductor memory device

Figure 2 is a detailed block diagram of a SWD block of the prior art

3 is an operation timing diagram according to driving of a semiconductor memory device of the related art.

4 is a configuration diagram of a semiconductor memory device according to the present invention.

5 is a detailed configuration diagram of a semiconductor memory device according to the present invention.

6 is an operation timing diagram according to driving of a semiconductor memory device according to the present invention.

Explanation of symbols for main parts of the drawings

40. Sub word line enable section 41. Row decoder

42. SWD block 43. Low decoding precharge signal generator

The semiconductor memory device of the present invention, which can drive a plurality of sub word line drivers using output signals GWLB and SWLE of a row decoder, includes a plurality of sub word line driver (SWD) blocks, and an MSB A row decoder that applies a plurality of global word line bar (GWLb) signals decoded to a Most Significant Bit (Address) address, and a sub word line enable (SWLE) selection signal decoded to a LSB (Least Significant Bit) address. And a low decoding precharge signal generator RDPRi / VBFi having an MSB address PXb and applying a Vbb voltage to the precharge signal of the row decoder 41 and the GWLb signal. It is characterized in that the configuration.

Hereinafter, a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

4 is a configuration diagram of a semiconductor memory device according to the present invention, and FIG. 5 is a detailed configuration diagram of the semiconductor memory device according to the present invention. 6 is an operation timing diagram according to the driving of the semiconductor memory device according to the present invention.

The semiconductor memory device of the present invention is largely configured as follows.

As shown in FIG. 4, a plurality of sub word line driver (SWD) blocks 42 and a plurality of global word line bar (GWLb) signals decoded to MSB (most significant bit) addresses are applied to the SWD block 42. A row decoder 41, a sub word line enable unit 40 for outputting a sub word line enable (SWLE) selection signal decoded with a LSB (Least Significant Bit) address, and an MSB address ( And a row decoding precharge signal generator (RDPRi / VBFi) 43 having PXb) and applying a Vbb voltage to the precharge signal of the row decoder 41 and the GWLb signal.

The detailed configuration of the semiconductor memory device of the present invention configured as described above is as follows.

First, the row decoder 41 is connected to drains of the first, second, and third PMOS transistors P40, P41, and P42 to which the Vpp voltage is applied to the source, and the drains of the first and second PMOS transistors P40 and P41. First, second, third, and fourth NMOS transistors N40 and N41 connected to the source of the first transistor and connected in series with a decoded signal by the MSB address output from the row decoding precharge signal generator 43 to the gate, respectively. N42 and N43, an inverter I40 connected to the drains of the first and second PMOS transistors P40 and P41, and an output terminal outputting a drain and a GWLb signal of the third PMOS transistor P42. Fifth and sixth NMOS transistors N44 and N45 each having a first transistor connected to each other and connected in series, and a seventh NMOS having a gate connected to an output terminal of the inverter I40 and a source connected to an output terminal for outputting a GWLb signal. A transistor N46, a source is connected to a ground terminal, and a drain thereof is in the seventh NMOS; And an eighth NMOS transistor N47 connected to the transistor N46 to which a VBF signal is applied to a gate.

The gate of the second PMOS transistor P41 is connected to the output terminal of the inverter I40, and a low decoding precharge signal is applied to the gate of the first PMOS transistor P40.

The VBFB signal is applied to the gate of the fifth NMOS transistor N44.

A detailed configuration of the row decoding precharge signal generator 43 is as follows.

A low decoding precharge signal generator RDPRi for inputting a decoding signal PXb by the MSB to output a low decoding precharge signal, a delay for delaying the low decoding precharge signal, and a delayed low decoding pre A NAND calculator for NAND operation of the charge signal and the non-delayed low decoding precharge signal, an inverter I41 for inverting the output signal of the NAND calculator, and Vcc applied to a source, and a gate of the inverter I41 is respectively applied to the gate. The first and second PMOS transistors P42-1 and P42-2 to which an output signal and an output signal of the NAND calculator are applied, Vbb is applied to a source, and a drain is applied to a drain of the first PMOS transistor P42-1. The first NMOS transistor N49-1 to be connected and the second NMOS transistor having a drain connected to the output terminal for outputting a VBF signal and a drain of the second PMOS transistor P42-2 applied with Vbb to the source. It is configured to include the (N49-2).

Each SWD block includes an inverter of PMOS and NMOS transistors P43 and P48 to which a GWLb signal output from the row decoder 41 is applied to a gate, respectively.

A SWLE (sub word line enable signal) is applied to the source of the PMOS transistor P43, and an SWL signal for driving a sub word line is output to an output terminal of the inverter.

The driving method of the semiconductor memory device of the present invention will be described as follows.

As shown in FIG. 6, as the MSB addresses PXij, PXkl, and PXmn supply a low voltage, the first, second, and third NMOS transistors N40, N41, N42 of the low decoder 41 are turned on in the period t1. As it is turned off, the MSB address (PXb) also supplies the Low Voltage, which supplies the output signal Low Voltage of the RDPRi block.

Accordingly, as the fourth NMOS transistor N43 is turned off and the first PMOS transistor P40 is turned on so that the node N40-1 becomes a boosted voltage, a low voltage is applied to the third PMOS transistor P42 through the inverter 140. As it is turned on, it supplies a boosted voltage to GWLb.

At this time, while the SWLE signal is being supplied with a low voltage, the PMOS transistor P43 of the SWD block is turned off and the NMOS transistor N48 of the SWD block 42 is turned on to supply VSS to the SWL line.

In the section t2, as the MSB addresses PXij, PXkl, and PXmn supply high voltages, the first, second, and third NMOS transistors N40, N41, and N42 of the row decoder 41 are turned on, and the MSB address PXb is also turned on. As the high voltage is supplied, the output signal of the RDPRi block supplies the boosted voltage.

Accordingly, as the first PMOS transistor P40 is turned off and the fourth NMOS transistor N43 is turned on so that the node N40-1 becomes low voltage, the sixth and seventh NMOS transistors N45 and N46 pass through the inverter I40. As the boosted voltage is supplied to the VBFB, the VBFB has the boosted voltage through the delay unit and the NAND calculator unit ND40 with the RDPR signal.

Since the VBF passing through the level shifter is in the negative Vbb voltage state, the fifth, sixth and seventh NMOS transistors N44, N45, and N46 are turned on, thus supplying a low voltage to the GWLb. At this time, since the selected SWLE signal is already supplying the boosted voltage, the PMOS transistor P43 of the SWD block is turned on and the NMOS transistor N48 of the SWD block 42 is turned off to supply the boosted voltage to the SWL line.

At this time, as the VBFB signal supplies the low voltage and the VFB signal supplies the high voltage after the data t1 time, the Vbb signal is supplied to the GWLb signal as the fifth NMOS transistor N44 is turned off and the eighth NMOS transistor N47 is turned on. do.

Therefore, even if unnecessary noise occurs in the unselected SWL, it flows through the unselected SWLE line having a low voltage through the PMOS transistor P43 of the SWD.

Then, VBFB applies the boosted voltage to NMOS Tr.N44 and Vbb to the eighth NMOS transistor N47 before the next time interval t1 comes to the GWLb line by delta t2. The SWL then falls to a low voltage as the selected SWLE supplies a low voltage.

In this case, as the MSB addresses PXij, PXkl, and PXmn supply low voltages, the fifth and sixth NMOS transistors N40 and N41 of the row decoder 41 are turned off, and the MSB addresses PXb also supply low voltages. Supply the output signal low voltage of the block.

Accordingly, the fourth NMOS transistor N43 is turned off, the first PMOS transistor P40 is turned on, and the node N40-1 is at the boosted voltage, and the sixth and seventh NMOS transistors N45 and N46 are turned off to GWLb. Supply boosted voltage.

At this time, the PMOS transistor P43 of the SWD block 42 is turned off and the NMOS transistor N48 is turned on to supply VSS to the SWL line while the SWLE signal is supplying a low voltage.

In the semiconductor memory device of the present invention, since only one signal is output from the row decoder, the GWLb signal controlled by the MSB address has an effect of increasing the yield by reducing the occurrence of open / short of the word line during the manufacturing process.

In addition, by applying a voltage of -Vbb to the selected GWLb, the PMOS transistor functions as a noise canceling function, thereby reducing the transistor size than a general SWD block. This has the effect of reducing the total area of the chip.

Claims (4)

A plurality of sub word line driver (SWD) blocks, A row decoder for applying a plurality of global word line bar (GWLb) signals decoded to a Most Significant Bit (MSB) address to the SWD block; A sub word line enable unit for outputting a sub word line enable (SWLE) selection signal decoded with a LSB (Least Significant Bit) address; And a low decoding precharge signal generator (RDPRi / VBFi) having an MSB address (PXb) and applying a Vbb voltage to the precharge signal of the row decoder and the GWLb signal. 2. The row decoder of claim 1, wherein the row decoder comprises: first, second, third PMOS transistors P40, P41, P42, to which a Vpp voltage is applied to the source; First, second, third, and fourth NMOS transistors N40, N41, N42 connected to the source of the first transistor to the drains of the first and second PMOS transistors, and decoded by an MSB address to the gate, respectively. ) (N43), An inverter I40 connected to a drain of the first and second PMOS transistors P40 and P41; Fifth and sixth NMOS transistors N44 and N45 having first transistors connected in series with output terminals for outputting the drain and the GWLb signal of the third PMOS transistor P42, respectively; A seventh NMOS transistor N46 having a gate connected to an output terminal of the inverter I40 and a source connected to an output terminal for outputting a GWLb signal; And a source connected to a ground terminal and a drain connected to the seventh NMOS transistor (N46), the eighth NMOS transistor (N47) applying a VBF signal to a gate. The low decoding precharge signal generator of claim 1, further comprising: a low decoding precharge signal generator RDPRi for receiving a decoding signal PXb by the MSB and outputting a low decoding precharge signal; A delay delaying the row decoding precharge signal; A NAND calculator configured to perform a NAND operation on the delayed low decoding precharge signal and the non-delayed low decoding precharge signal and output the result; An inverter I41 for inverting an output signal of the NAND calculator; First and second PMOS transistors P42-1 and P42-2 to which Vcc is applied to the source, and to which an output signal of the inverter I41 and an output signal of the NAND calculation unit are respectively applied to the gate; A first NMOS transistor N49-1 having a Vbb applied to the source and a drain connected to the drain of the first PMOS transistor P42-1, and a Vbb applied to the source and the second PMOS transistor P42-2. And a second NMOS transistor (N49-2) having a drain connected to the drain of the output terminal and the output terminal for outputting the VBF signal. 2. The semiconductor memory device according to claim 1, wherein the SWD block comprises an inverter of a PMOS and an NMOS transistor (P43) (P48) to which a GWLb signal output from a row decoder is applied to a gate, respectively.