KR20000051202A - Power boosting circuit of a SRAM cell - Google Patents

Abstract

PURPOSE: A power boosting circuit of an SRAM cell is provided to improve an access rate of a cell data by boosting the cell data and a word line and to improve the degree of high-integration by improving a read noise margin. CONSTITUTION: A boosting circuit(20) boosts a first power supply voltage to a certain level according to an enable signal. A word line driving unit(40) receives the boosted power supply from the boosting circuit(20) according to a low address selection signal and drives a word line of a corresponding memory cell with the boosted voltage. A memory cell(10) receives the boosted power supply from the boosting circuit (20) according to operation of the word line driving unit(40) to boost the cell data, and accesses the cell data by a pair of bit lines according to the boosted driving signal of the word line driving unit(40).

Description

Power boosting circuit of a SRAM cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static random access memory (SRAM), in particular an SRAM cell for applying a boost voltage to a cell and a wordline driver of an SRAM to improve margins of cell noise when reading cell data. It relates to a power boost circuit.

In the semiconductor memory device, the read operation margin of the cell data and the access speed of the cell data largely depend on the cell current.

In other words, due to the decrease of the cell current due to the low voltage, the voltage gaps formed on the pair of bit lines are reduced, so that sensing of the sense amplifier is delayed so that the access speed of the cell data is delayed or the sensing cannot be performed within the read pulse period. Error occurs.

In order to improve the margin of the read and write of the cell data, a technique of boosting the first power voltage applied to the word line driver by a predetermined amount is used as shown in FIG. 1.

1 shows a power boost circuit of a memory cell according to the prior art, and shows a word line driver 1 and a memory cell 5.

The word line driver 1 is configured to operate according to the row address selection signals IN1 and IN2 to receive a predetermined boost power PBoost to drive the word line of the corresponding memory cell 5 to a boost voltage. The memory cell 5 is configured to access the cell data as bit line pairs BL and BLB according to the boost driving signal of the word line driver 1.

That is, the output WL1 of the word line driver 1 selected by the row address is enabled at 'Vcc + α' at 0 V, and becomes the input of the pass transistors M1 and M2 of the memory cell 5.

In order to write data to the selected memory cell 5, the pass transistors M1 and M2 of the cell are turned on according to the enable of the word line WL1 to increase the level of the bit line pair BL and BLB. The write operation is performed by transferring the data to the node. In contrast, the data read from the memory cell 5 senses the voltage formation of the pair of bit lines BL and BLB by the cell current and reads the data.

In this way, the boosted word line WL1 performs a write operation by sufficiently transferring the first power supply voltage Vcc level of the bit line pair to the cell node without a down of the threshold voltage Vt of the pass transistor during the write operation. However, in the read operation, the difference between the cell data 'high' node and the cell data 'low' node formed in the bit line pair as well as an increase in the cell current as well as a current 'low' level rise of the cell node are formed. It has been accompanied with the problem of lowering the cell noise margin formed in the line pair.

An object of the present invention is to provide a power boost circuit for an S-RAM cell that increases cell current and improves cell noise margin by boosting the power supply of the word line and the cell connected to the word line of the S-RAM cell.

In order to achieve the above object, the apparatus of the present invention includes a boosting circuit unit for boosting the first power supply voltage to a predetermined level according to a predetermined enable signal, and a boosting power supply of the boosting circuit unit according to a row address selection signal. A word line driver for driving a word line of a cell at a boost voltage and a boost power from the boost circuit unit according to the operation of the word line driver to boost cell data, and according to a boost drive signal of the word line driver; Has a memory cell for accessing the bitline pair.

1 is a circuit diagram showing a power-up method of the S-RAM according to the prior art,

Figure 2 is a block diagram showing a power boost circuit of the SRAM applied to the present invention,

3 is a circuit diagram illustrating a power up circuit of an S-RAM cell according to an exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10: memory cell 20: booster circuit section

30: row decoder 40: word line driver

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 is a block diagram illustrating a power boost circuit of an S-RAM cell according to the present invention, and includes a boost circuit 20, a row decoder 30, a word line driver 40, a memory cell 10, and the like.

Reference numeral 20 denotes a booster circuit unit for boosting the first power supply voltage to a predetermined level according to a predetermined enable signal, reference numeral 30 denotes a row decoder that receives and decodes a row address, and reference numeral 40 denotes a selection signal INA, The word line driver is operated according to INB to drive the word line WLi of the memory cell 10 by receiving the boosted power of the booster circuit unit 20, and the reference numeral 10 denotes the operation of the word line driver 40. The memory for boosting the cell data by receiving the boost power from the boost circuit unit 20 and accessing the cell data to the bit line pairs BL and BLB according to the boost drive signal WLi of the word line driver 40. It is a cell.

That is, unlike the related art, the boosted power PBoost is supplied to the memory cell 10 through the word line driver 40 as well as the word line driver 40.

FIG. 3 is a circuit diagram illustrating a power up circuit of an S-RAM cell according to an exemplary embodiment of the present invention, showing a word line driver 40 and a memory cell 10.

The word line driver 40 includes a P-type transistor MP1 and a boost terminal PBoost connected to a current path between the boost terminal PBoost and the first node Nd1 and responding to the first input signal INA. ) And a current path is connected between the first node Nd1 and a P-type transistor MP2 in response to the second input signal INB, and a current path is connected in series between the first node Nd1 and the ground voltage. The plurality of N-type transistors MN1 and MN2 respectively respond to the first input signal INA and the second input signal INB.

In addition, a current path is connected between the boost stage PBoost and the second node Nd2 and the P-type transistor MP3 responding to the signal of the first node Nd1, and the boost stage PBoost and the word line output stage ( The current path is connected between the WLi and the P-type transistor MP4 responding to the signal of the first node Nd1, and the current path is connected between the word line output terminal WLi and the ground voltage and the first node Nd1. N-type transistor (MN3) in response to the signal, and the current path is connected between the power supply voltage (Vcc) and the second node (Nd2) to the P-type transistor (MP5) is always turned on in response to the ground voltage Consists of.

In the memory cell 10, an N-type transistor having a current path connected between the bit line BL and the third node Nd3 of the cell and responding to the word line output signal WLi of the word line driver 40 is provided. An N-type transistor MN5 that connects a current path between the MN4 and the bit line bar BLB and the fourth node Nd4 of the cell and responds to the word line output signal WLi of the word line driver 40. And a P-type transistor MP6 connected with a current path between the second node Nd2 and the third node Nd3 of the cell and responding to a signal of the fourth node Nd4 of the cell, and the third node Nd3. Current path is connected between the N-type transistor MN6 and the second node Nd2 and the fourth node Nd4 of the cell in response to the signal of the fourth node Nd4. P-type transistor MP7 connected to and responding to the signal of the third node Nd3 of the cell, and a current path is connected between the fourth node Nd4 and the ground voltage, and the signal of the third node Nd3 is connected. Is composed of N-type transistors response (MN7) which.

The operation of the present invention configured as described above will be described with reference to FIGS. 2 and 3.

When the predetermined enable signal Enable is input, the output boosting signal PBoost of the booster circuit unit 20 is boosted to the signal level Vcc + α in which the power supply voltage Vcc is increased by a predetermined amount α.

When the row address is input, the first line input signal INA and the second input signal INB corresponding to the row address decoded by the row decoder 30 are selected as the 'high' level so that the word line driver The N-type transistors MN1 and MN2 of 40 are turned on to lower the potential of the first node Nd1 to the 'low' level.

As the potential of the first node Nd1 becomes 'low' level, the P-type transistor MP3 is turned on to transfer the boosted voltage PBoost, which is a power source, to the second node Nd2 which is a drain terminal.

The boost signal PBoost transmitted to the second node Nd2 includes the bulk of the P-type transistors MP6 and MP7 and the P-type transistor MP5 of the memory cell 10 as the first power supply voltage Vcc. Therefore, the source terminal of the P-type transistors MP6 and MP7 of the cell 10 is not set to 'Vcc + α' but is set to 'Vcc + Vt (diode)' level, which is the diode voltage Vt of each of the transistors MP5, MP6 and MP7. do.

This is because the bulk stepped up by α flows through the transistors MP5, MP6, and MP7, which are the first power supply voltages Vcc, and is consumed, leaving only Vt, the diode voltage of each transistor.

Accordingly, the second node Nd2 of the cell 10 is stepped up to the voltage 'Vcc + Vt (diode)', and at the same time the output signal of the NAND gates MP1, MP2, MN1, MN2 of the word line driver 40 is substantially the same. Nd1 turns on the P-type transistors MP4 of the inverters MP4 and MN3 to boost the output word line WLi of the inverter from a 'low' level to a 'Vcc + α' level.

In a read operation, the 'high' node Nd3 or Nd4 of the cell is charged higher due to the boosted voltage of the second node, and the 'low' node Nd4 or Nd3 of the cell is full of the memory cell 10. By lowering to a lower level with the -down transistor (MN6 or MN7) lower and at the same time turning on the bitline transistor more strongly due to the 'Vcc + α' level when the wordline (WLi) is enabled, more cell current is bit It improves cell noise due to low current flowing into the line.

In addition, the P-type transistor MP5 installed in the word line driver 40 does not supply the boosted voltage PBoost to the memory cell 10 when the potential of the first node Nd1 is 'high' level. At this time, it is a power supply transistor for supplying the first power supply voltage Vcc to the memory cell 10.

Accordingly, in the present invention, by boosting the cell data and the word line, the access speed of the cell data is improved, and the read noise margin, which is a level difference between the cell data high node and the cell data low node, is improved to improve the degree of high integration. There is.

Claims (3)

A booster circuit unit for boosting the first power supply voltage to a predetermined level according to a predetermined enable signal; A word line driver configured to receive a boosted power of the booster circuit unit according to a row address selection signal to drive a word line of the corresponding memory cell at a boosted voltage; And And boosting cell data by receiving boost power from the boost circuit unit according to the operation of the word line driver, and accessing the cell data as a bit line pair according to the boost drive signal of the word line driver. Power boosting circuit of SRAM cell. The word line driver of claim 1, wherein A P-type transistor MP1 connected with a current path between the boosting stage PBoost and the first node Nd1 and responding to the first input signal INA, A p-type transistor MP2 connected to a current path between the boosting stage PBoost and the first node Nd1 and responding to a second input signal INB; A plurality of N-type transistors (MN1, MN2) and the current path is connected in series between the first node (Nd1) and the ground voltage, respectively, and respond to the first input signal (INA) and the second input signal (INB), A P-type transistor MP3 connected to a current path between the boosting stage PBoost and the second node Nd2 and responding to a signal of the first node Nd1; A p-type transistor MP4 connected to a current path between the boost stage PBoost and the word line output terminal WLi and responding to a signal of the first node Nd1; An N-type transistor MN3 connected to a current path between the word line output terminal WLi and a ground voltage and responding to a signal of a first node Nd1, and A power supply for an S-RAM cell, comprising a P-type transistor MP5 that is connected between a predetermined power supply voltage Vcc and a second node Nd2 and is always turned on in response to a ground voltage. Boost circuit. The method of claim 1, wherein the memory cell, An N-type transistor MN4 connected with a current path between the bit line BL and the third node Nd3 of the cell and responsive to the word line output signal WLi of the word line driver 40; An N-type transistor MN5 connected to a current path between the bit line bar BLB and the fourth node Nd4 of the cell and responsive to the word line output signal WLi of the word line driver 40; A p-type transistor MP6 connected with a current path between the second node Nd2 and the third node Nd3 of the cell and responding to a signal of the fourth node Nd4 of the cell; An N-type transistor MN6 connected with a current path between the third node Nd3 and the ground voltage and responding to a signal of the fourth node Nd4; A p-type transistor MP7 connected with a current path between the second node Nd2 and the fourth node Nd4 of the cell and responding to a signal of the third node Nd3 of the cell, and And an N-type transistor (MN7) connected to a current path between the fourth node (Nd4) and the ground voltage and responding to a signal from the third node (Nd3).