KR100884262B1 - Word line decoder capable of preventing current from leaking - Google Patents

Abstract

The present invention relates to a word line decoder capable of preventing current leakage. The present invention provides a pre-decoder signal input unit for receiving a signal corresponding to a preset address set from a low-free decoder; A control unit controlling a signal output of the pre decoder signal input unit; An inverter for inverting a signal output from the pre decoder signal input unit according to a control signal of the controller; And an active mode holding unit for maintaining an active mode for activating a word line according to a signal output from the inverter. According to the present invention, the simple structure has the advantage of increasing the level width and preventing current leakage.

Word, Line, Decoder, NMOS, PMOS, Pre Decoder

Description

Word line decoder capable of preventing current from leaking}

1 is a diagram illustrating an example of a word line decoder according to the prior art.

2 shows another example of a word line decoder according to the prior art.

3 illustrates a memory including a word line decoder in accordance with the present invention.

4 illustrates a logic structure of a word line decoder according to an exemplary embodiment of the present invention.

5A is a timing diagram of a word line decoder first and second input in accordance with the present invention.

5B is a timing diagram of a word line decoder third input in accordance with the present invention.

The present invention relates to a word line decoder that can prevent current leakage, and more particularly, to a word line decoder that is structurally simple and can prevent current leakage.

Recently, digital processing devices such as all mobile phones are using memory.

A memory is a device capable of storing (storing) data, and includes a memory cell array including peripheral circuits for transmitting control signals, addresses, and data, and a plurality of memory cells for storing data.

The memory cell array includes a word line, which is a signal line for selecting and activating a memory cell, and a bit line, which is a signal line for inputting and outputting memory cell data.

The peripheral circuit includes a word line decoder that decodes an externally input row address to activate a specific word line. FIGS. 1 to 2 illustrate a word line decoder according to the prior art.

As shown in FIG. 1, a conventional word line decoder includes a control PMOS transistor 100 (hereinafter referred to as control PMOS), a data latch PMOS transistor 102, a plurality of inverters 104 and 106, and a pre-decoded address signal (predecoder signal). Includes a plurality of NMOS transistors 108 to 112 (hereinafter referred to as NMOS).

Here, the control P-channel metal-oxide semiconductor (PMOS) 100 and the data latch PMOS 102 operate in the range of the first power supply Vpp (peak voltage 2.8V) to the second power supply Vss (source voltage 0V). Gate PMOS is applied.

In addition, the operating range of the inverters 104 and 106 is again Vpp to Vss, and the operating range of the three NMOSs 108 to 112 is Vperi (peripheral circuit voltage, 1.8V) to Vss.

The word line decoder outputs a low or high signal to the main word line (mwln, 114) pair through the low or high signal within the operating range.

However, according to the related art shown in FIG. 1, the level width is low because the main word line pair swings from Vpp to Vss, and thus a sub threshold leakage of capacitance for storing data. Will increase.

In this case, there is a problem that frequent refreshing is required, especially when the memory is configured with a DRAM (Dynamic Random Access Memory) cell array requiring refreshing.

On the other hand, in order to prevent such a refresh, as shown in FIG. 2, the operating range of the inverters 104 and 106 is Vnwl (negative word line) having a negative potential at Vpp, and a plurality of NMOSs 108 to 112 into which a predecoder signal is input. Has been proposed to have a ground potential of Vnwl.

However, when Vss is input as a low signal in the standby mode when the predecoder signal has an operating range of Vpp to Vss, the potential Vss and the ground potential Vnwl input to the NMOS 108 to 112 are input. Due to the difference between the current path (current path) is generated there is a problem that the current leakage occurs.

In order to solve this problem, a level shifter for dropping a low signal to Vnwl is provided at the front end of the word line decoder. However, in this case, the structure of the word line decoder is complicated because it is necessary to provide a level shifter for all the multiple inputs of the word line decoder. There was a problem that the layout is complicated.

In order to solve the problems of the prior art as described above, the present invention proposes a word line decoder capable of preventing current leakage in the standby mode.

Another object of the present invention is to provide a word line decoder capable of preventing current leakage even through a simple structure.

In order to achieve the above object, according to a preferred embodiment of the present invention, a pre-decoder signal input unit for receiving a signal corresponding to a preset address set from the low-free decoder; A control unit controlling a signal output of the pre decoder signal input unit; An inverter for inverting a signal output from the pre decoder signal input unit according to a control signal of the controller; And an active mode holding unit for maintaining an active mode for activating a word line according to the signal output from the inverter.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first, second, A, and B may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

 Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, the same reference numerals will be used for the same means regardless of the reference numerals in order to facilitate the overall understanding.

3 is a diagram illustrating a memory including a word line decoder according to the present invention.

Hereinafter, the word line decoder according to the present invention will be described as being applied to a synchronous DRAM (SDRAM) as shown in FIG. 3, but the present invention can be applied to any memory having a word line without being limited thereto. Should be understood.

As shown in FIG. 3, a memory according to the present invention may include a plurality of banks Bank 0 to 3 and 300 and a memory interface.

The plurality of banks is an array of unit DRAM memory cells, which are groups of memory cells that operate independently to implement high speed operation through interleaving.

The memory interface receives an address and a control signal from a processor to activate a predetermined bank, and activates a word line and a bit line of a specific memory cell included in the bank to enable writing and reading of data.

The memory interface shown in FIG. 3 illustrates an SDRAM memory interface, which includes a state machine 302, an address buffer 304, a row free decoder 306, an address register 308, and a column address counter. A 310 and column free decoder 312, a plurality of X-decoder (word line decoder, 314) and Y-decoder (column decoder, 316), main sense amplifier and input / output gate 318, and input / output buffer 320 It may include.

The state machine 302 receives a clock and a control signal from a processor or the like that decodes and executes an instruction to determine an operating state of the memory chip.

In this case, the control signal is a write-in which determines the writing or reading of a low strobe signal (Row Address Strobe (/ RAS)) activating DRAM operation, a column strobe signal (Column Address Strobe (/ CAS)) indicating the application of a column address, and data. It may include an enable signal (Write Enable, / WE) and a clock enable signal (CKE).

The state machine 302 outputs the low active signal to the low free decoder 306 through the combination of the control signals described above, and outputs the column active signal to the column free decoder 312.

On the other hand, the address buffer 304 receives an n-bit address input from an external processor or the like and outputs it to the address register 308.

The address may include a row address, a column address, and a bank address BA. The bank address may be, for example, 1 bit when the DRAM memory array has two banks, and may be 2 bits when the bank has four banks, as shown in FIG. 3.

The address register 308 outputs a bank select signal to the state machine 302 so that the corresponding bank is activated, and the row address and column address are supplied to the row free decoder 306, the column address counter 310 and the column free decoder ( 312).

The row predecoder 306 outputs a predecoder signal obtained by predecoding a row address input when a row active signal is input.

Here, the pre decoder signal is a signal that is independently decoded and output by 3 bits, 3 bits, and 2 bits when a preset address set (for example, an 8-bit row address exists).

The word line decoder 314 receives the pre decoder signal to activate the corresponding word line.

According to a preferred embodiment of the present invention, the word line decoder 314 is provided in a configuration capable of preventing current leakage in the standby mode while maintaining a high level width for activating a specific word line.

The word line decoder 314 according to the present invention includes a pre decoder signal input unit for receiving the pre decoder signal, a controller for controlling the output of the pre decoder signal input unit, an active mode for maintaining an active mode for activating an inverter and a word line. It may include a holding unit.

4 is a diagram showing the configuration of a word line decoder 314 according to the present invention.

As shown in FIG. 4, the control PMOS transistor 400 (hereinafter referred to as the control PMOS transistor), the data latch PMOS transistor 402, the plurality of inverters 404 and 406, and the row-free decoder 306 are preset. It may include a plurality of NMOS (408 to 412, corresponding to the pre decoder signal input unit described above) for receiving a signal corresponding to the set of addresses, and also connected to the data latch PMOS transistor 402 and the first inverter 404 NMOS 414 (corresponding to the active mode maintaining unit described above).

In FIG. 4, the control PMOS 400 and the data latch PMOS 402 may be configured as thick gate PMOS transistors because they operate at a general Vpp (2.8V) to Vss (0V).

The word line decoder 314 according to the present invention may be configured as a three-input NAND. In this case, the predecoder input unit includes a first NMOS 408, a second NMOS 410, and a first NMOS 410 as shown in FIG. 3 NMOS 412 may be included.

According to a preferred embodiment of the present invention, the first and second NMOSs 408 and 410 have an operating range of Vperi (1.8V) to Vss (0V), and the third NMOS 412 (gate of the third NMOS) is low. A level shifter 413 for dropping the signal from Vss to Vnwl is connected and has an operating range of Vperi (1.8V) to Vnwl (-0.57V). Also, the source side of the third NMOS 412 is grounded to Vnwl.

According to the present invention, a high signal is input to the first to third NMOSs 408 to 412 in the active mode as a pre decoder signal.

In this case, as illustrated in FIG. 5A, a high signal VPeri is input to the first and second NMOSs 408 and 410 during an active mode time (eg, 100 ns). That is, the first and second NMOSs 408 and 410 remain turned on for a time set in the active mode.

In contrast, according to the present invention, as shown in FIG. 5B, the high signal Vperi is input only to the third NMOS 412 for a shorter time (eg, 10 ns) than the active mode time.

In the three-input word line decoder, a high signal is input to all of the first to third NMOSs 408 to 412 to maintain a turn-on state in order to activate the corresponding word line. Only the preset pulse time is turned on, not the entire active mode time, and turned off to Vnwl for the rest of the time.

The word line decoder according to the present invention is provided with an active mode holding part connected to the output terminal of the first inverter 406, and in FIG. 4, the active mode holding part is connected to the ground potential Vnwl, and a gate is connected to the output terminal of the first inverter 406. It may be a fourth NMOS 414 connected to it.

As described above, the high signal Vperi is input to the first and second NMOSs 408 and 410 during the active mode time, and the high signal Vperi is applied to the gate side of the third NMOS 412 during the pulse time 10 ns. When input, the first to third NMOSs 408 to 412 are all turned on, so the input of the first inverter 406 becomes a low signal and the output terminal of the first inverter 406 becomes high.

In this case, since the gate of the fourth NMOS 414 is connected to the output terminal of the first inverter 406, the gate of the fourth NMOS 414 is turned on in response to the high signal output of the first inverter 406. Will remain low.

Accordingly, even if the third NMOS 412 is turned off after 10 ns, the first inverter 406 can maintain the output terminal in a low state for activating the word line for the remaining active mode time by the fourth NMOS 414. do.

In the standby mode, Vss is input to the gate sides of the first and second NMOSs 408 and 410, and thus the first and second NMOSs 408 and 410 are turned off. The third NMOS 412 is already turned off because the Vnwl low signal is being input after the pulse time.

In addition, since the predecoder signal Vnwl of the third NMOS 412 in the standby mode is equal to the ground potential, the word line decoder according to the present invention does not form a current path in the standby mode.

Also in this case, even if the first and second NMOS 408 and 410 are turned off to Vss, and the third NMOS 412 is turned to Vperi, the high signal is only applied to the gate side of the third NMOS 412 only for a predetermined pulse time. Since is inputted, only a pulse section forms a current path, which is a simpler structure than the conventional art, and can significantly reduce current leakage.

After activating a specific word line through the above process, the column free decoder 312 outputs the column address to the Y-decoder according to the column active signal input. In this case, the column free decoder 312 may receive a counting signal from the column address counter 310 according to a burst write and read mode, and sequentially output the column address from the start column address.

The Y-decoder activates the bit line corresponding to the corresponding column address, and the main sense amplifier and the input / output gate 318 amplify the memory cell data latched to the bit line in the data read mode or pass through the data line in the data write mode. Amplifies the memory cell data to perform input and output through the input and output buffer 320.

Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit and scope of the present invention. Additions should be considered to be within the scope of the following claims.

As described above, according to the present invention, there is an advantage of preventing current leakage in the standby mode while maintaining a large level width for activating the word line.

In addition, according to the present invention, since level shifting is required for only one input connected to the ground potential among the plurality of inputs, there is an advantage in that the level width can be kept large with a simple structure.

In addition, according to the present invention, since the third input becomes a pulse signal, a current path is generated only for a short time, thereby reducing the current leakage.

Claims (7)

A pre decoder signal input unit configured to receive a signal corresponding to a preset address set from a low pre decoder; A control unit controlling a signal output of the pre decoder signal input unit; An inverter for inverting a signal output from the pre decoder signal input unit according to a control signal of the controller; And And an active mode holding unit configured to maintain an active mode of activating a word line according to a signal output from the inverter. The method of claim 1, And the pre-decoder signal input section includes a plurality of (first to nth, wherein n is a natural number of 3 or more), and at least one of the NMOS transistors is connected to a ground potential of a negative potential. The method of claim 2, And a gate of an NMOS transistor connected to the ground potential is connected to a level shifter for dropping a low signal (Vss) level of the predecoder signal to the negative potential (Vnwl) level. The method of claim 3, And wherein when the gate of the NMOS transistor connected to the ground potential is an nth NMOS, the gates of the first to n-1th NMOS transistors have a Vperi to Vss operating range. The method of claim 3, And a pulse high signal is input to the gate in the active mode for a time shorter than a duration of the active mode. The method of claim 1, And the active mode holding part is an NMOS transistor whose gate is connected to an output terminal of the inverter. The method of claim 5, And the active mode maintaining unit outputs a pulse low signal after the pulse high signal for the duration of the active mode.

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