KR20030054901A - Method of Driving Liquid Crystal Display Module and Apparatus thereof - Google Patents

Abstract

PURPOSE: A method and an apparatus for driving a liquid crystal display module are provided to remove an afterimage by displaying a white signal on a liquid crystal panel when sensing a power-off point. CONSTITUTION: A liquid crystal display module(30) includes a liquid display panel(38) displaying an image, signal line driving circuits(34,36) driving signals lines of the liquid crystal panel, and a timing controller(32) controlling driving timing of the signal line driving circuits and supplying data signals. A power supply unit(24) supplies driving voltage required for the liquid crystal display module. A power-off detector(44) detects the off point of the power supply unit through base driving voltage and gate high voltage. If a specific state of a power-off sensing signal is supplied from the power-off detector, the timing control unit generates a white data signal to be displayed on the liquid display panel.

Description

Method and device for driving liquid crystal display module {Method of Driving Liquid Crystal Display Module and Apparatus}

The present invention relates to a liquid crystal display module driving apparatus, and more particularly, to a method and apparatus for driving a liquid crystal display module that can prevent an afterimage when the power is turned off.

The liquid crystal display module displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display module includes a liquid crystal panel having a pixel matrix and a driving circuit for driving the liquid crystal panel. The driving circuit drives the pixel matrix so that the image information is displayed on the display panel.

In practice, the liquid crystal display module is connected to the system driver 1 provided in the system main body as shown in FIG.

The system driver 1 includes a graphics card 2 for supplying video data or the like suitable for the liquid crystal display module 3. The graphics card 2 converts the input video data into the liquid crystal display module 3 so as to be suitable for the resolution of the liquid crystal display module 3. Video data is composed of red (R), green (G), and blue (B) data. In addition, the graphic card 2 generates control signals such as a main clock signal, a vertical synchronization signal and a horizontal synchronization signal suitable for the resolution of the liquid crystal display module 3.

The liquid crystal display module 3 includes a liquid crystal panel 10, a data driver 6 for driving the data lines D1 to Dm of the liquid crystal panel 10, and gate lines G1 of the liquid crystal panel 10. To the gate driver 8 for driving Gn, the timing controller 4 for controlling the driving timing of the data and gate drivers 6 and 8, and the driving voltage required for driving the liquid crystal display module 3; The power supply circuit 14 which generate | occur | produces, and the gamma circuit 12 which supplies a gamma voltage to the data driver 6 is provided.

The timing controller 4 relays the video data R, G, and B from the graphics card 2 and supplies it to the data driver 6. In addition, the timing controller 4 generates control signals such as timing signals and polarity inversion signals for controlling the timing of the data and the gate drivers 6 and 8 in response to the control signal from the graphics card 2. .

The power supply circuit 14 uses driving voltages (gate high voltage, gate low voltage, and gamma reference) required for driving the liquid crystal display module 3 using voltages input from a system power supply (not shown) of the system driver 1. Voltage, common voltage, and the like) are generated and supplied to the timing controller 4, the data driver 6, the gate driver 8, the gamma circuit 12, and the like.

The liquid crystal panel 10 is connected to a thin film transistor TFT formed at an intersection of n gate lines GL1 to GLn and m data lines DL1 to DLm, and is connected to the thin film transistor TFT and has a matrix form. The liquid crystal cells are arranged as. The thin film transistor TFT supplies a video signal from the data lines DL1 to DLm to the liquid crystal cell in response to the gate signal from the gate lines GL1 to GLn. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor, so that the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacitor Cst connected to the previous gate line to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged.

The gate driver 8 sequentially supplies the gate high voltage signal to the gate lines GL1 to GLn according to the control signal from the timing controller 4. The data driver 6 converts the R, G, and B data signals from the timing controller 4 into analog signals so that one horizontal line is provided for each horizontal period in which the gate high voltage signals are supplied to the gate lines GL1 to GLn. The video signal is supplied to the data lines DL1 to DLn. At this time, the gamma circuit 12 supplies the gamma voltage preset to the data driver 6 to have different voltage levels according to the voltage level of the video signal. Accordingly, the data driver 6 adds the gamma voltage from the gamma circuit 8 to the video signal and supplies it to the data lines DL1 to DLn so that the gamma characteristic in the liquid crystal display device is corrected.

Referring to the driving method of the liquid crystal panel 10, the thin film transistor TFT is turned on by the gate high voltage Vgh supplied to the gate line GL, and thus the video voltage supplied to the data lines DL1 to DLm. The signal is charged in the liquid crystal capacitor Clc. Subsequently, the thin film transistor TFT is turned off by the gate low voltage Vgl supplied to the gate line GL, so that the video voltage charged in the liquid crystal capacitor Clc is maintained until the next data voltage is supplied. In this case, the storage capacitor Cst connected in parallel with the liquid crystal capacitor Clc is provided when the gate high voltage Vgh is supplied to the previous gate line GLi-1, so that the gate low voltage Vgl is supplied. When the voltage is charged, the voltage is maintained higher than the voltage charged in the liquid crystal capacitor Clc in the turn-off period of the thin film transistor TFT. Accordingly, since the storage capacitor Cst supplies charge to the liquid crystal capacitor Clc in the turn-off period of the thin film transistor TFT, the variation of the voltage charged in the liquid crystal capacitor Clc may be minimized.

When the system power is turned off in the driving device of the liquid crystal display module, the afterimage is displayed on the screen as the video voltage charged in each of the liquid crystal cells of the liquid crystal panel 10 is slowly discharged. . This is because when the power is turned off, the voltage charged in the liquid crystal cell gradually converges to the base potential through the leakage current of the turned-off TFT.

In order to remove such an afterimage when the power is off, a method of forcibly discharging the voltage charged in the liquid crystal cells when the power is turned off by using a separate discharge circuit is used. For example, the discharge circuit detects a power off and supplies a base potential to the gate lines to turn on the thin film transistors to quickly discharge the voltage charged in the liquid crystal cells, thereby eliminating the afterimage. However, as these discharge circuits are provided for each gate line, the structure of the liquid crystal panel becomes complicated. In addition, when the discharge circuit is used in a dot or line inversion liquid crystal display module, the thin film transistor is turned on and forced discharge is performed in the liquid crystal cells charged with a negative voltage lower than the base potential supplied to the gate electrode. In the liquid crystal cells charged with a positive voltage higher than the base potential, the afterimage is still present as the thin film transistor is turned off and forced discharge is not performed. In addition, when the voltage charged in the liquid crystal cells is forcibly discharged using the discharge circuit, since a predetermined discharge time exists, afterimage removal using a separate discharge circuit is not effective.

Accordingly, an object of the present invention is to provide a method and apparatus for driving a liquid crystal display module that can remove an afterimage caused by discharge of a liquid crystal cell.

1 is a block diagram showing the configuration of a conventional liquid crystal display module driving apparatus.

2 is a block diagram showing the configuration of a liquid crystal display module driving apparatus according to an embodiment of the present invention.

3 is a circuit diagram showing a detailed configuration of the power supply circuit shown in FIG.

4 is a voltage waveform diagram output when the power supply circuit shown in FIG. 2 is turned off.

FIG. 5 is a block diagram showing the detailed configuration of the power off detection unit shown in FIG. 2; FIG.

FIG. 6 is a detailed circuit diagram of the VCC off detection unit shown in FIG. 5; FIG.

FIG. 7 is a detailed circuit diagram of the VGH off detection unit shown in FIG. 5. FIG.

8 is an input / output voltage waveform diagram of the power-off detection unit shown in FIG. 5;

<Description of Symbols for Main Parts of Drawings>

1, 20: system driver 2, 22: graphics card

3, 30: liquid crystal display module 4, 32: timing control unit

6, 34: data driver 8, 36: gate driver

10, 38: liquid crystal panel 12, 40: gamma circuit

14, 42: power supply circuit 24, 54: system power supply

In order to achieve the above object, the driving method of the liquid crystal display module according to the present invention comprises the steps of generating a white data signal by detecting the off time of the power supply unit through the base driving voltage and the gate high voltage supplied from the power supply unit of the liquid crystal display module; ; And displaying the white data signal on the liquid crystal display module.

In particular, the driving method of the liquid crystal display module according to the present invention may be regarded as an off point of the power supply unit when the base driving voltage and the gate high voltage are simultaneously changed.

The white data signal may be displayed on the liquid crystal display module by using the driving voltages converged to the ground voltage with a predetermined convergence time after detecting the off point of the power supply.

The white data signal may be displayed on the liquid crystal display module for at least one frame.

The liquid crystal display module driving apparatus according to the present invention provides a liquid crystal panel displaying an image, a signal line driving circuit for driving signal lines of the liquid crystal panel, a driving timing of the signal line driving circuit, and supplying a data signal. A liquid crystal display module having a timing controller; A power supply unit supplying a driving voltage required by the liquid crystal display module; A power off detection unit for detecting an off point of the power supply unit through a base driving voltage and a gate high voltage supplied from the power supply unit; When the power-off detection signal of a specific state is supplied from the power-off detection unit, the timing controller generates a white data signal to be displayed on the liquid crystal panel.

The power off detection unit may detect a time when the base driving voltage and the gate high voltage are simultaneously changed as the power off unit to generate a power off detection signal in a specific state.

To this end, the power-off detection unit includes a base driving voltage off detector for detecting a variable time point of the base driving voltage; A gate high voltage off detector for detecting a variable time point of the gate high voltage; And a logic sum gate for generating a power-off detection signal of the specific state when the variable driving time of the base driving voltage and the gate high voltage are simultaneously detected.

In particular, the base driving voltage off detector includes a transistor for switching the base driving voltage according to the voltage division ratio of the base driving voltage and outputs a voltage in a logic state, and adjusts the base driving voltage variable time point by adjusting the voltage division ratio of the base driving voltage. Should be.

The gate high voltage off detection unit may include a transistor that is switched according to the voltage division ratio of the gate high voltage and outputs a voltage in a logic state, and adjusts the base driving voltage variable time point by adjusting the voltage division ratio of the gate high voltage. It is done.

The timing controller may include a white data signal generator configured to generate a white data signal when a power off detection signal of a specific state is supplied from the power off detector; A control signal generator for generating control signals for controlling driving timing of the signal line driver integrated circuit using the input control signals; And a data alignment unit for aligning and outputting the input data signal and the white data signal.

The liquid crystal display module may display a white data signal on the liquid crystal panel using driving voltages converged to ground voltages with a predetermined convergence time in the power supply unit after sensing the off point of the power supply unit.

The liquid crystal display module may display the white data signal on the liquid crystal panel for at least one frame.

The power off detection unit may be built in the timing control unit.

Other objects and advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 6.

2 is a block diagram illustrating a configuration of a liquid crystal display module driving apparatus according to an exemplary embodiment of the present invention. The liquid crystal display module driving apparatus shown in FIG. 2 includes a system driver 20 installed in the system main body, and a liquid crystal display module 30 for detecting a power off state so that a white signal is displayed on the liquid crystal panel 38. .

The system driver 20 includes a graphic card 22 for supplying video data and the like to the liquid crystal display module 30, and a power supply unit 24 for supplying a driving voltage. The graphic card 22 converts the input video data to the resolution of the liquid crystal panel 38 and outputs the converted video data to the liquid crystal display module 30. Video data is composed of red (R), green (G), and blue (B) data. In addition, the graphic card 22 generates control signals such as a main clock signal, a vertical synchronization signal, a horizontal synchronization signal, and the like suitable for the resolution of the liquid crystal display module 30. The power supply unit 24 supplies a driving voltage to the power supply circuit 42 of the liquid crystal display module 30.

The liquid crystal display module 30 includes a liquid crystal panel 38, a data driver 34 for driving the data lines D1 to Dm of the liquid crystal panel 38, and gate lines G1 of the liquid crystal panel 38. To a gate driver 36 for driving Gn), a timing controller 32 for controlling the driving timing of the data and gate drivers 34 and 36, and generating a white data signal when a power-off is detected; A power-off circuit for generating a driving voltage for driving the liquid crystal display module 30 and a power-off detection unit for detecting a power-off circuit of the power supply circuit 42 and supplying a power-off detection signal to the timing controller 32 ( 44 and a gamma circuit 40 for supplying a gamma voltage to the data driver 34.

The power supply circuit 42 generates driving voltages necessary for driving the liquid crystal display module 30 by using input power from the system power supply unit 24. To this end, the power supply circuit 42 includes a DC / DC converter 46 for generating base driving voltages VCC and VDD using the input power from the system power supply unit 24 as shown in FIG. The first and second charge pumps 48 and 49 that generate the gate high voltage VGH and the gate low voltage VGL, respectively, are formed by using the base voltages VCC and VDD from the converter 46. Equipped.

The DC / DC converter 46 generates base drive voltages VCC and VDD which are usually set at 3.3V and 7.8V using the input power from the system power supply unit 24. The base driving voltages VCC and VDD are supplied to the timing controller 32, the data driver 34, the gate driver 36, the gamma circuit 40, and the power off detection unit 44. Each of the capacitors C1 and C2 for removing noise components is connected in parallel to the output lines of the base driving voltages VCC and VDD. The first charge pump 48 generates a gate high voltage VGH of about 20V by level shifting using the first base driving voltage VCC lowered by the first resistor R1. The second charge pump 49 generates a gate low voltage VGL of about −5 V by level shifting using the first base driving voltage VCC lowered by the first resistor R1. The gate high voltage VGH and the gate low voltage VGL are supplied to the gate driver 36. The output lines of the gate high voltage (VGH) have capacitors and resistors (C3 // R2) connected in parallel to remove noise components, and the gate low voltage (VGL) output lines are also connected in parallel for noise components. Capacitor and resistor C4 // R3.

When the power supply circuit 42 having such a configuration is turned off through the system power supply unit 24, the first base driving voltage VCC, the gate high voltage VGH, and the gate low voltage VGL supplied from the power supply circuit 42 are provided. ) Converges to the ground voltage (0V) with a predetermined convergence period as shown in FIG.

Referring to FIG. 4, a convergence time of about 70 ms is required for the first base driving voltage VCC to fully converge from the power-off time to the ground voltage OV. This convergence time is determined by the line resistance of the output line of the first base driving voltage VCC and the time constant RC of the capacitor C1. The convergence period of the gate high voltage VGH and the gate low voltage VGL, which starts to converge to the ground voltage OV later than the first base driving voltage VCC from the power-off time, takes about 70 ms. This convergence time is also the time constant of the line resistors of the output lines of the gate high voltage (VGH) and the gate low voltage (VGL) and the capacitors and resistors (C3 // R2, C4 // R3) connected in parallel to the output lines. Determined by (RC).

Even after the system power supply unit 24 is turned off, the driving voltages generated by the power supply circuit 42 converge to the ground voltage with a predetermined convergence time. Accordingly, even when the system power supply unit 24 is turned off, the liquid crystal display module 30 can be driven for at least one frame using driving voltages generated at the convergence time in the power supply circuit 42.

The power off detection unit 44 detects a power off time by using the first base driving voltage VCC and the gate high voltage VGH supplied from the power supply circuit 42. Specifically, as shown in FIG. 5, the power off detection unit 44 detects the off point of the VCC off detection unit 50 for detecting the off point of the first base driving voltage VCC, and the off point of the gate high voltage VGH. The AND gate 54 generating a power-off monitoring signal by performing an AND operation on the output voltages VCC_off and VGH_off from the VGH off detection unit 52 and the VCC off detection unit 50 and the VGH off detection unit 52. Equipped.

As illustrated in FIG. 6, the VCC off detection unit 50 is turned on / off according to the state of the first base driving voltage VCC to generate a low / high voltage signal. It is provided. The first base driving voltage VCC is divided by the divided resistors R1 and R2 and input to the base terminal of the transistor T1. When the divided first base driving voltage VCC is in a normal state, the first transistor T1 is turned on and is supplied to the collector terminal of the first transistor T1 via the third resistor R3. As the base driving voltage VCC converges to the ground potential GND, a low voltage is output to the output line connected to the collector terminal as the VCC off signal VCC_off as shown in FIG. On the other hand, when the power supply circuit 42 is turned off to reduce the first base driving voltage VCC, the first transistor T1 is turned off to the ground line OV at the output line as shown in FIG. 8. The converged first base driving voltage VCC is output as a VCC off signal VCC_off in a high state. As such, when the VCC off signal VCC_off is changed from a low state to a high state voltage, the VCC off detection unit 50 considers the VCC off point. Here, the off detection timing of the first base driving voltage VCC may be varied by adjusting the resistance ratios of the first and second resistors R1 and R2 that divide the first base driving voltage VCC and supply them to the gate terminal. have.

As illustrated in FIG. 7, the VGH off detector 52 includes a second transistor T2 that is turned on / off according to the state of the gate high voltage VGH to generate a voltage signal of a low / high state. do. The gate high voltage VGH is divided by the voltage divider R4 and R5 and input to the base terminal of the transistor T2. When the divided gate high voltage VGH is in the normal state, the second transistor T2 is turned on and is supplied to the collector terminal of the second transistor T2 via the sixth resistor R6. As the voltage VCC converges to the ground potential GND, a low voltage is supplied to the output line connected to the collector terminal as the VGH off signal VGH_off as shown in FIG. On the other hand, when the power supply circuit 42 is turned off to decrease the gate high voltage VGH, the second transistor T2 is turned off and is converging to the ground voltage OV in the output line as shown in FIG. 8. The first base driving voltage VCC is output as the VGH off signal VGH_off in the high state. In this way, the VGH off detection unit 52 considers the VGH off point when the VGH off signal VGH_off is changed from a low state to a high state voltage. The off detection timing of the gate high voltage VGH may be varied by adjusting the resistance ratios of the fourth and fifth resistors R4 and R5 that divide the gate high voltage VGH and supply the gate terminal to the gate terminal.

The AND gate 54 detects a variable time point of the first base driving voltage VCC and the gate high voltage VGH at the VCC off detection unit 50 and the VGH off detection unit 52 to detect the high VCC off signal VCC_off. When the VGH off signal VGH_off is input, a power off detection signal of a high state is generated.

As such, the power-off detection unit 44 detects a case where the first base driving voltage VCC and the gate high voltage VGH are simultaneously changed to generate a power-off detection signal and time the power-off detection signal. Supply to the control unit 32. The power off detection unit 44 may be integrated with the timing controller 32 as one chip.

The timing controller 32 relays the video data R, G, and B from the graphics card 22 and supplies it to the data driver 34. In addition, the timing controller 32 generates control signals such as timing signals and polarity inversion signals for controlling the timing of the data and the gate drivers 34 and 36 in response to the timing control signal from the graphics card 22. do. In addition, when the power-off detection signal from the power-off detection unit 44 is input, the timing controller 32 generates a white data signal and supplies it to the data driver 34.

To this end, the timing controller 32 may include a timing control signal generator that generates a timing control signal, a polarity controller that generates a polarity inversion signal, a video data alignment unit that aligns and outputs video data, and a power-off detector. And a white data signal generator configured to generate a white data signal when a power off signal of a state is input.

The timing control signal generation unit controls the timing of the data driver 34 and the gate driver 36 using the main clock signal MCLK, the horizontal synchronization signal H, the vertical synchronization signal V, and the like from the graphics card 22. Will generate signals.

The polarity control unit generates a polarity inversion signal suitable for inversion driving such as dot inversion, line inversion, frame inversion, etc. in response to the control signals from the graphics card 22.

The white data signal generator supplies the white data signal to the video data alignment unit when the power off detection signal is input from the power off detection unit 44.

The video data aligning unit inputs the video data R, G, and B from the graphics card 22, and rearranges the video data so as to be suitable for driving the data driver 34. In addition, the video data alignment unit rearranges the white data signal supplied from the white data signal generator and supplies the data driver 34 to the data driver 34.

When the power supply is detected, the timing controller 32 generates a white data signal and supplies the white data signal to the data driver 34 like the normal video data, and drives the data driver 34 and the gate driver 36. 38) is displayed.

The gate driver 36 sequentially supplies the gate high voltage VGH to the gate lines G1 to Gn according to the control signal from the timing controller 32. The gate driver 36 supplies the gate low voltage VGL to a period when the gate high voltage VGH is not supplied to the gate lines G1 to Gn.

The data driver 34 converts the R, G, and B data signals from the timing controller 32 into a video voltage signal, which is an analog signal, so that one horizontal period in which the gate high voltage VGH is supplied to the gate lines G1 through Gn. Each horizontal video voltage signal is supplied to the data lines D1 to Dm. At this time, the gamma circuit 40 supplies the gamma voltage preset to the data driver 34 to have different voltage levels according to the voltage level of the video signal. Accordingly, the data driver 34 converts the RGB data signal into a video voltage signal using the gamma voltage from the gamma circuit 40.

The liquid crystal panel 38 is connected to the thin film transistor TFT formed at the intersection of the n gate lines GL1 to GLn and the m data lines D1 to Dm, and is connected to the thin film transistor TFT and has a matrix form. The liquid crystal cells are arranged as. The thin film transistor TFT supplies a video voltage signal from the data lines DL1 to DLm to the liquid crystal cell in response to the gate signal from the gate lines G1 to Gn. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor, so that the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell also includes a storage capacitor Cst connected to the previous gate line to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged. When the gate high voltage VGH is supplied to the gate line Gi, the thin film transistor TFT is turned on and the video voltage signal supplied to the data lines D1 to Dm is charged in the liquid crystal capacitor Clc. The video voltage charged in the liquid crystal capacitor Clc is maintained until the next video voltage is supplied by turning off the thin film transistor TFT by the gate low voltage VGL supplied to the gate line Gi. In this case, the storage capacitor Cst connected in parallel with the liquid crystal capacitor Clc minimizes the variation of the voltage charged in the liquid crystal capacitor Clc.

As described above, in the liquid crystal display module driving apparatus according to the present invention, the power-off detection unit 44 regards an arbitrary time point at which the first base driving voltage VCC and the gate high voltage VGH are simultaneously changed as the power-off time point. Generates a power off detection signal. The timing controller 32 generates a white data signal and supplies the white data signal to the data driver 34 and controls the data driver 34 and the gate driver 36 when a power-off detection signal of a specific state is input from the power-off detection unit 44. The white data signal is converted into a white voltage signal and supplied to the liquid crystal panel 38. Accordingly, when the system power supply unit 24 is turned off, the liquid crystal panel 38 may display a white signal to remove an afterimage caused by discharge. In this case, the power supply circuit 42 of the liquid crystal display module 30 generates the driving voltages of the liquid crystal display module 30 that converge to the ground voltage with a predetermined convergence time even after the system power supply unit 24 is turned off. The signal may be displayed on the liquid crystal display module 30 for at least one frame or more.

As described above, in the method and apparatus for driving the liquid crystal display module according to the present invention, when the power-off time is detected using the base driving voltage and the gate high voltage, the white signal is displayed on the liquid crystal panel before the power is turned off. This can eliminate the afterimage problem that the image disappears slowly.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (13)

In the method for driving the liquid crystal display module, Generating a white data signal by detecting an off point of the power supply unit through a base driving voltage and a gate high voltage supplied from the power supply unit of the liquid crystal display module; And displaying the white data signal on the liquid crystal display module. The method of claim 1, And when the base driving voltage and the gate high voltage are simultaneously changed, the power supply unit is regarded as an off point of the power supply unit. The method of claim 1, And sensing the white data signal on the liquid crystal display module by using the driving voltages converged to the ground voltage at a predetermined convergence time by the power supply unit after detecting the off point of the power supply unit. The method of claim 1 And the white data signal is displayed on the liquid crystal display module for at least one frame. A liquid crystal display module including a liquid crystal panel for displaying an image, a signal line driver circuit for driving signal lines of the liquid crystal panel, and a timing controller for controlling a driving timing of the signal line driver circuit and supplying a data signal; and; A power supply unit supplying a driving voltage required by the liquid crystal display module; A power off detection unit for detecting an off point of the power supply unit through a base driving voltage and a gate high voltage supplied from the power supply unit; And the timing controller generates a white data signal to be displayed on the liquid crystal panel when the power off detection signal is supplied from the power off detection unit. The method of claim 5, The power off detection unit And detecting a time when the base driving voltage and the gate high voltage are simultaneously changed as an off point of the power supply unit to generate a power-off detection signal of the specific state. The method of claim 5, The power off detection unit A base driving voltage off detector for detecting a variable time point of the base driving voltage; A gate high voltage off detector for detecting a variable time point of the gate high voltage; And a logic sum gate for generating a power-off detection signal of the specific state when the base driving voltage and the gate high voltage are simultaneously detected. The method of claim 7, wherein The base driving voltage off detection unit A transistor configured to switch according to the voltage division ratio of the base driving voltage to output a voltage in a logic state, And controlling the base driving voltage variable time point by adjusting the partial pressure ratio of the base driving voltage. The method of claim 7, wherein The gate high voltage off detection unit A transistor configured to switch according to the voltage division ratio of the gate high voltage and output a voltage in a logic state; And controlling the base driving voltage variable time point by adjusting the voltage division ratio of the gate high voltage. The method of claim 5, The timing controller A white data signal generator for generating the white data signal when a power off detection signal of a specific state is supplied from the power off detector; A control signal generator for generating control signals for controlling driving timing of the signal line driver integrated circuit using input control signals; And a data alignment unit for aligning and outputting an input data signal and the white data signal. The method of claim 5, The liquid crystal display module displays the white data signal on the liquid crystal panel using the driving voltages converged to the ground voltage with a predetermined convergence time in the power supply unit after detecting the off point of the power supply unit. Device. The method of claim 5 And the liquid crystal display module displays the white data signal on the liquid crystal panel for at least one frame. The method of claim 5 And the power off detection unit is built in the timing control unit.