KR20030054229A - Method for forming metal line of semiconductor device - Google Patents

Method for forming metal line of semiconductor device Download PDF

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Publication number
KR20030054229A
KR20030054229A KR1020010084361A KR20010084361A KR20030054229A KR 20030054229 A KR20030054229 A KR 20030054229A KR 1020010084361 A KR1020010084361 A KR 1020010084361A KR 20010084361 A KR20010084361 A KR 20010084361A KR 20030054229 A KR20030054229 A KR 20030054229A
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South Korea
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film
titanium
forming
contact hole
semiconductor substrate
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KR1020010084361A
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Korean (ko)
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김영수
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주식회사 하이닉스반도체
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Publication of KR20030054229A publication Critical patent/KR20030054229A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a metal line of a semiconductor device is provided to be capable of improving the stability of data lines and preventing the degradation of devices. CONSTITUTION: After forming an insulating layer(22) on a semiconductor substrate(21), a contact hole is formed by selectively etching the insulating layer. A titanium film and a titanium silicide layer(25) are simultaneously formed on the insulating layer(22) and at the bottom of the contact hole, respectively by CVD(Chemical Vapor Deposition) using a heater for controlling temperature. After removing the titanium film without reacting the substrate, a barrier layer(26) and a conductive thin film(27) are sequentially formed on the resultant structure including the contact hole.

Description

반도체 소자의 금속배선 형성방법{method for forming metal line of semiconductor device}Method for forming metal line of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 공정 간소화 및 배선의 불량 발생율을 줄이는데 적당한 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device suitable for simplifying the process and reducing the occurrence rate of defective wiring.

일반적으로 금속배선 공정에 사용하고 있는 금속 박막의 증착 방법은 PVD(Physical Vapor Deposition)법을 이용하고 있다.In general, the deposition method of the metal thin film used in the metallization process uses a PVD (Physical Vapor Deposition) method.

상기 PVD 공정은 미세화되고 더욱 고집적화 되고 있는 현재의 디바이스(device) 개발을 고려할 때 적용하는데는 그 한계가 있다.The PVD process has its limitations in application in view of the development of current devices, which are becoming finer and more integrated.

따라서 PVD방법의 한계를 해결하기 위하여 적용하고 있는 것이 화학 기상 증착(Chemical Vapor Deposition : 이하 CVD 라고 한다) 방법이다.Therefore, in order to solve the limitations of the PVD method, a chemical vapor deposition (hereinafter referred to as CVD) method is applied.

상기 CVD 방법을 이용하여 물리적인 방법으로는 얻을 수 없는 스텝 커버레이지(step coverage)가 우수한 증착막을 얻을 수 있다는 것이 이 증착 방법의 가장 큰 특징이다.The biggest feature of this deposition method is that it is possible to obtain a deposition film having excellent step coverage which cannot be obtained by the physical method using the CVD method.

또한, 데이터 라인(data line) 역할을 하는 비트 라인(bit line)을 형성하는 물질에 있어서도 차세대 디바이스에서는 기존의 물질로서는 디바이스 리폰스 타임(device response time), 디바이스 스피드(device speed) 등의 문제를 극복하기 어렵기 때문에 이에 대한 해결책으로 전도성 물질인 텅스텐(Tungsten)막으로 많이 대체되어 지고 있는 상황이다.In addition, even in a material forming a bit line serving as a data line, in the next generation of devices, problems such as device response time, device speed, and the like as existing materials are encountered. As it is difficult to overcome, a solution to this situation is being replaced by a tungsten film, which is a conductive material.

이러한 추세에 비추어 볼 때 워드 라인(word line) 또는 데이터 라인의 경우 기존의 텅스텐 실리사이드(WSix) 물질 대신에 텅스텐막으로 전환하고 있는 추세이다.In light of this trend, word lines or data lines are being converted to tungsten films instead of conventional tungsten silicide (WSix) materials.

상기 데이터 라인의 형성에 있어서 커패시터(capacitor)가 비트 라인위에 형성되는 COB(Capacitor Over Bit line) 구조를 채택할 경우 무엇보다도 비트 라인을 형성한 후에 가해지는 고온의 열공정으로 인한 비트 라인의 열적 안정성이 문제가 된다.When the capacitor adopts a capacitor over bit line (COB) structure in which a capacitor is formed on the bit line, the thermal stability of the bit line due to the high temperature thermal process applied after the bit line is formed. This is a problem.

그러나 상기와 같은 종래의 반도체 소자의 금속배선 형성방법에 있어서 다음과 같은 문제점이 있었다.However, the above-described conventional method for forming metal wirings of semiconductor devices has the following problems.

즉, COB 구조에서 비트 라인을 형성한 후에 가해지는 고온의 열 공정으로 인하여 비트 라인의 열적 안정성이 취약하고, 이러한 문제를 해결하기 위하여 대부분 PVD 방법을 이용하여 금속 확산 방지막을 형성하고 있지만 공정 안정성 문제 및 디바이스 특성 열화로 많은 어려움이 있다.That is, the thermal stability of the bit line is weak due to the high temperature thermal process applied after the bit line is formed in the COB structure. To solve this problem, most of the metal diffusion barriers are formed by using the PVD method. And device characteristics deteriorate.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 데이터 라인의 안정성을 향상함과 동시에 디바이스의 특성 열화를 방지하도록 한 반도체 소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for forming metal wirings of a semiconductor device to improve the stability of data lines and to prevent deterioration of device characteristics.

도 1a 내지 도 1c는 본 발명에 의한 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도1A to 1C are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 절연막21 semiconductor substrate 22 insulating film

23 : 콘택홀 24 : 티타늄막23 contact hole 24 titanium film

25 : 티타늄 실리사이드막 26 : 질화 티타늄막25: titanium silicide film 26: titanium nitride film

27 : 텅스텐막27: tungsten film

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 금속배선 형성방법은 반도체 기판상에 절연막을 형성하는 단계와, 상기 반도체 기판의 표면이 소정부분 노출되도록 상기 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계와, 상기 콘택홀을 포함한 반도체 기판의 전면에 온도 조절이 가능한 히터를 사용한 화학 기상 증착법으로 티타늄막을 형성함과 동시에 콘택홀의 저면에 티타늄 실리사이드막을 형성하는 단계와, 상기 반도체 기판과 반응하지 않는 티타늄막을 제거하는 단계와, 상기 콘택홀을 포함한 반도체 기판의 전면에 베리어 금속막 및 전도성 박막을 차례로 형성하는 단계를 포함하여 형성함을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a metal wiring in a semiconductor device, the method including forming an insulating film on a semiconductor substrate, and selectively removing the insulating film to expose a predetermined portion of the surface of the semiconductor substrate. Forming a titanium film by a chemical vapor deposition method using a heater capable of temperature control on the entire surface of the semiconductor substrate including the contact hole, and simultaneously forming a titanium silicide film on a bottom surface of the contact hole, and reacting with the semiconductor substrate. And removing a titanium film which is not used, and sequentially forming a barrier metal film and a conductive thin film on the front surface of the semiconductor substrate including the contact hole.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 금속배선 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a metal wiring forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

계속적으로 디바이스의 스케일다운(scaling down)을 통한 고집적화와 물질 변경을 통한 디바이스 스피드의 요구가 증가함에 따라 차세대 디바이스에서는 물질변경과 공정방법 변경 등을 통하여 새로운 공정의 개발이 이루어져야 한다.As the demand for device speed through high integration and material change through scaling down of devices continues to increase, next-generation devices need to develop new processes through material change and process method change.

데이터 라인의 경우에 있어서도 이러한 요구를 만족시키기 위하여 많은 실혐과 연구가 이루어지고 있는데 본 발명에서는 CVD 방법을 이용하여 선택적으로 티타늄 실리사이드막을 형성한 후 금속배선을 형성하는 방법에 대하여 기술하고자 한다.In the case of a data line, many demonstrations and studies have been conducted to satisfy such demands. In the present invention, a method of forming a metal wiring after selectively forming a titanium silicide layer using a CVD method will be described.

도 1a 내지 도 1c는 본 발명에 의한 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to the present invention.

도 1a에 도시된 바와 같이, 반도체 기판(21)상에 절연막(22)을 형성하고, 포토 및 식각 공정을 이용하여 상기 반도체 기판(21)의 표면이 소정 부분 노출되도록 상기 절연막(22)을 선택적으로 제거하여 콘택홀(23)을 형성한다.As shown in FIG. 1A, the insulating film 22 is formed on the semiconductor substrate 21, and the insulating film 22 is selectively selected to expose a predetermined portion of the surface of the semiconductor substrate 21 by using a photo and etching process. To form a contact hole 23.

도 1b에 도시된 바와 같이, 상기 콘택홀(23)을 포함한 반도체 기판(21)의 전면에 CVD법으로 티타늄(Ti)막(24)을 30 ~ 200Å 두께로 증착한다.As shown in FIG. 1B, a titanium (Ti) film 24 is deposited to a thickness of 30 to 200 Å on the entire surface of the semiconductor substrate 21 including the contact hole 23 by CVD.

여기서 상기 티타늄막(24)을 증착할 때 온도 조절이 가능한 히터(heater)를 사용함으로서 티타늄 실리사이드막(25)을 형성하기 위한 열 공정을 생략한다.When the titanium film 24 is deposited, a thermal process for forming the titanium silicide film 25 is omitted by using a heater capable of temperature control.

한편, 상기 온도 조절(550 ~ 700℃)이 가능한 히터를 사용함으로서 상기 티타늄막(24)이 증착될 때 반도체 기판(21)의 실리콘(Si)과 반응하여 콘택홀(23)의 저면에 티타늄 실리사이드막(25)이 형성된다.Meanwhile, when the titanium film 24 is deposited by using a heater capable of controlling the temperature (550 to 700 ° C.), titanium silicide is formed on the bottom surface of the contact hole 23 by reacting with silicon (Si) of the semiconductor substrate 21. The film 25 is formed.

도 1c에 도시된 바와 같이, 상기 반도체 기판(21)과 반응하지 않은티타늄막(24)을 제거한다.As shown in FIG. 1C, the titanium film 24 that does not react with the semiconductor substrate 21 is removed.

여기서 상기 티타늄막(24)은 황산류의 용액(H2SO4+ DI)을 이용하여 제거한다.The titanium film 24 is removed using a solution of sulfuric acid (H 2 SO 4 + DI).

만약, 상기 티타늄막(24)이 제거되지 않고 그대로 남아 있을 경우 후속 열처리 공정에 의해 그 표면에 산화 티타늄(TiOx)막이 형성되고, 상기 TiOx막은 데이터 라인을 식각하는 과정에서 잘 제거되지 않기 때문에 라인 숏트(line short)를 유발할 수 있기 때문에 깨끗하게 제거함으로서 불량 발생율을 줄일 수 있다.If the titanium film 24 is not removed and remains as it is, a titanium oxide (TiOx) film is formed on the surface by a subsequent heat treatment process, and since the TiOx film is not removed during the etching of the data line, the line short (line short) can cause line shorts can be removed to reduce the incidence of defects.

이어, 상기 콘택홀(23)을 포함한 반도체 기판(21)의 전면에 CVD법으로 질화 티타늄(TiN)막(26)을 형성한다.Next, a titanium nitride (TiN) film 26 is formed on the entire surface of the semiconductor substrate 21 including the contact hole 23 by CVD.

여기서 상기 질화 티타늄막(26)은 100 ~ 400Å 두께로 증착하고, 증착온도는 600 ~ 700℃이다.The titanium nitride film 26 is deposited to a thickness of 100 ~ 400 ~, the deposition temperature is 600 ~ 700 ℃.

이어, 상기 질화 티타늄막(26)상에 CVD법으로 텅스텐막(27)을 400 ~ 1500Å 두께로 증착하고, 포토 및 식각 공정을 이용하여 상기 텅스텐막(27) 및 질화 티타늄막(26)을 선택적으로 제거하여 금속배선을 형성한다.Subsequently, a tungsten film 27 is deposited to a thickness of 400 to 1500 Å on the titanium nitride film 26 by CVD, and the tungsten film 27 and the titanium nitride film 26 are selectively selected using a photolithography process. To form metal wiring.

이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 금속배선 형성방법은 다음과 같은 효과가 있다.As described above, the metal wiring forming method of the semiconductor device according to the present invention has the following effects.

첫째, CVD 방법을 이용한 티타늄막 증착시 온도 조절이 가능한 히터를 채용함으로서 티타늄 실리사이드막을 형성하기 위한 후속 열처리 공정을 생략할 수 있어 공정을 단순화시킬 수 있다.First, by employing a temperature controllable heater during the deposition of a titanium film using a CVD method, the subsequent heat treatment process for forming the titanium silicide film can be omitted, thereby simplifying the process.

둘째, 기판과 반응하지 않는 티타늄막을 깨끗하게 제거함으로서 불량 발생율을 줄일 수 있다.Second, it is possible to reduce the failure rate by removing the titanium film that does not react with the substrate clean.

셋째, 후속의 고온 열처리 공정에서도 확산 방지막 역할을 수행함으로서 디바이스가 정상적인 동작을 할 수 있다.Third, the device may operate normally by acting as a diffusion barrier in a subsequent high temperature heat treatment process.

Claims (5)

반도체 기판상에 절연막을 형성하는 단계;Forming an insulating film on the semiconductor substrate; 상기 반도체 기판의 표면이 소정부분 노출되도록 상기 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계;Selectively removing the insulating layer so as to expose a predetermined portion of the surface of the semiconductor substrate to form a contact hole; 상기 콘택홀을 포함한 반도체 기판의 전면에 온도 조절이 가능한 히터를 사용한 화학 기상 증착법으로 티타늄막을 형성함과 동시에 콘택홀의 저면에 티타늄 실리사이드막을 형성하는 단계;Forming a titanium film by a chemical vapor deposition method using a temperature-controlled heater on the front surface of the semiconductor substrate including the contact hole and simultaneously forming a titanium silicide film on a bottom surface of the contact hole; 상기 반도체 기판과 반응하지 않는 티타늄막을 제거하는 단계;Removing a titanium film that does not react with the semiconductor substrate; 상기 콘택홀을 포함한 반도체 기판의 전면에 베리어 금속막 및 전도성 박막을 차례로 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 금속배선 형성방법.And forming a barrier metal film and a conductive thin film in order on the front surface of the semiconductor substrate including the contact hole. 제 1 항에 있어서, 상기 티타늄막은 30 ~ 200Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the titanium film is formed to a thickness of 30 to 200 kHz. 제 1 항에 있어서, 상기 티타늄막은 황산류 용액을 이용하여 제거하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the titanium film is removed using a sulfuric acid solution. 제 1 항에 있어서, 상기 히터의 온도는 550 ~ 700℃인 것을 특징으로 하는반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the temperature of the heater is 550 ~ 700 ℃. 제 1 항에 있어서, 상기 베리어 금속막은 질화 티타늄막을 100 ~ 400Å 두께로 증착하여 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the barrier metal film is formed by depositing a titanium nitride film with a thickness of 100 to 400 GPa.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100541696B1 (en) * 1998-09-18 2006-03-22 주식회사 하이닉스반도체 Metal silicide forming method of semiconductor device
KR100702028B1 (en) * 2005-10-31 2007-03-30 삼성전자주식회사 Method of fabricating semiconductor device having metal silicide layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100541696B1 (en) * 1998-09-18 2006-03-22 주식회사 하이닉스반도체 Metal silicide forming method of semiconductor device
KR100702028B1 (en) * 2005-10-31 2007-03-30 삼성전자주식회사 Method of fabricating semiconductor device having metal silicide layer

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