KR20030053084A - Method for fabricating silicon wafer - Google Patents

Method for fabricating silicon wafer Download PDF

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KR20030053084A
KR20030053084A KR1020010083118A KR20010083118A KR20030053084A KR 20030053084 A KR20030053084 A KR 20030053084A KR 1020010083118 A KR1020010083118 A KR 1020010083118A KR 20010083118 A KR20010083118 A KR 20010083118A KR 20030053084 A KR20030053084 A KR 20030053084A
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wafer
bare wafer
bare
double
silicon
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KR1020010083118A
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Korean (ko)
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공순현
윤종욱
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주식회사 실트론
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Publication of KR20030053084A publication Critical patent/KR20030053084A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02019—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE: A method for fabricating a silicon wafer is provided to simplify a fabricating process and reduce damage to an edge of a wafer and minimizing a decrease of a thickness of a bare wafer by eliminating the necessity of a lapping process. CONSTITUTION: A silicon single crystal ingot is grown and sliced to form a bare wafer(S101). An edge polishing process is performed to make the shape of the edge of the bare wafer uniform(S102). An etch process is performed to eliminate the damage to the surface of the bare wafer(S103). A double surface grinding process is performed to reduce the thickness difference of the surface of the bare wafer and improve planarization(S104). A double surface polishing process is performed to reduce the surface roughness of the bare wafer and make the surface of the bare wafer become a mirror surface(S105).

Description

실리콘 웨이퍼의 제조방법{Method for fabricating silicon wafer}Method for fabricating silicon wafers

본 발명은 실리콘 웨이퍼의 제조방법에 관한 것으로, 특히 12인치 실리콘 웨이퍼의 가공 공정중에 식각공정과 양면 연삭 공정을 추가 실시하여 고품질 실리콘 웨이퍼를 제조하기 위한실리콘 웨이퍼의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a silicon wafer, and more particularly, to a method of manufacturing a silicon wafer for manufacturing a high quality silicon wafer by additionally performing an etching process and a double-sided grinding process during a processing process of a 12 inch silicon wafer.

일반적으로 반도체장치는 웨이퍼상에 형성되며 이때 사용되는 웨이퍼들 중, 8인치의 지름을 가지는 웨이퍼를 형성하는 방법은 다음과 같다.In general, a semiconductor device is formed on a wafer, and among the wafers used, a method of forming a wafer having a diameter of 8 inches is as follows.

먼저 초크랄스키(Czochralski) 결정성장법 또는 플로트존(Float zone) 결정 성장법에 의해서 형성된 단결정 실리콘 봉을 와이어소우, I.D 소우, O.D소우등을 사용하여 얇게 슬라이싱하는 공정을 실시하여 베어 웨이퍼를 형성한다(S1).First, a bare wafer is formed by thinly slicing single crystal silicon rods formed by Czochralski crystal growth method or Float zone crystal growth method using wire saws, ID saws, and OD saws. (S1).

베어 웨이퍼의 가장자리가 일정한 형상을 가지도록 가장자리 연삭공정을 실시한다(S2).The edge grinding process is performed so that the edge of the bare wafer has a certain shape (S2).

그리고 와이어를 이용한 절단 공정 후 절단공정에서 발생되는 베어 웨이퍼의 표면손상을 감소시키고 베어 웨이퍼 표면의 평탄도를 향상시키기 위하여 슬러리를 사용하여 베어 웨이퍼 전, 후면을 일정한 두께로 연마하는 래핑공정을 실시한다(S3). 이때 래핑공정으로 베어 웨이퍼의 두께가 70㎛감소된다.In order to reduce the surface damage of the bare wafer and improve the flatness of the bare wafer surface after the cutting process using the wire, a lapping process is performed to polish the back and front surfaces of the bare wafer to a certain thickness using a slurry. (S3). At this time, the thickness of the bare wafer is reduced by 70 μm by the lapping process.

이후 래핑공정이 완료된 후 래핑공정에서 발생된 미세균열이나 표면 결함이 여전히 존재하므로 이를 제거하기 위해 화학적 반응을 이용하여 베어 웨이퍼를 식각한다(S4). 이때 식각공정으로 베어 웨이퍼가 30㎛감소된다.Thereafter, since the microcracks or surface defects generated in the lapping process still exist after the lapping process is completed, the bare wafer is etched using a chemical reaction to remove them (S4). At this time, the bare wafer is reduced by 30 μm by the etching process.

그리고 식각 공정 후에 웨이퍼의 평탄도를 향상시키기 위한 단면 연삭공정(S5)을 실시한다. 이때 단면 연삭 공정으로 인해 5~10㎛의 베어 웨이퍼 두께가 감소된다.After the etching process, a cross-sectional grinding step S5 is performed to improve the flatness of the wafer. At this time, the bare wafer thickness of 5 ~ 10㎛ is reduced due to the cross-sectional grinding process.

마지막으로 베어 웨이퍼 표면을 경면화하기 위해 연마 공정(S6)을 실시하여 실리콘 웨이퍼를 제조한다.Finally, in order to mirror the bare wafer surface, a polishing step (S6) is performed to manufacture a silicon wafer.

그러나 이러한 종래 기술에 따른 일련의 공정은 절단공정에서 폴리싱 공정까지 실시하여 실리콘 웨이퍼를 제조하는 과정에서 베어 웨이퍼의 두께가 감소되는 문제점이 있었다. 이때 감소되는 베어 웨이퍼의 두께는 100㎛이상으로 실리콘 웨이퍼의 제조원가를 상승시키는 문제점이 있었다.However, such a series of processes according to the prior art has a problem in that the thickness of the bare wafer is reduced in the process of manufacturing the silicon wafer by performing the cutting process to the polishing process. At this time, the reduced thickness of the bare wafer has a problem of increasing the manufacturing cost of the silicon wafer to more than 100㎛.

그리고 래핑공정시 베어 웨이퍼의 가장자리 부분이 캐리어(carrier)와 접촉되어 스크래치(SCRATCH), 딤플(DIMPLE), 블로큰(BROKEN)등의 가공불량 현상을 발생시켜 실리콘 웨이퍼의 전기적 특성을 저하시키는 문제점이 있었다.In the lapping process, the edge of the bare wafer comes into contact with the carrier, causing defects such as scratches, dimples, and blockons, which degrades the electrical characteristics of the silicon wafer. there was.

또한 래핑공정 후 베어 웨이퍼의 두께 편차(TTV)가 크게 되어 베어 웨이퍼의 형상을 후속공정인 연마공정에 적합하게 제어하기 곤란하여 단면 연삭 공정이 추가적으로 필요하게 되는 문제점이 있었다.In addition, since the thickness variation (TTV) of the bare wafer becomes large after the lapping process, it is difficult to control the shape of the bare wafer appropriately for the polishing process which is a subsequent process, so that a cross-sectional grinding process is additionally required.

따라서 본 발명은 상기한 종래 기술의 문제점을 해결하기 위한 것으로 실리콘 웨이퍼를 제조하는 공정시 베어 웨이퍼의 두께 감소량을 최소화하고, 실리콘 웨이퍼의 가장자리의 특성을 향상시키는 것을 그 목적으로 한다.Accordingly, an object of the present invention is to minimize the reduction in thickness of the bare wafer and to improve the characteristics of the edge of the silicon wafer in the process of manufacturing a silicon wafer.

상기한 목적을 달성하기 위한 본 발명에 따른 실리콘 웨이퍼의 제조방법은 단면 지름이 12인치인 실리콘 단결정 봉을 성장시킨 후 슬라이싱하여 베어 웨이퍼를 형성하는 절단공정과; 상기 베어 웨이퍼 가장자리의 형상을 일정하게 하기 위한 연마공정과; 상기 연마공정 후, 상기 베어 웨이퍼 표면의 손상을 제거하기 위한 식각공정과; 상기 식각공정 후, 상기 베어 웨이퍼의 표면 두께차를 감소시키고 평탄도를 향상하기 위한 양면 동시연삭공정과; 상기 양면 동시 연삭공정 후 , 상기 베어 웨이퍼의 표면 거칠기를 감소시키고 경면화하기 위한 양면 동시 연마 공정을 포함하여 이루어진다.Method for manufacturing a silicon wafer according to the present invention for achieving the above object is a cutting step of forming a bare wafer by growing and slicing a silicon single crystal rod having a cross-sectional diameter of 12 inches; A polishing step for making the shape of the bare wafer edge constant; An etching process for removing damage to the bare wafer surface after the polishing process; After the etching process, a double-sided simultaneous grinding process for reducing the surface thickness difference of the bare wafer and improving the flatness; After the double-sided simultaneous grinding process, a double-sided simultaneous polishing process is performed to reduce and mirror the surface roughness of the bare wafer.

제 1도는 종래 기술에 따른 실리콘 웨이퍼의 제조 방법을 도시한 순서도.1 is a flow chart showing a method of manufacturing a silicon wafer according to the prior art.

제 2도는 본 발명에 따른 실리콘 웨이퍼의 제조 방법을 도시한 순서도.2 is a flow chart showing a method of manufacturing a silicon wafer according to the present invention.

이하 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 12인치 베어 웨이퍼에 가장자리 연마공정, 식각공정, 양면 동시 연삭공정, 양면 동시 연마공정을 순차적으로 실시하여 이루어진다.The present invention is performed by sequentially performing the edge polishing process, etching process, double-sided simultaneous grinding process, double-sided simultaneous polishing process on a 12-inch bare wafer.

도1은 본 발명에 따른 실리콘 웨이퍼의 제조방법을 개략적으로 도시한 공정 순서도이다.1 is a process flowchart schematically showing a method of manufacturing a silicon wafer according to the present invention.

먼저 도1에 도시된 바와같이, 초크랄스키 결정성장법 또는 플로트존 결정 성장법에 의해서 형성된 단면 지름이 12인치인 단결정 실리콘 봉을 와이어소우, I.D 소우,O.D소우등을 사용하여 얇게 슬라이싱하는 공정을 실시하여 베어 웨이퍼를 형성한다.First, as shown in FIG. 1, a process of thinly slicing single crystal silicon rods having a cross-sectional diameter of 12 inches formed by Czochralski crystal growth method or float zone crystal growth method using wire saw, ID saw, OD saw, etc. To form a bare wafer.

본 발명에 따라 제조된 실리콘 웨이퍼와, 본 발명에 따른 가공공정이 완료되지 않은 웨이퍼를 구분하기 위해서 가공공정을 실시하지 않은 웨이퍼를 편의상 베어 웨이퍼(bare wafer)라 하고 가공 공정이 완료된 웨이퍼를 실리콘 웨이퍼라 칭한다.In order to distinguish between the silicon wafer manufactured according to the present invention and the wafer which has not been processed according to the present invention, the wafer which has not been processed is called a bare wafer for convenience, and the wafer which has been processed is a silicon wafer. It is called.

베어 웨이퍼의 가장자리가 일정한 형상을 가지도록 가장자리 연삭 공정을 실시한다(S101).An edge grinding process is performed so that the edge of the bare wafer has a constant shape (S101).

그리고 웨이퍼의 표면 손상이나 미세결함을 제거하기 위해서 화학적 반응을 이용하여 베어 웨이퍼의 표면을 식각한다. 이때 베어 웨이퍼의 두께는 30㎛ 정도 감소된다(S102).Then, the surface of the bare wafer is etched by using a chemical reaction in order to remove surface damage or fine defects of the wafer. At this time, the thickness of the bare wafer is reduced by about 30㎛ (S102).

식각이 완료된 후 베어 웨이퍼의 평탄도를 향상시키고 연마 공정에 적합한 베어 웨이퍼 형상으로 하기 위한 양면 동시 연삭공정을 진행한다(S103).After etching is completed, a double-sided simultaneous grinding process is performed to improve the flatness of the bare wafer and to form a bare wafer shape suitable for the polishing process (S103).

양면 동시 연삭공정은 다이아몬드 휠이 부착된 연삭기를 이용하여 베어 웨이퍼의 전, 후면을 동시에 연삭하여 베어 웨이퍼의 평탄도를 향상시킨다. 이때 베어 웨이퍼의 두께는 30~60㎛정도 감소된다.Double-sided simultaneous grinding process improves the flatness of the bare wafer by simultaneously grinding the front and the back side of the bare wafer using a diamond wheel attached grinding machine. At this time, the thickness of the bare wafer is reduced by about 30 ~ 60㎛.

양면 동시 연삭공정이 완료된 후 베어 웨이퍼의 표면을 경면화하기 위해 양면 동시 연마공정을 진행하여 실리콘 웨이퍼를 완성한다(S104).After the double-sided simultaneous grinding process is completed, the double-sided simultaneous polishing process is performed to mirror the surface of the bare wafer to complete the silicon wafer (S104).

이상에서 설명한 바와 같이, 본 발명은 래핑공정을 실시하지 않아 공정을 단순화시키면서 웨이퍼 가장자리의 손상을 감소시킨다.As described above, the present invention reduces the damage to the wafer edge while simplifying the process by not performing the lapping process.

그리고 양면 동시 연삭공정은 래핑공정과 달리 슬러리를 사용하지 않으므로 슬러리의 사용에 따른 제조비용이 추가되지 않으므로, 실리콘 웨이퍼의 제조단가를 감소시켜 생산성을 향상시킬 수 있다. 또한, 연마공정에 필요한 평탄도를 향상시키고 웨이퍼 형상으로 제어가 가능하여 고품질 실리콘 웨이퍼를 생산할 수 있다.In addition, since the double-sided simultaneous grinding process does not use a slurry unlike the lapping process, the manufacturing cost is not added due to the use of the slurry, thereby reducing the manufacturing cost of the silicon wafer and improving productivity. In addition, the flatness required for the polishing process can be improved and the wafer shape can be controlled to produce high quality silicon wafers.

또한 종래의 실리콘 웨이퍼 제조시 보다 실리콘 웨이퍼의 두께의 제거량이 10㎛이상 감소됨으로 실리콘 웨이퍼의 제조원가를 대폭 절감시킬 수 있다.In addition, since the removal amount of the thickness of the silicon wafer is reduced by 10 µm or more, the manufacturing cost of the silicon wafer can be greatly reduced than the conventional silicon wafer manufacturing.

Claims (2)

실리콘 단결정 봉을 성장시킨 후 슬라이싱하여 베어 웨이퍼를 형성하는 절단공정과;A cutting step of growing a silicon single crystal rod and slicing to form a bare wafer; 상기 베어 웨이퍼 가장자리의 형상을 일정하게 하기 위한 가장자리 연삭공정과;An edge grinding step for making the shape of the bare wafer edge constant; 상기 연마공정 후, 상기 베어 웨이퍼 표면의 손상을 제거하기 위한 식각공정과;An etching process for removing damage to the bare wafer surface after the polishing process; 상기 식각공정 후, 상기 베어 웨이퍼의 표면 두께차를 감소시키고 평탄도를 향상하기 위한 양면 동시 연삭 공정과;After the etching process, a double-sided simultaneous grinding process for reducing the surface thickness difference of the bare wafer and improving the flatness; 상기 양면 동시 연삭공정 후 , 상기 베어 웨이퍼의 표면 거칠기를 감소시키고 경면화하기 위한 양면 동시 연마 공정을 포함하여 이루어지는 것을 특징으로 하는 실리콘 웨이퍼의 제조방법.And a double-sided simultaneous polishing step for reducing and mirror-mirroring the surface roughness of the bare wafer after the double-sided simultaneous grinding step. 제1항에 있어서,The method of claim 1, 상기 실리콘 단절봉은 단면 지름이 12인치인 것을 사용하는 것을 특징으로 하는 실리콘 웨이퍼의 제조방법.The silicon disconnection rod is a silicon wafer manufacturing method, characterized in that using the cross-sectional diameter of 12 inches.
KR1020010083118A 2001-12-22 2001-12-22 Method for fabricating silicon wafer KR20030053084A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8389409B2 (en) 2009-06-24 2013-03-05 Siltronic Ag Method for producing a semiconductor wafer

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