KR20030049582A - method for forming copper line - Google Patents

method for forming copper line Download PDF

Info

Publication number
KR20030049582A
KR20030049582A KR1020010079824A KR20010079824A KR20030049582A KR 20030049582 A KR20030049582 A KR 20030049582A KR 1020010079824 A KR1020010079824 A KR 1020010079824A KR 20010079824 A KR20010079824 A KR 20010079824A KR 20030049582 A KR20030049582 A KR 20030049582A
Authority
KR
South Korea
Prior art keywords
copper
film
forming
deposition
diffusion barrier
Prior art date
Application number
KR1020010079824A
Other languages
Korean (ko)
Other versions
KR100744599B1 (en
Inventor
이덕원
이세영
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020010079824A priority Critical patent/KR100744599B1/en
Publication of KR20030049582A publication Critical patent/KR20030049582A/en
Application granted granted Critical
Publication of KR100744599B1 publication Critical patent/KR100744599B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A method for forming a copper wiring in a semiconductor device is provided to be capable of stabilizing the CMP(Chemical Mechanical Polishing) without using additional annealing. CONSTITUTION: A desired pattern(102) is formed on a semiconductor substrate(100). After forming a diffusion barrier layer(110) on the desired pattern(102), a copper seed layer is deposited on the resultant structure. The first copper film is formed by electroplating of the copper seed layer. The second copper film is formed by high temperature sputtering of the first copper layer. A copper wiring(121) is then formed by CMP of the second copper film.

Description

구리 배선 형성 방법{method for forming copper line}Method for forming copper line

본 발명은 반도체장치의 형성 방법에 관한 것으로, 보다 상세하게는 고온 스퍼터링 방식을 적용하여 구리 금속배선을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a copper metal wiring by applying a high temperature sputtering method.

현재 구리를 이용한 금속 배선으로 전기 도금 증착 방법이 널리 사용되고 있다. 상기 전기 도금 증착 방법은 높은 종횡비를 가진 패턴을 채울 수 있는 반면에, 사용되는 첨가제로 인해 패턴 위에 과도하게 증착되는 오버플랫팅(overplating) 문제가 있다.Currently, electroplating deposition methods are widely used for metal wiring using copper. While the electroplating deposition method can fill patterns with high aspect ratios, there is a problem of overplating that is overdeposited on the pattern due to the additives used.

따라서, 이를 방지하기 위해, 미세 패턴에서의 필링(filling)을 이루는 첨가제와, 필링이 이루어지는 동안 패턴이 없는 부분에서의 증착을 억제시키는 첨가제와, 미세 패턴에서의 필링이 이루어진 후에 미세 패턴 위로 과도한 증착 (overplating)이 발생하는 것을 억제시키는 첨가제를 모두 포함한 3성분 첨가제를 사용하거나 역 펄스 플레이팅(reverse pulse plating)이 적용되고 있다.Therefore, to prevent this, additives for filling in fine patterns, additives for suppressing deposition in areas without patterns during filling, and excessive deposition over fine patterns after filling in fine patterns (Three-component additives including all additives that suppress the occurrence of overplating) or reverse pulse plating are applied.

그러나, 상기 3 성분 첨가제의 경우는 변수가 증가함에 따른 관리가 어렵고, 역 펄스 플레이팅의 경우는 결점(defect) 발생을 증가시켰다.However, in the case of the three-component additives, it is difficult to manage as the variable increases, and in the case of reverse pulse plating, defect occurrence is increased.

또한, 전기 도금으로 증착한 구리막은 결정립의 크기가 0.1㎛ 이하로 작음에 따라 상온에서도 물성이 변하는 특성을 가진다. 이때문에 화학적-기계적 연마 공정의 안정화를 위하여 전기 도금 증착 후에 열처리 공정이 반드시 수반되어야 하는 문제점이 발생되었다.In addition, the copper film deposited by electroplating has the property that the physical properties change even at room temperature as the size of the crystal grains is less than 0.1㎛. For this reason, there is a problem that the heat treatment process must be accompanied after the electroplating deposition in order to stabilize the chemical-mechanical polishing process.

이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 별도의 열처리 공정이 필요없으며, 화학적-기계적 연마 공정의 안정화를 가져올 수 있는 구리 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made in order to solve the above problems, and does not require a separate heat treatment process, and an object thereof is to provide a method for forming a copper wiring, which can bring about stabilization of a chemical-mechanical polishing process.

도 1a 내지 도 1d는 본 발명에 따른 구리 배선 형성 방법을 도시한 공정단면도.1A to 1D are cross-sectional views illustrating a method for forming a copper wiring according to the present invention.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

100. 반도체기판 102. 패턴100. Semiconductor substrate 102. Pattern

110. 확산방지막 120. 구리 씨드막110. Diffusion barrier 120. Copper seed membrane

121, 122. 구리막 123. 구리 배선121, 122. Copper Film 123. Copper Wiring

상기 목적을 달성하기 위한 본 발명의 구리 배선 형성 방법은 반도체기판에 소정 패턴을 형성하는 단계와, 패턴을 포함한 기판 상에 구리 씨드막을 증착하는 단계와, 구리 씨드막에 전기 도금 증착 방식을 적용하여 제 1구리막을 형성하는 단계와, 제 1구리막에 고온 스퍼터링 방식을 적용하여 제 2구리막을 형성하는 단계와, 제 2구리막을 연마하여 구리배선을 형성하는 단계를 포함한 것을 특징으로한다.The copper wiring forming method of the present invention for achieving the above object comprises the steps of forming a predetermined pattern on a semiconductor substrate, depositing a copper seed film on a substrate including the pattern, by applying an electroplating deposition method to the copper seed film Forming a first copper film, forming a second copper film by applying a high-temperature sputtering method to the first copper film, and forming a copper wiring by polishing the second copper film.

상기 스퍼터링 공정은 150∼400℃ 온도에서 진행하는 것을 특징으로 한다.The sputtering process is characterized in that proceeds at a temperature of 150 ~ 400 ℃.

상기 구리 씨드막을 증착하기 전에, 패턴을 포함한 기판 상에 확산방지막을 형성하는 단계를 추가하는 것을 특징으로 한다.Before the copper seed film is deposited, the method may further include forming a diffusion barrier on the substrate including the pattern.

상기 확산방지막으로 Ta, TaN, TiN 또는 WN 중 어느 하나의 막을 이용한 것을 특징으로 한다.As the diffusion barrier, any one of Ta, TaN, TiN, or WN is used.

상기 확산방지막은 100∼1000Å두께로 증착하는 것을 특징으로 한다.The diffusion barrier is characterized in that the deposition to 100 ~ 1000 100 thickness.

상기 구리 씨드막은 250∼2500Å 두께로 증착하는 것을 특징으로 한다.The copper seed film is characterized in that the deposition to a thickness of 250 ~ 25002.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1d는 본 발명에 따른 구리 배선 형성 방법을 도시한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a copper wiring according to the present invention.

본 발명에 따른 구리 배선 형성 방법은, 도 1a에 도시된 바와 같이, 먼저, 반도체기판(100) 상에 포토리쏘그라피 공정에 의해 원하고자 하는 패턴(102)을 형성한다. 이어서, 상기 패턴(102)을 포함한 기판 상에 확산방지막(110) 및 구리 씨드(seed)막(120)을 차례로 증착한다. 이때, 상기 확산방지막(110)으로는 Ta, TaN, TiN 또는 WN 중 어느 하나의 막을 이용하여 100∼1000Å두께로 증착한다.In the method for forming a copper wiring according to the present invention, as shown in FIG. 1A, first, a desired pattern 102 is formed on a semiconductor substrate 100 by a photolithography process. Subsequently, the diffusion barrier film 110 and the copper seed film 120 are sequentially deposited on the substrate including the pattern 102. At this time, the diffusion barrier 110 is deposited to a thickness of 100 ~ 1000Å by using any one of Ta, TaN, TiN or WN.

한다. 또한, 상기 확산방지막(110)과 구리 씨드막(120) 증착 공정은 스퍼터링(sputtering) 또는 화학기상증착(Chemical Vapor Deposition) 공정 모두 적용 가능하다. 상기 구리 씨드막(120)은 250∼2500Å 두께로 증착한다.do. In addition, the diffusion barrier 110 and the copper seed layer 120 deposition process may be applied to both sputtering or chemical vapor deposition (Chemical Vapor Deposition) process. The copper seed film 120 is deposited to a thickness of 250 ~ 2500Å.

그 다음, 도 1b에 도시된 바와 같이, 상기 구리 씨드막에 전기 도금 방법을 적용하여 상기 패턴(102)을 매립시키는 제 1구리막(121)을 증착한다.Next, as shown in FIG. 1B, a first copper film 121 for embedding the pattern 102 is deposited by applying an electroplating method to the copper seed film.

이때, 3성분 첨가제 또는 역 펄스 플레이팅의 적용이 모두 가능하나, 미세 패턴에서의 필링(filling)을 이루는 첨가제 및 필링이 이루어지는 동안 패턴이 없는 부분에서의 증착을 억제시키는 첨가제를 포함한 2성분 첨가제와 DC 플레이팅만으로도 진행이 가능하다.At this time, it is possible to apply all three-component additives or reverse pulse plating, but two-component additives including additives for filling in the fine pattern and additives for suppressing deposition in the portion without the pattern during the filling and DC plating can be used to proceed.

이 후, 도 1c에 도시된 바와 같이, 상기 제 1구리막에 고온 스퍼터링 방법을 적용하여 제 2구리막(122)을 증착한다. 이때, 제 2구리막(122)은 이 후의 화학적-기계적 연마 공정에서 필요로 하는 두께까지 증착한다.Thereafter, as illustrated in FIG. 1C, a second copper film 122 is deposited by applying a high-temperature sputtering method to the first copper film. At this time, the second copper film 122 is deposited to a thickness required in a subsequent chemical-mechanical polishing process.

또한, 상기 제 2구리막(122) 증착 공정은 일반적인 스퍼터링 장비에 존재하는 백사이드(backside) 가스 투입 기능을 이용하여 150∼400℃ 온도에서 스퍼터링을 진행한다.In addition, in the deposition process of the second copper film 122, sputtering is performed at a temperature of 150 to 400 ° C. by using a backside gas input function existing in a general sputtering equipment.

고온 스퍼터링 방법을 적용한 제 2구리막(122) 증착은 스퍼터링의 균일한 증착성에 의해 전기 도금 증착 방법의 단점인 오버플레이팅을 피하고 고온에서 증착하는 동안 평탄화가 이루어져서 이 후 진행되는 화학적-기계적 연마 공정이 수월하다.The deposition of the second copper film 122 using the high-temperature sputtering method avoids overplating, which is a disadvantage of the electroplating deposition method due to the uniform deposition property of the sputtering, and is planarized during the deposition at high temperature so that the subsequent chemical-mechanical polishing process is performed. Easy

이어서, 도 1d에 도시된 바와 같이, 상기 제 2구리막(122)에 화학적-기계적 연마 공정을 진행하여 표면을 평탄화한다.Subsequently, as illustrated in FIG. 1D, the second copper film 122 is subjected to a chemical-mechanical polishing process to planarize the surface.

본 발명에서는 고온에서 제 2구리막을 증착함으로써 상온에서의 "셀프-어닐(self anneal)" 효과는 감소하고 전기 도금 증착한 제 1구리막에 대한열처리 효과가 있으므로 별도의 열처리 공정이 필요없이 화학적-기계적 연마 공정을 진행할 수 있다.In the present invention, by depositing the second copper film at a high temperature, the "self anneal" effect at room temperature is reduced and there is a heat treatment effect on the electroplated first copper film. The mechanical polishing process can proceed.

이상에서와 같이, 본 발명의 방법에서는 스퍼터링 공정의 균일한 증착성에 의하여 전기 도금 증착 공정의 단점인 오버플레이팅을 피할 수 있으므로 3성분 첨가제 또는 역 펄스 플레이팅의 사용이 불필요하다.As described above, in the method of the present invention, the overdeposition which is a disadvantage of the electroplating deposition process can be avoided by the uniform deposition property of the sputtering process, so that the use of the three-component additive or the reverse pulse plating is unnecessary.

또한, 고온 스퍼터링 공정이 진행되는 동안 제 2구리막의 평탄화가 이루어짐으로써 이 후의 화학적-기계적 연마 공정이 수월하며, 별도의 열처리 공정이 불필요하다.In addition, since the planarization of the second copper film is performed during the high temperature sputtering process, the subsequent chemical-mechanical polishing process is facilitated, and a separate heat treatment process is unnecessary.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (6)

반도체기판에 소정 패턴을 형성하는 단계와,Forming a predetermined pattern on the semiconductor substrate; 상기 패턴을 포함한 기판 상에 구리 씨드막을 증착하는 단계와,Depositing a copper seed film on the substrate including the pattern; 상기 구리 씨드막에 전기 도금 증착 방식을 적용하여 제 1구리막을 형성하는 단계와,Forming a first copper film by applying an electroplating deposition method to the copper seed film; 상기 제 1구리막에 고온 스퍼터링 방식을 적용하여 제 2구리막을 형성하는 단계와,Forming a second copper film by applying a high temperature sputtering method to the first copper film; 상기 제 2구리막을 연마하여 구리배선을 형성하는 단계를 포함한 것을 특징으로 하는 구리 배선 형성 방법.And polishing the second copper film to form copper wiring. 제 1항에 있어서, 상기 스퍼터링 공정은 150∼400℃ 온도에서 진행하는 것을 특징으로 하는 구리 배선형성 방법.The method of claim 1, wherein the sputtering process is performed at a temperature of 150 ~ 400 ℃. 제 1항에 있어서. 상기 구리 씨드막을 증착하기 전에 상기 패턴을 포함한 기판 상에 확산방지막을 형성하는 단계를 추가하는 것을 특징으로 하는 구리 배선형성 방법.The method of claim 1. And forming a diffusion barrier film on the substrate including the pattern before depositing the copper seed film. 제 1항에 있어서. 상기 확산방지막으로 Ta, TaN, TiN 또는 WN 중 어느 하나의 막을 이용한 것을 특징으로 하는 구리 배선형성 방법.The method of claim 1. Copper diffusion forming method, characterized in that using any one of Ta, TaN, TiN or WN as the diffusion barrier. 제 1항에 있어서. 상기 확산방지막은 100∼1000Å두께로 증착하는 것을 특징으로 하는 구리 배선 형성 방법.The method of claim 1. The diffusion barrier is a copper wiring forming method characterized in that the deposition to 100 ~ 1000∼ thickness. 제 1항에 있어서. 상기 구리 씨드막은 250∼2500Å 두께로 증착하는 것을 특징으로 하는 구리 배선 형성 방법.The method of claim 1. And the copper seed film is deposited to a thickness of 250 to 2500 kPa.
KR1020010079824A 2001-12-15 2001-12-15 method for forming copper line KR100744599B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020010079824A KR100744599B1 (en) 2001-12-15 2001-12-15 method for forming copper line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020010079824A KR100744599B1 (en) 2001-12-15 2001-12-15 method for forming copper line

Publications (2)

Publication Number Publication Date
KR20030049582A true KR20030049582A (en) 2003-06-25
KR100744599B1 KR100744599B1 (en) 2007-08-01

Family

ID=29575379

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010079824A KR100744599B1 (en) 2001-12-15 2001-12-15 method for forming copper line

Country Status (1)

Country Link
KR (1) KR100744599B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100866110B1 (en) * 2002-06-10 2008-10-31 매그나칩 반도체 유한회사 Method for forming copper line in semiconductor device
KR100871368B1 (en) * 2002-07-11 2008-12-02 주식회사 하이닉스반도체 Method For Forming Bit Line Spacer Of Semiconductor Device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3501265B2 (en) * 1997-10-30 2004-03-02 富士通株式会社 Method for manufacturing semiconductor device
JP3244058B2 (en) * 1998-07-28 2002-01-07 日本電気株式会社 Method for manufacturing semiconductor device
JP3187011B2 (en) * 1998-08-31 2001-07-11 日本電気株式会社 Method for manufacturing semiconductor device
JP2000183067A (en) * 1998-12-18 2000-06-30 Rohm Co Ltd Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100866110B1 (en) * 2002-06-10 2008-10-31 매그나칩 반도체 유한회사 Method for forming copper line in semiconductor device
KR100871368B1 (en) * 2002-07-11 2008-12-02 주식회사 하이닉스반도체 Method For Forming Bit Line Spacer Of Semiconductor Device

Also Published As

Publication number Publication date
KR100744599B1 (en) 2007-08-01

Similar Documents

Publication Publication Date Title
US20180374745A1 (en) Semiconductor Constructions; and Methods for Providing Electrically Conductive Material Within Openings
US20040219779A1 (en) Method and structure to improve reliability of copper interconnects
US7314827B2 (en) Method of manufacturing semiconductor device
KR20010051074A (en) Microstructure control of copper interconnects
KR20090057282A (en) Method and apparatus for workpiece surface modification for selective material deposition
US7659198B2 (en) In-situ deposition for Cu hillock suppression
EP1087432A1 (en) A method for improving the quality of a metal layer deposited from a plating bath
CN101908501A (en) Diffusion barrier and forming method thereof
EP1154472A1 (en) Process for fabrication of semiconductor devices having copper interconnects
KR100407681B1 (en) Method of forming a metal line in a semiconductor device
US20180005953A1 (en) Structure and method for improved stabilization of cobalt cap and/or cobalt liner in interconnects
KR20000058029A (en) Polishing method and polishing solution
KR100744599B1 (en) method for forming copper line
US20130078797A1 (en) Method for manufacturing a copper-diffusion barrier layer used in nano integrated circuit
KR100499557B1 (en) method for fabricating the wire of semiconductor device
US7204924B2 (en) Method and apparatus to deposit layers with uniform properties
US7172963B2 (en) Manufacturing method of semiconductor integrated circuit device that includes chemically and mechanically polishing two conductive layers using two polishing pads that have different properties
JP2004153274A (en) Damascene interconnection utilizing barrier metal layer deposited with metal carbonyl
JP2000252285A (en) Manufacture of semiconductor device
KR100701673B1 (en) METHOD FOR FORMING Cu WIRING OF SENICONDUCTOR DEVICE
US20040259348A1 (en) Method of reducing post-CMP defectivity
EP1063696A1 (en) A method for improving the quality of a metal-containing layer deposited from a plating bath
JP4733804B2 (en) Wiring formation method
JP2001053028A (en) Formation method of cu thin film
KR101621852B1 (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
N231 Notification of change of applicant
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130620

Year of fee payment: 7

FPAY Annual fee payment

Payment date: 20140618

Year of fee payment: 8

FPAY Annual fee payment

Payment date: 20150617

Year of fee payment: 9

FPAY Annual fee payment

Payment date: 20160620

Year of fee payment: 10

FPAY Annual fee payment

Payment date: 20170626

Year of fee payment: 11

FPAY Annual fee payment

Payment date: 20180618

Year of fee payment: 12

FPAY Annual fee payment

Payment date: 20190619

Year of fee payment: 13