KR100866110B1 - Method for forming copper line in semiconductor device - Google Patents
Method for forming copper line in semiconductor device Download PDFInfo
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- KR100866110B1 KR100866110B1 KR1020020032352A KR20020032352A KR100866110B1 KR 100866110 B1 KR100866110 B1 KR 100866110B1 KR 1020020032352 A KR1020020032352 A KR 1020020032352A KR 20020032352 A KR20020032352 A KR 20020032352A KR 100866110 B1 KR100866110 B1 KR 100866110B1
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- copper
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- electroplating
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 82
- 239000010949 copper Substances 0.000 title claims abstract description 79
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 77
- 238000000034 method Methods 0.000 title claims abstract description 49
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000009713 electroplating Methods 0.000 claims abstract description 30
- 239000001257 hydrogen Substances 0.000 claims abstract description 18
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 18
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- 238000005498 polishing Methods 0.000 claims abstract description 6
- 239000000126 substance Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000007747 plating Methods 0.000 claims description 17
- 239000000654 additive Substances 0.000 claims description 13
- 230000000996 additive effect Effects 0.000 claims description 10
- 239000012190 activator Substances 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000003112 inhibitor Substances 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 14
- 230000007547 defect Effects 0.000 abstract description 13
- 230000008021 deposition Effects 0.000 abstract description 10
- 230000008569 process Effects 0.000 abstract description 8
- 238000005137 deposition process Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 150000002431 hydrogen Chemical class 0.000 description 4
- 230000005012 migration Effects 0.000 description 4
- 238000013508 migration Methods 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000010948 rhodium Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- RVSGESPTHDDNTH-UHFFFAOYSA-N alumane;tantalum Chemical compound [AlH3].[Ta] RVSGESPTHDDNTH-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000008151 electrolyte solution Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- 229910052701 rubidium Inorganic materials 0.000 description 1
- IGLNJRXAVVLDKE-UHFFFAOYSA-N rubidium atom Chemical compound [Rb] IGLNJRXAVVLDKE-UHFFFAOYSA-N 0.000 description 1
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 구리의 전기도금 증착시 발생하는 고유의 결함을 감소시킬 수 있는 반도체 소자의 구리배선 형성방법에 관한 것으로, 반도체 기판 위의 소정의 패턴상에 배리어층과 씨드(Sed)층을 형성하는 단계; 상기 씨드층 상에 전기도금법으로 제1구리층을 형성하는 단계; 상기 제1구리층상에 수소 분위기에서 제2구리층을 형성하는 단계; 상기 제1 및 제2구리층내로 수소가 확산되도록 열처리하는 단계; 및 상기 제1 및 제2구리층을 화학 기계적 연마로 평탄화시켜 구리배선을 형성하는 단계를 포함하며, 패턴을 매립하는 단계까지만 전기도금 증착법을 진행함으로써 구리 전기 도금 증착공정이 단순화되고, 구리원자의 확산을 촉진시키는 수소의 성질을 이용함으로써 일부 평탄화를 이룰 수 있어 구리 CMP 공정에서 필요로 하는 구리막의 두께를 감소시킬 수 있으며, 또한 전기도금 증착시 발생하는 결함이 감소됨으로 소자의 전기적 특성과 배선 신뢰성이 향상되고 제조수율이 향상되는 효과가 있는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device capable of reducing inherent defects generated during electroplating deposition of copper. The present invention provides a method for forming a barrier layer and a seed layer on a predetermined pattern on a semiconductor substrate. step; Forming a first copper layer on the seed layer by electroplating; Forming a second copper layer on the first copper layer in a hydrogen atmosphere; Heat-treating the diffusion of hydrogen into the first and second copper layers; And planarizing the first and second copper layers by chemical mechanical polishing to form copper wiring, and by performing the electroplating deposition method only until the step of embedding the pattern, the copper electroplating deposition process is simplified, Partial planarization can be achieved by utilizing the properties of hydrogen that promotes diffusion, thereby reducing the thickness of the copper film required in the copper CMP process, and also reducing the defects generated during electroplating deposition, thereby reducing the electrical characteristics and wiring reliability of the device. This has the effect of improving the production yield.
Description
도 1 내지 도 5는 본 발명에 따른 반도체 소자의 구리배선 형성방법을 도시한 공정별 단면도.1 to 5 are cross-sectional views for each process illustrating a method of forming copper wirings of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100; 반도체 기판 110; 패턴100; A
120; 씨드층 130; 배리어층120;
140; 제1구리층 150; 제2구리층140;
155; 수소 ` 160a; 구리배선155; Hydrogen `160a; Copper wiring
본 발명은 반도체 소자의 구리배선 형성방법에 관한 것으로, 보다 상세하게는 구리의 전기도금 증착시 발생하는 고유의 결함을 감소시킬 수 있는 반도체 소자의 구리배선 형성방법에 관한 것이다.The present invention relates to a method for forming a copper wiring of a semiconductor device, and more particularly to a method for forming a copper wiring of a semiconductor device that can reduce the inherent defects generated during electroplating of copper.
종래 반도체 소자를 제조하는 데 있어서는 텅스텐과 알루미늄 합금을 금속배선으로 사용하는 것이 일반적이다. 그러나, 최근 반도체 소자의 고집적화 경향에 따라 선폭의 미세화에 의해서 소자의 동작 때문에 금속배선내의 전류밀도가 높아지고, 이에 따라 일렉트로 마이그레이션(electro migration) 현상이 두드러졌다. In manufacturing a conventional semiconductor device, it is common to use tungsten and an aluminum alloy as metal wiring. However, in recent years, with the tendency of high integration of semiconductor devices, the current density in the metal wiring is increased due to the operation of the devices due to the miniaturization of the line width, and thus, the electro migration phenomenon has been remarkable.
또한, 금속배선과 이를 보호하기 위한 절연막의 열팽창계수가 달라서 금속배선에 인장력이 가해져서 생기는 크리프(creep) 파괴인 스트레스 마이그레이션(stress migration) 현상이 배선의 미세화로 인해 더욱 두드려졌다.In addition, stress migration, a creep failure caused by the application of a tensile force to the metal wiring due to different thermal expansion coefficients of the metal wiring and the insulating film for protecting the same, has been further exacerbated by the miniaturization of the wiring.
이에 따라, 기존의 금속배선으로 사용되는 텅스텐과 알루미늄 합금은 큰 비저항과 일렉트로 마이그레이션(electro migration)이나 스트레스 마이그레이션(stress migration)으로 인해 신뢰성이 저하되었다. 따라서, 텅스텐과 알루미늄 합금을 대신하여 비저항이 작고 신뢰성이 우수한 구리가 금속배선 재료로 등장하게 되었다. 특히, 구리합금은 순수한 구리에 비해 비저항이 상대적으로 다소 크지만 배선의 신뢰성과 내식성이 우수하여 반도체 소자의 금속배선으로 이용된다.As a result, the tungsten and aluminum alloys used in the existing metal wirings are degraded due to large resistivity, electro migration, or stress migration. Therefore, copper having a low specific resistance and excellent reliability has emerged as a metal wiring material in place of tungsten and aluminum alloys. In particular, although copper alloy has a relatively large specific resistance compared to pure copper, it is used as a metal wiring of a semiconductor device because of excellent wiring reliability and corrosion resistance.
종래 기술에 따른 반도체 소자의 구리배선 형성방법으로는 전기도금 증착법을 이용하였다. 전기도금 증착법은 우수한 매립 능력과 높은 처리량(Throughput) 등의 장점이 있는 구리배선의 대표적인 형성방법이다.As a method of forming a copper wiring of a semiconductor device according to the prior art, an electroplating deposition method was used. Electroplating deposition is a typical method for forming copper interconnects that has the advantages of excellent embedding capability and high throughput.
그러나, 종래 기술에 따른 반도체 소자의 구리배선 형성방법에 있어서는 다음과 같은 문제점이 있었다.However, the copper wiring forming method of the semiconductor device according to the prior art has the following problems.
종래 기술에 있어서 선행공정인 배리어(Barrier)/씨드(Seed) 증착공정과 전기도금 증착공정시 구리 씨드(Seed)의 웨팅(Wetting)에 따라 공동(Void)이나 피트(Pit) 등의 결함(Defect)을 유발할 수 있었다. 이러한 결함은 전기도금 증착법 고유의 결함으로서 반도체 소자의 전기적 특성과 배선의 신뢰성을 악화시키고 생산 수율(Yield)을 떨어뜨리는 주요 인자로 기능한다.Defects such as voids and pits due to wetting of copper seeds during the barrier / seed deposition process and the electroplating deposition process, which are the prior art processes. ) Could be caused. These defects are inherent in the electroplating deposition method, and serve as a major factor for deteriorating the electrical characteristics and wiring reliability of semiconductor devices and lowering the production yield.
이에, 본 발명은 상기한 종래 기술상의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 구리 원자간의 결합에너지를 감소시키고 구리 원자의 확산을 촉진시키는 수소의 성질을 이용하여 전기도금 증착시 발생하는 결함을 감소시킬 수 있는 반도체 소자의 구리배선 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-mentioned problems in the prior art, an object of the present invention is generated during electroplating deposition using the property of hydrogen to reduce the binding energy between copper atoms and promote the diffusion of copper atoms. The present invention provides a method for forming a copper wiring of a semiconductor device capable of reducing defects.
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 구리배선 형성방법은, 반도체 기판 위의 소정의 패턴상에 배리어층과 씨드(See)층을 형성하는 단계; 상기 씨드층 상에 전기도금법으로 제1구리층을 형성하는 단계; 상기 제1구리층상에 수소 분위기에서 제2구리층을 형성하는 단계; 상기 제1 및 제2구리층내로 수소가 확산되도록 열처리하는 단계; 및 상기 제1 및 제2구리층을 화학 기계적 연마로 평탄화시켜 구리배선을 형성하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method for forming a copper wiring of a semiconductor device, the method including: forming a barrier layer and a seed layer on a predetermined pattern on a semiconductor substrate; Forming a first copper layer on the seed layer by electroplating; Forming a second copper layer on the first copper layer in a hydrogen atmosphere; Heat-treating the diffusion of hydrogen into the first and second copper layers; And planarizing the first and second copper layers by chemical mechanical polishing to form a copper wiring.
본 발명에 의하면 전기도금 증착시 발생하는 결함이 수소에 의해 확산이 촉진된 구리가 매립되어 결함이 줄어들게 된다.According to the present invention, the defects generated during electroplating deposition are embedded in copper, which is promoted by hydrogen, to reduce defects.
(실시예)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. (Example)
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 5는 본 발명에 따른 반도체 소자의 구리배선 형성방법을 설명하기 위한 공정별 단면도이다.1 to 5 are cross-sectional views for each process for explaining a method of forming copper wirings of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 구리배선 형성방법은, 도 1에 도시된 바와 같이, 먼저 반도체 기판(100)위에 형성된 다마신 패턴(damascene pattern)과 같은 소정의 패턴(110)상에 배리어층(120;barrier layer)과 씨드층(130;seed layer)을 형성한다.In the method for forming a copper wiring of a semiconductor device according to the present invention, as shown in FIG. 1, a
상기 배리어층(120)은 상기 소정의 패턴(110) 물질인 절연막과 후속공정으로 형성될 구리배선과의 접착력을 향상시키는 동시에 구리 원자의 외부 확산을 방지하는 역할을 한다. 상기 배리어층(120)으로는 탄탈륨(Ta), 탄탈륨질화물(TaN), 탄탈륨알루미늄질화물(TaAlN), 탄탈륨실리콘질화물(TaSiN), 탄탈륨실리사이드(TaSix), 티타늄(Ti), 티타늄질화물(TiN), 티타늄실리콘질화물(TiSiN), 텅스텐질화물(WN), 코발트(Co), 코발트실리사이드(CoSix) 및 이들의 조합 중에서 어느 하나를 스퍼터링이나 화학기상증착법(CVD) 등으로 증착하여 약 100Å~1,000Å 두께로 형성한다.The
상기 씨드층(130)은 상기 배리어층(120) 전면에 구리 도금(Cu plating)을 위한 것으로, 구리(Cu)를 이용하거나 백금(Pt), 팔라듐(Pd), 루비듐(Rb), 스트론튬(Sr), 로듐(Rh) 및 코발트(Co) 등의 전이금속 중에서 어느 하나를 스퍼터링이나 화학기상증착법(CVD) 등으로 증착하여 약 250Å~2,500Å 정도의 두께로 형성한다.The
그다음, 도 2에 도시된 바와 같이, 상기 씨드층(130)상에 전기도금법(electroplating)으로 제1구리층(140)을 형성한다. 구체적으로, 상기 소정의 패턴(110)의 미세한 패턴 부분(110b)은 상기 제1구리층(140)에 의해 완전히 매립되게 하고, 상기 소정의 패턴(110)의 조대한 패턴 부분(110a)은 상기 제1구리 층(140)에 의해 부분 매립될 정도로 진행한다.Next, as shown in FIG. 2, the
상기 제1구리층(140)을 형성하기 위한 전기도금법은 구리 이온이 포함된 전해용액내로 상기 씨드층(130)이 형성된 기판(100)을 넣은 후 이를 음극(cathode)으로 하여 전압을 인가하여 상기 씨드층(130) 상에만 선택적으로 구리층이 형성되는 것을 이용한 것이다.In the electroplating method for forming the
전기도금법에 있어서, 3-성분(component) 첨가제 즉, 미세한 패턴에서의 매립을 활성화시키는 활성제(accelerator)와 미세한 패턴이 아닌 영역에서의 증착을 억제하는 억제제(suppressor) 및 과도층착을 억제하는 레벨러(leveler)를 첨가제로 하여 직류도금(DC plating)법으로 진행할 수 있고, 또는 2-성분(component) 첨가제 즉, 활성제(accelerator)와 억제제(suppressor)만을 첨가제로 하고 과도증착을 억제하기 위하여 역펄스 도금(reverse pulse plating)법으로 진행할 수 있다.In the electroplating method, a three-component additive, that is, an activator that activates embedding in a fine pattern, an inhibitor that suppresses deposition in a region that is not a fine pattern, and a leveler that suppresses overlamination ( It can be proceeded by DC plating method with the leveler as an additive or reverse pulse plating in order to suppress the over-deposition by using only the two-component additive, that is, the activator and the suppressor as the additive. It can be done by reverse pulse plating.
그러나, 이 단계에서는 2-성분(component) 첨가제와 직류 도금(DC plating)만으로도 진행이 가능하며 또한 이러한 공정이 바람직하다. 그 이유는 다음과 같다.At this stage, however, only two-component additives and DC plating can proceed, and such a process is preferred. The reason for this is as follows.
미세한 패턴을 매립하는 전기도금에 있어서, 상기한 바와 같이 3-성분 첨가제와 직류도금(DC Plating)을 이용할 경우에는 상대적으로 공정관리가 복잡하며, 2-성분 첨가제와 역펄스 도금(reverse pulse plating)을 이용할 경우에는 결함이 발생하기도 한다.In the electroplating in which fine patterns are embedded, process control is relatively complicated when using 3-component additives and DC plating as described above, and 2-component additives and reverse pulse plating In the case of using a defect may occur.
따라서, 미세한 패턴의 매립이 끝난후 후속 스퍼터링으로 구리층을 증착하면 활성제(accelerator) 성분에 의한 과도증착을 방지할 수 있고 전기도금 증착만으로 미세한 패턴 매립 공정까지만 진행하면 되므로, 2-성분 첨가제와 직류 도금(DC plating)법에 의한 전기도금법이 바람직하다.Therefore, if the copper layer is deposited by the subsequent sputtering after the fine pattern is finished, the overdeposition by the activator component can be prevented and only the fine pattern embedding process can be performed only by electroplating deposition. The electroplating method by DC plating method is preferable.
이어서, 도 3에 도시된 바와 같이, 상기 제1구리층(140)상에 수소 분위기에서 스퍼터링 방법으로 제2구리층(150)을 형성한다. 상기 스퍼터링 방법은 아르곤(Ar)이나 수소(H2)를 이용한 Ar/H2 가스 분위기 또는 N2/H2
가스 분위기에서 진행하는데, 상기 수소(H2) 가스의 함량이 최대 50%가 되도록 가스 공급(Gas Flow)을 조절한다.Next, as shown in FIG. 3, the
그다음, 도 4에 도시된 바와 같이, 상기 제1구리층(140) 및 제2구리층(150) 내로 수소(155)가 확산되도록 열처리를 한다. 상기 열처리는 노(Furnace)를 이용하여 100℃~500℃ 온도에서 진행하거나 또는 급속 열처리(Rapid Thermal Anneling)를 이용하여 100℃~500℃ 온도에서 진행한다.Next, as shown in FIG. 4, heat treatment is performed such that
수소는 구리 원자간의 결합 에너지를 감소시키고 구리 원자의 확산을 촉진시키는 역할을 한다. 따라서, 전기도금 증착시 발생한 피트(Pit)와 보이드(Void)는 수소에 의해서 확산이 촉진된 구리가 매립되어 제거된다. 그결과, 상기 제1구리층(140)과 제2구리층(150)은 수소(155)에 의해서 확산이 촉진된 구리로써 피트와 보이드 등의 결함이 제거된 구리층(160)으로 형성된다.Hydrogen serves to reduce the binding energy between copper atoms and to promote the diffusion of copper atoms. Therefore, the pits and voids generated during the electroplating deposition are removed by embedding copper, which is promoted to be diffused by hydrogen. As a result, the
이어서, 도 5에 도시된 바와 같이, 상기 제1구리층(140)과 제2구리층(150)으로 구성된 결함이 없는 구리층(160)을 화학 기계적 연마(CMP)로 평탄화시켜 구리배선(160a)을 형성한다. 이때, 화학기계적 연마에 의해 상기 씨드층(120)도 일부 제 거된 형태(120a)로 된다. Subsequently, as shown in FIG. 5, the defect-
전단계의 전기도금 증착시 발생한 결함이 감소함에 따라 화학기계적 연마를 진행한 후의 구리배선(160a)의 경우도 결함이 감소하게 된다.As defects generated during the previous electroplating deposition are reduced, the defects in the
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 구리배선 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the copper wiring forming method of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는, 패턴을 매립하는 단계까지만 전기도금 증착법을 진행함으로써 구리 전기 도금 증착공정이 단순화되고, 구리원자의 확산을 촉진시키는 수소의 성질을 이용함으로써 일부 평탄화를 이룰 수 있어 구리 CMP 공정에서 필요로 하는 구리막의 두께를 감소시킬 수 있는 효과가 있다.In the present invention, the electroplating deposition process is carried out only until the step of embedding the pattern, and the copper electroplating deposition process is simplified, and some planarization can be achieved by utilizing the property of hydrogen to promote the diffusion of copper atoms, which is necessary for the copper CMP process. There is an effect of reducing the thickness of the copper film.
또한, 전기도금 증착시 발생하는 결함이 감소됨으로 소자의 전기적 특성과 배선 신뢰성이 향상되고, 제조수율이 향상되는 효과가 있다.In addition, the defects occurring during the electroplating deposition is reduced, thereby improving the electrical characteristics and wiring reliability of the device, and the manufacturing yield is improved.
Claims (10)
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| KR20030049582A (en) * | 2001-12-15 | 2003-06-25 | 주식회사 하이닉스반도체 | method for forming copper line |
| KR20030050062A (en) * | 2001-12-18 | 2003-06-25 | 주식회사 하이닉스반도체 | METHOD FOR FORMING Cu WIRING OF SENICONDUCTOR DEVICE |
| KR20040007863A (en) * | 2002-07-11 | 2004-01-28 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
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| KR20030049582A (en) * | 2001-12-15 | 2003-06-25 | 주식회사 하이닉스반도체 | method for forming copper line |
| KR20030050062A (en) * | 2001-12-18 | 2003-06-25 | 주식회사 하이닉스반도체 | METHOD FOR FORMING Cu WIRING OF SENICONDUCTOR DEVICE |
| KR20040007863A (en) * | 2002-07-11 | 2004-01-28 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
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