TW201405643A - Semiconductor reflow processing for feature fill - Google Patents

Abstract

A method for at least partially filling a feature on a workpiece generally includes obtaining a workpiece including a feature depositing a first conformal conductive layer in the feature, and thermally treating the workpiece to reflow the first conformal conductive layer in the feature.

Description

Semiconductor reflow processing for feature filling

The present disclosure relates to electrochemical deposition of conductive materials (eg, metals, such as metals, such as in trenches and vias, particularly trenches and vias in damascene applications). A method of copper (Cu), cobalt (Co), nickel (Ni), gold (Au), silver (Ag), manganese (Mn), tin (Sn), aluminum (Al), and alloys of the above.

The integrated circuit is an interconnected body of elements formed within the semiconductor material and the dielectric material covering the surface of the semiconductor material. Elements that can be formed within the semiconductor include MOS transistors, bipolar transistors, diodes, and diffusion resistors. Elements that can be formed within the dielectric include thin film resistors and capacitors. The components are interconnected by conductor paths formed within the dielectric. Typically, more than two conductor paths having a continuous layer separated by a dielectric layer serve as interconnects. In current practice, copper oxide and cerium oxide are commonly used for conductors and dielectrics, respectively.

Deposits in copper interconnects typically include a dielectric layer, a barrier layer, a seed layer, a copper fill, and a copper cap. Because copper readily diffuses into the dielectric material, the barrier layer serves to separate the copper deposit from the dielectric material. However, it should be understood that a barrier layer may not be required for other metal interconnects, except that a barrier layer may not be required for copper removal. Barrier usually It is composed of a refractory metal or a refractory compound, for example, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or the like. Other suitable barrier materials can include manganese (Mn) and manganese nitride (MnN). The barrier layer is typically formed using a deposition technique known as physical vapor deposition (PVD), but barrier layers can also be formed by using other deposition techniques, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

A seed layer can be deposited on the barrier layer. However, it should also be understood that direct direct on barrier (DOB) deposition is also within the scope of the present disclosure, which is deposited directly on the barrier layer (DOB), for example by alloying or co-depositing. a barrier formed of a metal and deposited on other barrier layers well known and/or used by those skilled in the art, the interconnect metal may be deposited on the barrier layer composed of an alloy or a co-deposited metal without the need for separate The seed layer is made of a metal such as TiRu, TaRu, or WRu.

In one non-limiting example, the seed layer can be a copper seed layer. As another non-limiting example, the seed layer may be a copper alloy seed layer, such as a copper manganese alloy, a copper cobalt alloy, or a copper nickel alloy. In the case where copper is deposited in the features, there are several exemplary options for the seed layer. First, the seed layer can be a PVD copper seed layer. See, for example, Figure 3 for illustrating a process including PVD copper seed deposition. The seed layer can also be formed by using other deposition techniques such as CVD or ALD.

Second, the seed layer can be a stacked film, such as a liner layer and a PVD seed layer. The liner layer is a material used to relieve discontinuous seed crystal problems between the barrier layer and the PVD seed crystal and to improve PVD seed crystal adhesion. The liner is usually a precious metal, for example Such as ruthenium (Ru), platinum (Pt), palladium (Pd) and osmium (Os), but the series may also include cobalt (Co) and nickel (Ni). Currently, CVD Ru and CVD Co are common liners; however, the liner layer can also be formed by using other deposition techniques (eg, ALD or PVD).

Third, the seed layer can be a secondary seed layer. The secondary seed layer is similar to the liner layer because the secondary seed layer is typically formed of noble metals such as Ru, Pt, Pd, and Os, but the series may also include Co and Ni and the most common CVD Ru and CVD. Co. (Like the seed layer and the liner layer, the secondary seed layer can also be formed by using other deposition techniques such as ALD or PVD). The difference is that the secondary seed layer is used as a seed layer, and the liner layer is an intermediate layer between the barrier layer and the PVD seed crystal. See, for example, Figures 5 and 6 for illustrating a process including secondary seed deposition, which is followed by ECD seed deposition in Figure 5, as described below, and flashing in Figure 6 Flash deposition. ("Flash" deposition is mainly at the top and bottom of the feature, without significant deposition on the sidewalls of the feature).

After the seed layer has been deposited according to one of the above examples, the features may include a seed layer enhancement (SLE) layer that is thin of a deposited metal (eg, copper having a thickness of about 2 nm). Floor. The SLE layer is also referred to as an electrochemical deposition seed crystal (or ECD seed crystal). See, for example, Figure 4 for illustrating a process including PVD seed deposition and ECD seed deposition. See, for example, Figure 5 for illustrating a process including secondary seed deposition and ECD seed deposition. As seen in Figures 4 and 5, the ECD seed crystal can be a conformally deposited layer.

Commonly used copper diamine (EDA) complexes including very low concentrations Basic chemistry deposits ECD copper seed crystals. ECD copper seed crystals may also be deposited using other copper complexes (eg, copper citrate, copper tartrate, and urea copper, etc.) and may range from about 2 to about 11, from about 3 to about 10, or at about 4 ECD copper seed crystals are deposited to a pH range of about 10.

After the seed layer has been deposited according to one of the above examples (the seed layer may also include an optional ECD seed crystal), for example, conventional ECD fill and overlay may be performed in the features using an acidic deposition chemistry. Conventional ECD copper acidic chemicals may include, for example, copper sulfate, sulfuric acid, methanesulfonic acid, hydrochloric acid, and organic additives (eg, accelerators, suppressors, and levelers). Electrochemical deposition of copper has been found to be the most economical way to deposit a copper metallization layer. In addition to being economically viable, ECD deposition techniques provide substantially bottom-up (eg, non-conformal) metal fill that is mechanically and electrically suitable for interconnect structures.

Conventional ECD fills, especially ECD fills in small features, can result in lower quality interconnects. For example, conventional ECD copper fill can create voids, especially in features that are less than 30 nm in size. As an example of a type of void formed using conventional ECD deposition, the opening of the feature can be pinch off. Other types of voids may also result from the use of conventional ECD copper fill processes in small features. This void and other inherent properties of deposits formed using conventional ECD copper fill can increase the electrical resistance of the interconnect, thereby reducing the electrical performance of the component and degrading the reliability of the copper interconnect.

Therefore, a need exists for an improved, substantially void-free metal fill process for features. This substantially void-free metal fill can be used in small features, for example, features having an opening size of less than 30 nm.

The Summary is provided to introduce a selection of concepts in a simplified form, which is further described in the Detailed Description. This Summary is not intended to identify key features of the claimed subject matter, and is not intended to be used as an adjunct to the scope of the claimed subject matter.

In accordance with an embodiment of the present disclosure, a method for at least partially filling features on a workpiece is provided. The method generally includes the steps of: obtaining a workpiece comprising features; depositing a first conformal conductive layer in the feature; and thermally treating the workpiece to reflow the first conformal conductive layer in the feature.

In accordance with another embodiment of the present disclosure, a method for at least partially filling features on a workpiece is provided. The method generally includes the steps of: obtaining a workpiece comprising features; depositing a barrier layer in the feature; and depositing a first conductive layer in the feature after the barrier layer, wherein the first conductive layer is a seed layer. The method further includes the step of depositing a second conductive layer in the feature after the first conductive layer, wherein the second conductive layer is a conformal conductive layer; and annealing the workpiece to reflow the second conductive layer in the feature.

According to another embodiment of the present disclosure, a workpiece is provided. The workpiece typically includes a substantially void-free conductive layer of at least one feature and feature having a dimension of less than 30 nm.

102~110‧‧‧Steps

112‧‧‧Workpiece

114‧‧‧Block

115‧‧‧ seed layer

116‧‧‧ECD seed material

118‧‧‧Filling

120‧‧‧Materials

122‧‧‧Characteristics

The foregoing aspects and many attendant advantages of the present disclosure will be more readily understood from the following detailed description of the <RTIgt; Schematic flow chart; 2 is a comparison of exemplary process steps that may be used in connection with prior art processes with processes in accordance with embodiments of the present disclosure; FIG. 3 is a schematic depiction of process steps and exemplary feature development processes using the prior art main damascene process Flowchart, including barrier deposition, seed deposition, and conventional ECD fill and overlay deposition; Figure 4 is a schematic depiction of process steps and exemplary feature development processes using prior art SLE (also known as ECD seed crystal) process Flowchart, including barrier deposition, seed deposition, ECD seed deposition, and conventional ECD fill and overlay deposition; Figure 5 is a schematic depiction of process steps and exemplary feature development processes using prior art ECD seed crystal processes Flowchart, including barrier deposition, secondary seed deposition, ECD seed deposition, and conventional ECD fill and overlay deposition; Figure 6 is a depiction of prior art deposition of a secondary seeding process with a flash layer A schematic flow chart of steps and exemplary feature development processes, including barrier deposition, secondary seed deposition, flash deposition, and conventional ECD fill and overlay deposition; A schematic flow diagram of process steps and exemplary feature development processes for several exemplary embodiments of the present disclosure; FIG. 8 is a chart of exemplary process steps for depositing in a damascene feature for various exemplary wafers in accordance with embodiments of the present disclosure. Depicted, the damascene feature has a feature diameter of about 30 nm; Figure 9 is a graphical depiction of a 120 micron long line resistor resistance result obtained from the exemplary wafer depicted in Figure 8; Figure 10 is from Figure 8. 1 meter long obtained in the exemplary wafer described in Graph depiction of line resistor resistance results; FIG. 11 is a graphical depiction of a 1 meter long resistor RC delay result obtained from the exemplary wafer depicted in FIG. 8; and FIG. 12 includes for use in accordance with an embodiment of the present disclosure A transmission electron microscopy (TEM) image of the substantially void-free gap fill of the damascene feature having a feature diameter of about 30 nm.

Embodiments of the present disclosure relate to a workpiece (eg, a semiconductor wafer), an element or processing element for processing a workpiece, and a method of processing the workpiece. The term workpiece, wafer or semiconductor wafer means any flat medium or article, including semiconductor wafers and other substrates or wafers, glass, masks and optical or memory media, MEMS substrates or any other microelectronic, micromechanical or microelectromechanical The workpiece of the component.

The processes described herein will be used for metal deposition or metal alloy deposition in workpiece features, including trenches and vias. In one embodiment of the present disclosure, the process can be used in small features, such as features having a feature diameter of less than 30 nm. However, it should be understood that the processes described herein are applicable to any feature size. The size discussed in this application is the post-etch feature size at the top opening of the feature. The processes described herein can be applied to various forms of copper, cobalt, nickel, gold, silver, manganese, tin, aluminum, and alloy deposition, for example, in damascene applications. In embodiments of the present disclosure, the damascene features may be selected from a group of features having a size of less than 30 nm, from about 5 nm to less than 30 nm, from about 10 nm to less than 30 nm, from about 15 nm to about 20 nm, from about 20 nm to less than 30 nm. Less than 20 nm, less than 10 nm, and about 5 nm to about 10 nm.

It should be understood that the descriptive terms "micro-feature workpiece" and "workpiece" as used herein include all structures and layers that have been previously deposited and formed at a given point during processing, and are not limited to those depicted in FIG. Structure and layer.

It should be understood that the processes described herein can also be modified for metal or metal alloy deposition in high aspect ratio features, such as vias in through-via via (TSV) features.

Although generally described herein as metal deposition, it should be understood that the term "metal" also contemplates metal alloys. The metal and metal alloy can be used to form a seed layer or for fully or partially filling features. Exemplary copper alloys can include, but are not limited to, copper manganese and copper aluminum. As a non-limiting example, the alloy may be distributed in a range of from about 0.5% to about 6% of the secondary alloy metal as compared to the primary alloying metal (e.g., Cu, Co, Ni, Ag, Au, etc.).

As noted above, conventional fabrication of metal interconnects can include depositing a barrier layer on the dielectric material to prevent diffusion of the metal into the dielectric material. Suitable barrier layers can include, for example, Ta, Ti, TiN, TaN, Mn or MnN. Suitable barrier deposition methods can include PVD, ALD, and CVD; however, PVD is the most common process for barrier deposition. The barrier layer is typically used to separate the copper or copper alloy from the dielectric material; however, it should be understood that in the case of other metal interconnects, diffusion may not be an issue and a barrier layer may not be needed.

The barrier layer deposition may be followed by an optional seed layer deposition. In the case where metal is deposited in the features, there are several options for the seed layer. As described above, the seed layer may be (1) a seed layer (as a non-limiting example, a PVD copper seed layer). The seed layer may be a metal layer such as copper, cobalt, nickel, gold, silver, Manganese, tin, aluminum, niobium and alloys of the above. The seed layer may also be a stacked film of (2) a liner layer and a seed layer (as a non-limiting example, a CVD Ru liner layer and a PVD copper seed layer), or (3) a secondary seed layer (as A non-limiting example is a CVD or ALD Ru secondary seed layer). However, it should be understood that the present disclosure also contemplates other methods of depositing the exemplary seed layer.

As discussed above, the liner layer is a material used to mitigate discontinuous seeding problems between the barrier layer and the seed layer and to improve the adhesion of the seed layer. The liner is typically a precious metal such as Ru, Pt, Pd and Os, but the series may also include Co and Ni. Currently, CVD Ru and CVD Co are common liners; however, the liner layer can also be formed by using other deposition techniques (eg, PVD or ALD). For damascene applications, the thickness of the liner layer can range from about 5 Å to 50 Å.

As also discussed above, the secondary seed layer is similar to the liner layer because the secondary seed layer is typically formed of noble metals (eg, Ru, Pt, Pd, and Os), but the series may also include Co and Ni and most Common CVD Ru and CVD Co. The difference is that the secondary seed layer is used as a seed layer, and the liner layer is an intermediate layer between the barrier layer and the seed layer. The secondary seed layer can also be formed by using other deposition techniques such as PVD or ALD.

It can be between about 100 ° C and about 500 ° C in a forming gas (for example, 3%-5% hydrogen in nitrogen or 3%-5% hydrogen in helium). The liner or secondary seed deposit is heat treated or annealed at temperature to remove any surface oxide, densify the secondary seed layer or liner layer, and improve the surface properties of the deposit. The liner or secondary seed deposit may be additionally passivated by immersion in gaseous nitrogen (N ₂ gas) or other passivation environment to prevent surface oxidation. The passivation of the liner or secondary seed crystal is described in U.S. Patent No. 8,357,599 issued Jan. 22, 2013.

In a non-limiting example of a deposited seed layer (eg, PVD copper seed crystal, PVD copper seed crystal including CVD Ru liner or CVD Ru secondary seed crystal or another deposited metal or metal alloy, layer combination or deposition technique) After a non-limiting example, the feature can include a conformal metal layer behind the seed layer. However, it should also be understood that the conformal metal layer can be deposited directly on the barrier layer, i.e., without the seed layer.

In one embodiment of the present disclosure, the conformal layer is deposited using an ECD seeding process and then modified using a process known as ECD seed crystal "additional" deposition (or ECD seeding "addition") including a heat treatment step. The conformal layer. In other embodiments of the present disclosure, the conformal layer can be deposited using CVD, ALD, or other deposition techniques, and then the conformal layer can be subjected to a heat treatment step. In accordance with embodiments of the present disclosure, the conformal layer is "flowable" or movable when subjected to heat treatment or annealing.

In this embodiment, the "addition" of the ECD seed crystal generally refers to the ECD metal seed deposition plus a heat treatment step (eg, an annealing step). In one embodiment of the present disclosure, the heat treatment step can result in a heavy flow of some or all of the seed deposition. The increase in temperature in the ECD seed layer contributes to the mobility of atoms in the layer and enhances the ability of the atom to fill the structure.

In contrast to conventional ECD metal fills (using acidic chemicals), ECD seed crystal "additional" deposition is similar to ECD seed crystal deposition (using alkaline chemicals), but with the addition of a heat treatment step. Furthermore, instead of depositing only the seed layer, an ECD seed crystal "addition" can be performed to partially fill or completely fill the features. Substantial void-free filling of small features can be achieved by the ECD seed crystal "additional" process, as described in more detail below (see the substantial absence of voids in the small features in Figure 12). Filled image).

The chemicals used in the ECD chamber for "additional" deposition of ECD seed crystals may include alkaline chemicals, for example, Cu (ethylenediamine) 2 at a pH in the range of from about 8 to about 11, in In one embodiment of the present disclosure the pH is from about 8 to about 10, and in one embodiment of the present disclosure the pH is about 9.3. However, it should be understood that acidic chemicals using suitable organic additives can also be used to achieve conformal ECD seed deposition.

After the ECD seed crystal deposition, the workpiece can then be subjected to a spin, rinse and dry (SRD) process or other cleaning process. The ECD seed crystal is then heated at a temperature sufficiently warm to allow the seed crystal to reflow, but the temperature is not overheated such that the components on the workpiece or workpiece are damaged or degraded. For example, the temperature can range from about 100 °C to about 500 °C for the seeding heavy flow in the feature. A suitable heat treatment temperature or annealing temperature is in the range of from about 100 ° C to about 500 ° C, and can be maintained at a temperature ranging from about 200 ° C to about 400 ° C and maintained at a temperature of from about 250 ° C to about 350 ° C. The equipment within the range achieves such appropriate heat treatment temperatures or annealing temperatures.

The heat treatment process or the annealing process may be performed using a synthesis gas or an inert gas, pure hydrogen gas, or a reducing gas (for example, ammonia gas (NH ₃ )). During reflow, the deposition shape changes such that metal deposits can pool at the bottom of the feature, as shown in FIG. In addition to the heavy flow during the heat treatment process, the metal deposits can also produce larger grains and reduce the sheet resistivity. An inert gas can be used to cool the heated workpiece.

After the ECD seed crystal "additional" deposition and heat treatment process has been completed to partially fill or completely fill the features, conventional acid chemicals can be used to complete A deposition process for gap filling and overlay deposition. The acidic chemical metal deposition step is typically used to fill large structures and to maintain the proper film thickness required for subsequent polishing steps because the acidic chemical metal deposition step is typically a faster process than the ECD seeding process, saving time and reducing Processing costs.

As seen in Figures 1 and 7, the ECD seed deposition and reflow steps can be repeated to ensure completion of the ECD seed fill feature. In that regard, the processes described herein can include one or more ECD seed deposition, cleaning (eg, SDR), and heat treatment loops.

Referring to Figure 1, a reflow process 100 and exemplary features produced by the reflow process are depicted. The workpiece 112 may be a dielectric material on a crystalline tantalum workpiece containing at least one feature 122 in an exemplary embodiment. In an exemplary step 102, feature 122 is lined with barrier layer 114 and seed layer 115. In the exemplary step 104, feature 122 of workpiece 112 has received a layer of ECD seed material 116 on seed layer 115. In an exemplary annealing step 106, the workpiece is annealed at an appropriate temperature to induce the exemplary reflow step 108 to promote partial or complete filling. During the annealing step, the ECD seed material 116 flows into the features 122 to form the filler 118, while the adverse effects of the workpiece 112 or features included in the workpiece 112 are minimized. In an exemplary embodiment, the ECD seed deposition step 104, the annealing step 106, and the reflow step 108 may be repeated to obtain the desired characteristics of the fill 118. The number of iterations can depend on the structure. Once the filler 118 reaches the desired size, an exemplary overlaying step 110 can be used to complete the process of depositing additional material 120 over the features to prepare for additional workpiece 112 processing.

Referring now to Figure 2, an example of a process flow is provided, wherein the disclosure is The application can be combined with other workpiece surface deposition processes and incorporated into other workpiece surface deposition processes. The previously developed process will be described first. First, the TSV process includes deposition of barrier layers, seed layers, and conventional ECD fills. Second, the ECD seed crystal (also known as SLE) process includes deposition of barrier layers, seed layers, ECD seed layers, and conventional ECD fills. Third, the ECD seeding (SLE) process associated with the liner includes deposition of a barrier layer, a liner layer, a seed layer, an ECD seed layer, and a conventional ECD fill. Fourth, the ECD seed crystal (SLE) process with secondary seeding includes deposition of a barrier layer, a secondary seed layer, an ECD seed layer, and a conventional ECD fill. Fifth, the ECD seeding (SLE) process with secondary seed crystals and flashes includes deposition of barrier layers, secondary seed layers, flash layers, ECD seed layers, and conventional ECD fills. Sixth, the ECD seed crystal (DOB) process includes deposition of barrier layers, ECD seed layers, and conventional ECD fills. The ECD seed crystal (DOB) process is a DOB process because no secondary seed, pad or seed layer is deposited; instead, the ECD seed layer is deposited directly on the plateable barrier.

Still referring to FIG. 2, a process in accordance with an embodiment of the present disclosure will now be described. Seventh, the ECD seed crystal addition (DOB) process includes barrier layers, ECD seed crystal "additional" deposits, and conventional ECD fill and/or overlay deposition. As in the sixth example above, the ECD seed addition (DOB) process is also a DOB process because no secondary seed, pad or seed layer is deposited; instead, the ECD seed layer is deposited directly on the electroplatable barrier layer. on. Eighth, the ECD seed crystal addition process includes a barrier layer, a secondary seed layer, an ECD seed crystal "additional" deposit, and a conventional ECD fill and/or overlay deposition. Ninth, the ECD seed crystal addition process without ECD includes deposition of barrier layers, secondary seed layers, and ECD seed crystal "additional" deposits. Tenth, ECD seed crystal addition processes without secondary seeding include barrier layers, seed layers, ECD seed crystal "additional" deposits, and conventional ECD fill and/or overlay deposition. Eleventh, ECD seeding additional processes associated with liners and seed crystals include barrier layers, liner layers, seed layers, ECD seed crystal "additional" deposits, and conventional ECD fill and/or overlay deposition.

Referring to Figure 7, another exemplary process in accordance with an embodiment of the present disclosure is provided. In the first step, the workpiece having the barrier layer and the secondary seed layer is heat treated or annealed prior to the ECD seeding step to remove any surface oxide, densify the deposit, and improve the surface properties of the deposit. The seed layer shown in FIG. 7 is a secondary seed layer, but it should be understood that the second seed layer may also be a seed layer or a stacked film of a liner layer and a seed layer. Suitable heat treatment conditions or annealing conditions may include the possibility of a temperature between about 200 ° C and about 400 ° C in the synthesis gas or pure hydrogen for about one (1) minute to about ten (10) minutes. As described above, the workpiece can be alternatively heat treated in an inert gas such as N ₂ , argon (Ar) or helium (He). A reducing gas such as ammonia (NH ₃ ) can also be used.

In a second step, the workpiece is transferred to a deposition chamber for conformal deposition of the ECD seed layer. The thickness of the deposited film varies depending on the desired properties and feature sizes of the metal deposit.

In the third step, the workpiece is rotated, the workpiece is rinsed with deionized (DI) water and the workpiece is dried (SRD) to clean the workpiece.

In the fourth step, the workpiece is heat treated or annealed at a temperature in the range of 200 ° C to 400 ° C to reflow the metal into the features.

In a fifth step, the workpiece can undergo sequential reprocessing of steps 2, 3 and 4 until a desired fill profile of the features on the workpiece is obtained.

In a sixth step, the workpiece is subjected to conventional ECD acidic chemical deposition to achieve the desired thickness. The workpiece is then prepared for subsequent processing, which may include additional heat treatment, chemical mechanical polishing, and other processes.

Alternative embodiments of the process may include variations of the steps already described herein, and such steps, combinations, and permutations may additionally be incorporated into the following additional steps. It is contemplated in the present disclosure that, for example, from about 4 to about 10, from about 3 to about 10, or from about 2 to about 11, with or without an organic additive (eg, an inhibitor, accelerator, and/or leveling agent) Conformal "seed" deposition is performed in an alkaline or acidic solution in the pH range. The reflow may be performed using a plurality of deposition steps, a cleaning (eg, SRD) step, and a heat treatment step or an annealing step, or may be performed in a single step followed by heat treatment or annealing at a suitable temperature.

The "additional" deposition of ECD seed crystals is important for the development of small features because the heat treatment step or the annealing step and the reflow step provide substantial void-free seed deposition. As described in more detail below, the void formation in the feature increases the electrical resistance (reducing the electrical performance of the component) and degrades the reliability of the interconnect.

Other advantages are realized by using the processes described herein. In this regard, a single tool (e.g., the Applied Materials, Inc. Raider ^® manufactured by electrochemical deposition, cleaning (e.g. SRD), and heat treatment or annealing tools) can be used to seed deposition step ECD (or more on repeated ECD seed deposition step), cleaning step (or multiple cleaning steps at the time of repetition), heat treatment step (or multiple heat treatment steps at the time of repetition) and used in the final ECD step. Furthermore, the results show that the substantially void-free gap fill of the small features using the process described herein results in lower resistance and RC delay values. Moreover, the processes described herein provide the ability to fill small features on the order of less than about 30 nm, although filling may not be achieved using conventional techniques. It is also advantageous for the ECD seed crystal to be "added" to a feature greater than 30 nm.

As described above, one or more layers of ECD seed crystals can be applied and then one or more layers of the ECD seed crystal are exposed to elevated temperatures to fill deeper features or high aspect ratio features. Referring to Figure 8, two exemplary ECD seed crystal addition processes (including annealing steps) (wafer 4 and wafer 5) are provided, with two conventional ECD seed crystals for deposition in a damascene feature having a feature diameter of about 30 nm. Process (no annealing step) [wafer 1 and wafer 7] compared. Referring to Figures 9 through 11, the results show that the incremental deposition of ECD seed crystals in the inlaid features results in resistance and resistance (RC) compared to the single step of ECD seeding (i.e., no annealing step). The retardation value is reduced, with some or all of the deposition step followed by an annealing step.

All wafer 1, wafer 4, wafer 5, and wafer 7 include the following initial processing conditions: depositing a 10 Å ALD TaN barrier layer, followed by deposition of a 30 Å CVD Ru seed layer (secondary seed), and then subjecting the workpiece to 300 ° C Annealed with 10 minutes of nitrogen passivation.

Wafer 1 and wafer 7 were then plated through a single step of ECD copper seeding at 2.1 amp-min and 0.5 amp-min, respectively, and wafer 1 and wafer 7 were then filled and covered using a conventional acidic ECD copper deposition process. The resultant workpiece produced thick ECD copper seed crystals (wafer 1) and thin ECD copper seed crystals (wafer 7).

The wafer 4 and wafer 5 are subjected to ECD seed crystal "additional" conditions. Wafer 4 includes three ECD copper seeding steps, each step at 0.7 amp-min, wherein each of the first two steps is followed by 300 ° C annealing and in the third step There is no annealing after the step, followed by filling and covering using a conventional acidic ECD copper deposition process. A microscopic image associated with wafer 4 having a feature size approaching 30 nm is provided in FIG. Although there is no annealing after the third step, it should be understood that the final annealing step is also within the scope of the present disclosure.

Wafer 5 includes four ECD copper seeding steps, each step at 0.5 amp-min, wherein each of the first three steps has an annealing of 300 ° C and no annealing after the fourth step, followed by conventional The acid ECD copper deposition process completes the filling and coverage. Like wafer 4, it should be understood that the final annealing step is also within the scope of the present disclosure.

Referring now to Figures 9 through 11, comparative resistance and RC delay data for wafer 1, wafer 4, wafer 5, and wafer 7 are provided. As can be seen in Figures 9 through 11, the workpieces formed using the ECD seed crystal "additional" (wafer 4 and wafer 5) according to the method described herein are compared to the workpieces formed using previously developed techniques (wafer 1 and wafer 7). ) has significantly reduced resistance and resistive/capacitive (RC) delay.

Referring to Figures 9 and 10, the workpiece formed in accordance with embodiments of the present disclosure achieves a reduction in resistance within the following ranges compared to a workpiece formed using ECD seed crystals without an ECD seed crystal additional annealing loop: 0 to about 40 %, greater than 0 to about 30%, greater than 0 to about 20%, from about 10% to about 20%, and from about 10% to about 15%.

Referring to Figure 11, the workpiece formed in accordance with embodiments of the present disclosure achieves a reduction in RC retardation value as compared to a workpiece formed using ECD seed crystals without an ECD seed crystal additional annealing loop. Lower RC delays can result in lower or no damage to the low K intermetal dielectric in the feature.

Although the illustrative embodiments have been illustrated and described, it will be understood that various modifications may be made herein without departing from the spirit and scope of the disclosure Variety.

102~110‧‧‧Steps

112‧‧‧Workpiece

114‧‧‧Block

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116‧‧‧ECD seed material

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122‧‧‧Characteristics

Claims (20)

A method for at least partially filling a feature on a workpiece, the method comprising the steps of: (a) obtaining a workpiece comprising a feature; (b) depositing a first conformal conductive layer in the feature; (c) heat treating the workpiece to cause the first conformal conductive layer to reflow in the feature. The method of claim 1, wherein the step of heat treating the workpiece reduces voids in the feature fill. The method of claim 1, the method further comprising the step of depositing a barrier layer in the feature prior to depositing the first conformal conductive layer. According to the method of claim 1, the method further comprises the step of depositing a conductive seed layer in the feature prior to depositing the first conformal conductive layer. The method of claim 4, wherein the metal for the seed layer is selected from the group consisting of copper, cobalt, nickel, gold, silver, manganese, tin, aluminum, antimony, and the like. alloy. The method of claim 1, wherein the first conformal conductive layer is used The metal is selected from the group consisting of copper, cobalt, nickel, gold, silver, manganese, tin, aluminum, and alloys of the above metals. The method of claim 1, wherein the first conformal conductive layer is electrochemically deposited by chemical vapor deposition or by atomic layer deposition. According to the method of claim 1, the method further comprises the steps of: depositing a second conformal conductive layer after the first conformal conductive layer, and heat treating the workpiece to reflow the second conformal conductive layer. According to the method of claim 8, the method further comprises the steps of: depositing a third conformal conductive layer after the second conformal conductive layer, and heat treating the workpiece to reflow the third conformal conductive layer. The method of claim 4, wherein the seed layer is selected from the group consisting of seed crystals, secondary seed crystals, and a stacked film of seed crystals and liners. The method of claim 1, wherein the first conformal conductive layer of the reflow partially or completely fills the feature. The method of claim 1, wherein the first conformal conductive layer is deposited using a chemical comprising at least one copper complex selected from the group consisting of copper ethylene diamine, copper citrate, and tartaric acid. A group of copper and urea copper. The method of claim 1, the method further comprising the step of depositing a cap layer on the first conformal conductive layer of the reflow. The method of claim 13 wherein the cover layer is deposited in an acidic chemical. The method of claim 1, wherein the heat treatment temperature is selected from the group consisting of temperatures in the range of from about 100 ° C to about 500 ° C, in the range of from about 200 ° C to about 400 ° C, and It is in the range of about 250 ° C to about 350 ° C. The method of claim 1, wherein the characteristic diameter is selected from the group consisting of less than 30 nm, about 5 nm to less than 30 nm, about 10 nm to less than 30 nm, about 15 nm to about 20 nm, and about 20 nm to less than 30 nm, less than 20 nm, less than 10 nm, and about A group consisting of 5 nm to about 10 nm. The method of claim 1, wherein the heat-treated workpiece has a resistance value decrease selected from the group consisting of: from more than 0 to about 40%, compared to a workpiece formed by the step of not heat-treating the workpiece, More than 0 to about 30%, greater than 0 to about 20%, from about 10% to about 20%, and from about 10% to about 15%. The method of claim 3, wherein the first conformal conductive layer is deposited directly on the barrier layer. A method for at least partially filling a feature on a workpiece, the method comprising the steps of: (a) obtaining a workpiece comprising a feature; (b) depositing a barrier layer in the feature; (c) Depositing a first conductive layer in the feature, wherein the first conductive layer is a crystalline layer; (d) depositing a second conductive layer in the feature after the first conductive layer, wherein The second conductive layer is a conformal conductive layer; and (e) annealing the workpiece to cause the second conductive layer to reflow in the feature. A workpiece comprising: (a) at least one feature having a dimension of less than 30 nm; and (b) a substantially void-free conductive layer disposed in the feature .