JP4733804B2 - Wiring formation method - Google Patents

Wiring formation method Download PDF

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JP4733804B2
JP4733804B2 JP2000041807A JP2000041807A JP4733804B2 JP 4733804 B2 JP4733804 B2 JP 4733804B2 JP 2000041807 A JP2000041807 A JP 2000041807A JP 2000041807 A JP2000041807 A JP 2000041807A JP 4733804 B2 JP4733804 B2 JP 4733804B2
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forming
wiring
layer
film
intermediate layer
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JP2001230219A (en
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信幸 大塚
紀嘉 清水
久弥 酒井
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Fujitsu Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain highly reliable wiring which can cope with further scale down and a higher degree of integration by making desired fine wiring formable, by sufficiently securing not on the surface covering property of a plated Cu film, but also the adhesion between the Cu film and a base film, and a semiconductor device provided with the wiring. SOLUTION: At the time of forming fine multilayered Cu wiring by using both the dual damascene method and electroplating method, a base layer 14 composed of a material containing a metal having a high melting point, an intermediate layer 15 composed of Zr or a Zr compound, and a Cu seed layer 16 are formed by the CVD method so as to cover the internal wall surfaces of wiring grooves 12 and via holes 13 before the groove 12 and holes 13 are filled up with plated Cu. The Zr compound used for forming the intermediate film 15 is Zr N(C2H5)2}4.

Description

【０００１】
【発明の属する技術分野】
本発明は、いわゆるダマシン法により絶縁膜の微細な溝内に配線を充填形成してなる配線の形成方法及び半導体装置に関し、特に当該配線を下層配線とビア孔を通じて接続するように形成するデュアルダマシン法に適用して好適である。
【０００２】
【従来の技術】
従来より、低抵抗で高いエレクトロマイグレーション（ＥＭ）耐性を有するＣｕ配線は、近時におけるＬＳＩの高集積化及び微細化の要請に応え得る高信頼性材料として期待されている。
【０００３】
その一方で、Ｃｕは微細加工が困難な配線材料であり、例えば通常の金属配線のようにフォトリソグラフィーでは微細加工に限界がある。
【０００４】
そこで、Ｃｕ配線の微細加工に有効な手法の一つとして、下層配線上を覆う下地絶縁膜にビア・溝加工を施し、当該ビア孔及び溝内をＣｕで充填することによりビア孔で接続された多層配線の形成を行うデュアルダマシン法が注目され始めている。そして、このデュアルダマシン法を用いてＣｕの埋め込みを行う実用化に最も適切な手法として、電解メッキ法が検討されている。
【０００５】
【発明が解決しようとする課題】
電解メッキ法を用いてＣｕ配線形成を行う場合、メッキ下地膜としてＣｕシード層が必要であり、現在のところＣｕシード層はスパッタ法により成膜されている。ところが、デュアルダマシン法に電解メッキ法を併用して微細配線（例えば、アスペクト比が３以上）を形成する場合、微細且つ複雑な形状の溝及びビア孔の内壁面をきれいに覆うようにスパッタ法でＣｕシード層を形成することは極めて困難である。
【０００６】
そこで、スパッタ法に替わり、高アスペクト比構造の前記内壁面にＣｕシード層をきれいに形成する有効な手法として、化学気相成長法（ＣＶＤ法）の適用が検討されている。
【０００７】
Ｃｕシード層は、その膜質として前述のように下地構造に対する表面被覆性に加え、下地膜との密着性に優れていることが要求される。ＣＶＤ法を用いてＣｕシード層を形成する際には、表面被覆性については十分な効果が得られるが、下地膜との密着性が弱くなるという問題がある。Ｃｕシード層が密着性に劣るものであれば、その後のＣｕメッキ膜を形成した状態では更なる密着性の劣化を生じ、続く化学機械研磨（ＣＭＰ）の工程でＣｕメッキ膜の剥離が発生してしまうため、実際のプロセスとして使用に耐え得るものとは言えない。
【０００８】
このように、デュアルダマシン法に電解メッキ法を併用して微細なＣｕ配線を形成する場合、Ｃｕメッキ膜の表面被覆性の向上についてはＣＶＤ法の導入により解決されるものの、密着性の低下による悪影響は甚大であり、これを克服する好適な手法が模索されている現況にある。
【０００９】
本発明は、前記課題に鑑みてなされたものであり、ダマシン法に電解メッキ法を併用して微細なＣｕ配線を形成するに際して、Ｃｕメッキ膜の表面被覆性のみならず下地膜との密着性を十分に確保して所望の微細配線の形成を可能とし、更なる微細化・高集積化に対応した信頼性の高い配線の形成方法及び当該配線を備えた半導体装置を提供することを目的とする。
【００１０】
【課題を解決するための手段】
本発明者らは、鋭意検討の結果、以下に示す発明の諸態様に想到するに至った。
【００１１】
第１の態様は、ダマシン法に電解メッキ法を併用して微細なＣｕ配線を形成する配線の形成方法である。具体的には、基板の上層に形成された絶縁膜に少なくとも配線溝を形成する工程と、前記配線溝の内壁面を覆うように、少なくとも高融点金属を含有する材料からなる下地層を化学気相成長法により形成する工程と、Ｚｒ又はＺｒ化合物からなる中間層を化学気相成長法により形成する工程と、電解メッキ用のシード層を化学気相成長法により形成する工程と、前記配線溝を埋め込むように電解メッキ法により銅又は銅を含む金属層を形成する工程と、前記銅又は銅を含む金属層を研磨して、前記配線溝内を充填するように前記銅又は銅を含む金属層を残して配線を形成する工程とを有し、前記中間層を形成した後に、前記中間層に対してアニール処理及び還元処理を施す。
【００１２】
ここで、前記中間層を形成する際に用いる化学気相成長による成膜原料を、常温で気体又は液体であり、前記中間層の適切な成長温度が３５０℃〜４５０℃であり、前記成長温度以下の取り扱い所定温度範囲で高蒸気圧を有するものとすることが好適である。
【００１３】
この場合、前記下地層を形成する前記工程と、前記中間層を形成する前記工程とを同一の成膜室内で連続的に実行することが好適である。
【００１４】
また、前記下地層を形成する際に用いる化学気相成長による成膜原料における前記高融点金属と化学結合した付加物と、前記中間層を形成する際に用いる化学気相成長による成膜原料におけるＺｒと化学結合した付加物とを同一のものとすることが好適である。
【００１５】
また、前記下地層を形成する前記工程と、前記中間層を形成する前記工程とを、真空を介して接続したそれぞれ独立の成膜室内で実行してもよい。
【００１６】
この場合、前記中間層を形成する際に用いる化学気相成長による成膜原料を、常温で気体又は液体であり、前記中間層の適切な成長温度が１００℃〜４５０℃であり、前記成長温度以下の取り扱い所定温度範囲で高蒸気圧を有するものとすることが好適である。
【００１７】
また前記第１の態様は、ダマシン法を用いる場合に比べて、更に複雑且つ微細な成膜を要するデュアルダマシン法に適用して好適である。即ち、前記基板の上層に下部配線が形成されており、前記下部配線と接続孔を通じて電気的に接続されるように前記配線を形成するに際して、前記下地膜を前記配線溝及び前記接続孔の内壁面を覆うように形成した後、前記中間層及び前記シード層を形成し、前記配線溝及び前記接続孔を埋め込むように前記銅又は銅を含む金属層を形成する。
【００２０】
【作用】
微細且つ高アスペクト比の複雑な形状の部位に優れた表面被覆性をもって成膜を行うには、化学気相成長法（ＣＶＤ法）が最も有効な手段である。そこで本発明においては、ダマシン法に電解メッキ法を併用して高アスペクト比の微細なＣｕ配線を形成するに際して、高融点金属を含有する下地膜及び電解メッキ用のシード層をＣＶＤ法により成膜することに加え、下地膜とシード層との間にＺｒ又はＺｒ化合物からなる中間層をＣＶＤ法により成膜する。この中間層の存在により、シード層が優れた表面被覆性をもって密着性良く形成され、これに依存して電解メッキによる銅又は銅を含む金属層が密着性良く微細な配線溝（及び接続孔）内を充填し、所望の微細配線が実現する。
【００２１】
【発明の実施の形態】
以下、本発明を適用した具体的な実施形態について図面を参照しながら詳細に説明する。
【００２２】
（本実施形態による多層配線の形成）
本実施形態では、いわゆるデュアルダマシン法に電解メッキ法を併用して高アスペクト比の微細なＣｕ又はＣｕを含む金属多層配線、ここでは多層Ｃｕ配線を形成する好適な方法を開示する。
図１〜図３は、本実施形態による多層Ｃｕ配線（ここでは２層）の形成方法を工程順に示す概略断面図である。
【００２３】
先ず、図１（ａ）に示すように、所定の半導体素子が形成された半導体基板（不図示）を覆うようにＳｉＯ2を材料として層間絶縁膜２を膜厚５００ｎｍ程度に堆積形成した後、膜厚３０ｎｍ程度の薄いＳｉＮ膜３を形成し、フォトリソグラフィー及びそれに続くドライエッチングによりＳｉＮ膜３及び層間絶縁膜２を加工し、幅３００ｎｍ程度、深さ５３０ｎｍ程度の配線溝４をパターン形成する。
【００２４】
続いて、配線溝４の内壁面を含むＳｉＮ膜３上に、高融点金属を含む材料、ここではＴｉＮ又はＴａＮよりなる下地層（バリアメタル層）５をＣＶＤ法により膜厚１０ｎｍ程度に成膜し、次いでメッキ用のＣｕシード層１をＣＶＤ法により膜厚５０ｎｍ程度に成膜した後、電解メッキ法により配線溝４を埋め込むようにＳｉＮ膜３上にＣｕ層６を堆積形成する。
【００２５】
そして、ＳｉＮ膜３をストッパーとして、Ｃｕ層６に化学機械研磨（ＣＭＰ）を施し、配線溝４を充填する下部Ｃｕ配線７を形成する。
【００２６】
続いて、図１（ｂ）に示すように、下部Ｃｕ配線７上を含むＳｉＮ膜３上にＳｉＯ2を材料として層間絶縁膜８を膜厚７００ｎｍ程度に堆積形成した後、膜厚３０ｎｍ程度の薄いＳｉＮ膜９を形成し、フォトリソグラフィー及びそれに続くドライエッチングによりＳｉＮ膜９を加工して、下部Ｃｕ配線７の直上に孔部１０をパターン形成する。
【００２７】
続いて、図１（ｃ）に示すように、孔部１０上を含むＳｉＮ膜９上にＳｉＯ2を材料として層間絶縁膜１１を膜厚５００ｎｍ程度に堆積形成し、フォトリソグラフィー及びそれに続くドライエッチングにより層間絶縁膜８，１１を加工する。このとき、層間絶縁膜１１上のレジストマスク形状に倣って層間絶縁膜１１に配線溝１２がパターン形成されるとともに、当該配線溝１２の底部に存するＳｉＮ膜９がマスクとなって孔部１０の形状に倣ったパターンが層間絶縁膜８に形成され、下部Ｃｕ配線７の表面の一部を露出させるビア孔１３が形成される。
【００２８】
続いて、図２（ａ）に示すように、配線溝１２及びビア孔１３の内壁面を含む層間絶縁膜１１上に、高融点金属を含む材料、ここではＴｉＮ又はＴａＮよりなる下地層（バリアメタル層）１４をＣＶＤ法により膜厚１０ｎｍ程度に成膜する。
【００２９】
続いて、図２（ｂ）に示すように、バリアメタル層１４を覆うように、Ｚｒ又はＺｒ化合物、ここではＺｒからなる中間層１５をＣＶＤ法により膜厚５ｎｍ程度に成膜する。なお後述するように、中間層１５の形成前後に半導体基板にアニール処理を施すことが好適である。当該アニール処理の後、Ｈ2（Ｈ2＋Ｎ2）ガスを用いたプラズマ処理及びＨｈｆａｃ処理を行うことが好ましい。
【００３０】
更に後述するように、バリアメタル層１４の形成工程と中間層１５の形成工程は各々のＣＶＤ成膜原料を適宜選択することにより、同一成膜室内で同一成膜温度により連続的に行うことが可能となる。
【００３１】
続いて、図２（ｃ）に示すように、中間層１５を覆うように、Ｃｕメッキ用のＣｕシード層１６をＣＶＤ法により膜厚５０ｎｍ程度に成膜する。なお後述するように、Ｃｕシード層１６の形成後に、再びアニール処理を施すことが好適である。
【００３２】
続いて、図３（ａ）に示すように、電解メッキ法により配線溝１２及びビア孔１３を埋め込むようにＣｕシード層１６上にＣｕ層１７を堆積形成する。
【００３３】
そして、図３（ｂ）に示すように、Ｃｕ層１７に化学機械研磨（ＣＭＰ）を施し、配線溝１２及びビア孔１３を充填する上部Ｃｕ配線１８を形成する。
以上の工程により、下部Ｃｕ配線７と上部Ｃｕ配線１８とがビア孔１３を通じて電気的に接続されてなる微細な多層配線が完成する。
【００３４】
なおここでは、上部Ｃｕ配線１８の形成のみに中間層１５を用いた例を開示したが、もちろん下部Ｃｕ配線７に適用してもよい。実際、多層配線の更なる微細化を図る際には、ビア孔１３をもたない下部Ｃｕ配線７にも中間層１５を適用することが好適である。
【００３５】
（本実施形態による主要構成の機能）
上述した多層配線の形成方法において、本実施形態の主要構成は、配線溝１２及びビア孔１３が一体となった微細で複雑な部位をＣｕで充填してなる上部Ｃｕ配線１８を形成する際に、バリアメタル層１４及びＣｕシード層１６をＣＶＤ法により成膜することに加え、バリアメタル層１４とＣｕシード層１６との間にＺｒ又はＺｒ化合物からなる中間層１５をＣＶＤ法により成膜することにある。
【００３６】
ここで、中間層１５を成膜するにあたり、ＣＶＤ用の成膜原料の適切な選択が重要である。具体的には、他の構成部材に与える影響、当該成膜原料の取り扱いの容易性、形成工程の簡略性、他の構成部材、特にバリアメタル層１４との関連性等を総合的に考察して選択する必要がある。
【００３７】
先ず、他の構成部材に与える影響を緩和する要請から、特にＣＶＤ法による成膜温度が問題となる。高い成膜温度が必要な成膜原料を用いた場合、特に下層に形成された配線や半導体素子に悪影響を及ぼすおそれがある。従って、成膜温度が比較的低い（好ましくは４５０℃以下）成膜原料であることが要求される。
【００３８】
次に、取り扱いの容易性の要請から、成膜原料は常温で気体又は液体であることが要求される。もちろん、気体であることが理想的ではあるが、前記成膜温度の制限要請から、現実的には液体の成膜原料が使用候補として挙げられる。更に当該成膜原料は、成膜温度以下の取り扱い所定温度範囲で十分な蒸気圧を有するものであることが必要である。
【００３９】
上記の各要件を満たすことがＣＶＤ法により中間層１５の成膜を行ううえで必須となるが、更にこれらに加えて、バリアメタル層１４との関連性から、形成工程の簡略化を図ることが要請される。具体的には、バリアメタル層１４を形成する工程と、中間層１５を形成する工程とを同一の成膜室内で連続的に実行することが好ましい。これを実現する好適な一例として、バリアメタル層１４のＣＶＤ成膜原料における高融点金属と化学結合する付加物と、中間層１５のＣＶＤ成膜原料におけるＺｒと化学結合する付加物とを同一となるように成膜原料を選択することが考えられる。
【００４０】
本発明者らは、以上の考察から、中間層１５のＣＶＤ成膜原料として、Ｚｒ｛Ｎ（Ｃ2Ｈ5）2｝4（テトラジエチルアミノジルコニウム）等のアミノジルコニウムが最も好適な化合物の一つであることを見出した。以下、前記各要件との関連で、Ｚｒ｛Ｎ（Ｃ2Ｈ5）2｝4を例に採り中間層１５のＣＶＤ成膜原料としての有用性について説明する。
【００４１】
即ち、Ｚｒ｛Ｎ（Ｃ2Ｈ5）2｝4は常温で液体であり、成膜温度が２００℃程度と比較的低く、当該成膜温度以下の取り扱い所定温度範囲で十分な蒸気圧を有する。
【００４２】
具体的に、Ｚｒ｛Ｎ（Ｃ2Ｈ5）2｝4の熱物性評価を行った。
先ず、図４の円内に示すような圧力測定器を用いて、Ｚｒ｛Ｎ（Ｃ2Ｈ5）2｝4の加熱時における圧力測定を行ったところ、図４の特性曲線に示されるように、１００℃付近から圧力上昇の割合に変化が生じており、この付近から熱分解が生じていることがわかる。この１００℃以下における領域での圧力変化から蒸気圧曲線を求めた結果、飽和蒸気圧Ｐ（Ｔｏｒｒ）は、温度をＴ（Ｋ）として、
ｌｏｇＰ＝−１７５６／Ｔ＋４．７２７ （３１３＜Ｔ＜３５３） …（１）
であることが判明した。これは、ＣＶＤ成膜原料として申し分ない値である。
【００４３】
更に、２００℃付近からは圧力上昇の割合が急激に変化していることがわかった。残留ガスのＦＩ−ＩＲ測定の結果、
１００℃付近からの変化は、Ｒを所定の炭価水素として、
Ｚｒ｛Ｎ（Ｃ2Ｈ5）2｝4→Ｚｒ＋２ＨＮ（Ｃ2Ｈ5）2＋Ｎ2＋２ＲＨ …（２）
２００℃付近からの変化は、Ｒを所定の炭価水素として、
２ＨＮ（Ｃ2Ｈ5）2→Ｎ2＋２ＲＨ …（３）
となるものと予測される。
【００４４】
以上の結果から、Ｚｒ｛Ｎ（Ｃ2Ｈ5）2｝4をＣＶＤ成膜原料として用いる場合、１００℃程度、好ましくは２００℃程度の比較的低温の成膜温度から成膜可能であり、しかも十分な飽和蒸気圧を有するために取り扱いが容易であって、所望の正確な成膜は可能であることがわかった。
【００４５】
更に、Ｚｒ｛Ｎ（Ｃ2Ｈ5）2｝4は、バリアメタル膜１４のＣＶＤ成膜原料として用いられるＴｉ｛Ｎ（Ｃ2Ｈ5）2｝4（テトラジエチルアミノチタニウム）と付加物に相当する部分、即ち｛Ｎ（Ｃ2Ｈ5）2｝が同一であるため、副反応生成物が発生するおそれがなく、従ってバリアメタル層１４を形成する工程と、中間層１５を形成する工程とを同一の成膜室内で連続的に実行することが可能となる。
【００４６】
ここで、Ｔｉ｛Ｎ（Ｃ2Ｈ5）2｝4の飽和蒸気圧Ｐ（Ｔｏｒｒ）は、温度をＴ（Ｋ）として、
ｌｏｇＰ＝−３０３８／Ｔ＋７．９０６ …（４）
であり、上述したＺｒ｛Ｎ（Ｃ2Ｈ5）2｝4の飽和蒸気圧と大差なく、しかもＺｒ｛Ｎ（Ｃ2Ｈ5）2｝4とＴｉ｛Ｎ（Ｃ2Ｈ5）2｝4とでは分解温度が近接していることから、同一温度での連続成長が可能である。当該成膜温度としては、バリアメタル層１４の方が高温を要するためにこれに律され、３５０℃〜４５０℃となる。従ってこの場合、ＣＶＤ成膜原料を切り替えるだけでバリアメタル層１４及び中間層１５の連続的成膜が可能であり、工程数の大幅な削減化及び簡略化が実現する。もちろん、バリアメタル層１４及び中間層１５を別の成膜室内で形成する場合には、中間層１５の成膜温度はバリアメタル層１４とは独立に１００℃〜４５０℃の範囲内で設定することができる。
【００４７】
以上説明したように、Ｚｒ｛Ｎ（Ｃ2Ｈ5）2｝4が中間層１５のＣＶＤ成膜原料として最適であることがわかった。そして、これにより中間層１５を形成することにより、ダマシン法に電解メッキ法を併用して高アスペクト比の微細なＣｕ配線を優れた表面被覆性をもって密着性良く形成することが可能となる。
【００４８】
更に、中間層１５及びＣｕシード層１６の各形成工程の前後でアニール処理を行うことにより、更なる密着性の向上が実現することが確認された。これは、当該アニール処理により、バリアメタル層１４については膜中に残留した不純物の除去、中間層１５については膜中に残留した不純物の除去、結晶性の向上及び脱Ｎ、Ｃｕシード層１６については膜中に残留した不純物の除去の各効果を奏するためである。
【００４９】
また、Ｚｒ｛Ｎ（Ｃ2Ｈ5）2｝4は窒素（Ｎ）を含有するため、成膜されたＺｒからなる中間層１５は窒化物になり易い傾向がある。ＺｒＮの抵抗率は１３．６μΩｃｍであり、Ｚｒの抵抗率である４０．０μΩｃｍより低いが、４価の窒化物であるＺｒ3Ｎ4は高抵抗物質であるため、ビア孔１３の部位に使用するには若干問題である。そこで中間層１５の高抵抗化を防止するため、中間層１５の成膜後に還元処理、特にＨ2（Ｈ2＋Ｎ2）ガスを用いたプラズマ処理やＨｈｆａｃ処理を行うことが有効である。また、バリアメタル層の材料として、Ｔａ，Ｔｉ等の窒化物を作り易い高融点金属を使用することにより、Ｚｒの窒化を抑制し、高抵抗化を防止するようにしても好適である。
【００５０】
（実験例）
以下、上述した本実施形態による主要構成の諸効果を調べた各実験について説明する。
ここでは、中間層１５のＣＶＤ成膜原料としてＺｒ｛Ｎ（Ｃ2Ｈ5）2｝4を用い、図５に示すように、反応室Ａと反応室Ｂが搬送室を介して併設されてなるＣＶＤ成膜チャンバーを用いて中間層１５及びＣｕシード層１６をそれぞれ成膜した。
【００５１】
−実験１−
バリアメタル層１４としてＰＶＤ法により膜厚２０ｎｍ程度のＴａＮ膜を形成した下地基板を用いた。先ず、反応室Ａ内で中間層１５の成膜を行い、続いて反応室Ｂ内でＣｕシード層１６の成膜を行った。
【００５２】
このときの各成膜条件は、
中間層１５については、バブラー温度を５０℃で供給量を２００ｓｃｃｍ、キャリアガスをＨｅとして供給量を５００ｓｃｃｍ、基板温度を２５０℃、圧力を１ｋＰａとした。
Ｃｕシード層１６については、ＣｕのＣＶＤ成膜原料をＣｕ（ｈｆａｃ）ＴＭＶＳ−１．０ｇ／ｍｉｎ、キャリアガスをＨ2として供給量を５００ｓｃｃｍ、、基板温度を１８０℃、圧力を１ｋＰａとした。
【００５３】
成膜した中間層１５及びＣｕシード層１６の膜厚はそれぞれ１０ｎｍ程度、５０ｎｍ程度となった。
得られたＣｕシード層１６上にＣｕ層１７を膜厚１μｍ程度にメッキ成膜し、ＣＭＰを施した結果、膜剥離が発生していないことが確認された。
【００５４】
−実験２−
バリアメタル層１４としてＣＶＤ法により膜厚１０ｎｍ程度のＴｉＮ膜を形成した下地基板を用い、実験１と同様に中間層１５及びＣｕシード層１６の成膜を行った。ここでは、中間層１５の成膜前に、４００℃で１０分間のアニール処理を施した。
得られたＣｕシード層１６上にＣｕ層１７を膜厚１μｍ程度にメッキ成膜し、テープテストを行った結果、アニール処理を行わない場合に比して良好な密着性を示した。
【００５５】
−実験３−
実験１と同様に中間層１５及びＣｕシード層１６の成膜を行った。ここでは、中間層１５の成膜後に、Ｈ2を用い３００℃で１０分間のアニール処理を施した。
得られたＣｕシード層１６上にＣｕ層１７を膜厚１μｍ程度にメッキ成膜し、テープテストを行った結果、アニール処理を行わない場合に比して良好な密着性を示した。
【００５６】
−実験４−
実験１と同様に中間層１５及びＣｕシード層１６の成膜を行った。ここでは、Ｃｕシード層１６の成膜前にＨ2を用いたプラズマ処理を施した。
得られたＣｕシード層１６の抵抗測定を行った結果、その比抵抗が２．８μΩｃｍとなり、プラズマ処理を施さない場合の３．５μΩｃｍに比して減少することが確認された。
【００５７】
−実験５−
実験１と同様に中間層１５及びＣｕシード層１６の成膜を行った。ここでは、Ｃｕシード層１６の成膜前に供給量１０ｓｃｃｍ，１ｍｉｎ，１８０℃の条件でＨｈｆａｃ処理を施した。
得られたＣｕシード層１６の抵抗測定を行った結果、その比抵抗が２．９μΩｃｍとなり、Ｈｈｆａｃ処理を施さない場合の３．５μΩｃｍに比して減少することが確認された。
【００５８】
−実験６−
バリアメタル層１４としてＰＶＤ法によりＴａ膜を形成した下地基板を用い、実験１と同様に中間層１５及びＣｕシード層１６の成膜を行った。
得られたＣｕシード層１６の抵抗測定を行った結果、その比抵抗が２．７μΩｃｍと低値を示すことが確認された。
【００５９】
−実験７−
実験１と同様に中間層１５及びＣｕシード層１６の成膜を行った。ここでは、Ｃｕシード層１６の成膜後に、真空・３５０℃で１０分間のアニール処理を施した。
得られたＣｕシード層１６上にＣｕ層１７を膜厚１μｍ程度にメッキ成膜し、テープテストを行った結果、アニール処理を行わない場合に比して良好な密着性を示した。
【００６０】
−実験８−
先ず、Ｔｉ｛Ｎ（Ｃ2Ｈ5）2｝4をＣＶＤ成膜原料とし、３５０℃の成膜温度でＴｉＮからなるバリアメタル層１４を膜厚１０ｎｍ程度に成膜した後、同一成膜室内で連続して中間層１５を成膜した。
中間層１５の各成膜条件は、、バブラー温度を５０℃で供給量を１００ｓｃｃｍ、キャリアガスをＨｅとして供給量を５００ｓｃｃｍ、基板温度を３５０℃、圧力を０．５ｋＰａとした。
得られた膜厚５０ｎｍ程度Ｃｕシード層１６上にＣｕ層１７を膜厚１μｍ程度にメッキ成膜し、テープテストを行った結果、良好な密着性を示した。
【００６１】
−実験９−
バリアメタル層１４としてＣＶＤ法により膜厚１０ｎｍ程度のＴｉＮ膜を形成した下地基板を用い、中間層１５を（１）膜厚１０ｎｍ程度、（２）膜厚２０ｎｍ程度、（３）膜厚５０ｎｍ程度の３種類成膜した後、Ｃｕシード層１６を膜厚５０ｎｍ程度に成膜した。
得られたＣｕシード層１６上にＣｕ層１７を膜厚１μｍ程度にメッキ成膜し、テープテストを行った結果、密着強度は（１）＞（２）＞（３）となり、（１），（２）については良好な密着性を示すことを確認した。
【００６２】
前記各実験結果を含む各種条件に対するテープテストの結果を、まとめて以下の表１に示す。
【００６３】
【表１】

Figure 0004733804
【００６４】
以上説明したように、本実施形態によれば、ダマシン法に電解メッキ法を併用して高アスペクト比の微細なＣｕ配線を形成するに際して、高融点金属を含有するバリアメタル層１４及び電解メッキ用のＣｕシード層１６をＣＶＤ法により成膜することに加え、バリアメタル層１４とＣｕシード層１６との間にＺｒ又はＺｒ化合物からなる中間層１５をＣＶＤ法により成膜する。この中間層１５の存在により、Ｃｕシード層１６が優れた表面被覆性をもって密着性良く形成され、これに依存して電解メッキによるＣｕ層１７が密着性良く微細な配線溝（及び接続孔）内を充填し、所望の微細配線１８が実現する。
【００６５】
（多層配線を備えた半導体装置）
具体的に、半導体基板上に半導体素子を備え、前述の各工程により多層配線が形成されてなる半導体装置の一例を図６に示す。
【００６６】
この半導体装置は、半導体基板１０１上に形成されたＭＯＳトランジスタと、当該ＭＯＳトランジスタと接続された多層配線（ここでは２層）とを有して構成されている。
【００６７】
ＭＯＳトランジスタは、ゲート絶縁膜１０２を介して帯状のゲート電極１０３がパターン形成され、ゲート電極１０３の両側における半導体基板１の表層に不純物が導入されてソース／ドレイン１０４が形成されて構成されている。
【００６８】
更に、ＭＯＳトランジスタを覆う層間絶縁膜１０５が形成され、ソース／ドレイン１０４とコンタクト孔１０６を介して前述の下部Ｃｕ配線７が形成される。そして、下部Ｃｕ配線７とビア孔１３を介して接続されるように上部Ｃｕ配線１８が形成されて、半導体装置が構成される。ここで、下部Ｃｕ配線７及び上部Ｃｕ配線１８は、前述のようにデュアルダマシン法に電解メッキ法を併用して形成されたものであり、特に上部Ｃｕ配線１８は、配線溝１２及びビア孔１３の内壁面にバリアメタル層１４、Ｚｒ又はＺｒ化合物からなる中間層１５及びＣｕシード層１６がＣＶＤ法により順次成膜され、配線溝１２及びビア孔１３をＣｕメッキで充填するように形成されるものである。
【００６９】
この半導体装置は、優れた表面被覆性及び密着性を確保された微細な多層配線を有しており、近時における装置の微細化・高集積化の要請に十分応えることのできる信頼性の高いものである。
【００７０】
なお、本実施形態では、多層Ｃｕ配線を形成する場合を例示したが、本発明はこれに限定されず、Ｃｕを含む金属多層配線に適用可能である。具体的に当該金属としては、Ｃｕ−Ｓｎ、Ｃｕ−Ａｇ等が好適であり、これによりマイグレーション耐性を大幅に改善することができる。
【００７１】
以下に示す諸態様もまた、本発明を構成する。
【００７２】
態様１は、前記第１の態様に記載の配線の形成方法であり、前記下地層を形成する前記工程と、前記中間層を形成する前記工程とを同一の成膜室内で連続的に実行するに際して、前記両工程における成膜温度を３５０℃〜４５０℃の同一温度とすることを特徴とする。
【００７３】
態様２は、前記第１の態様に記載の配線の形成方法であり、前記下地層を形成する前記工程と、前記中間層を形成する前記工程とをそれぞれ独立の成膜室内で実行するに際して、前者の前記工程における成膜温度を３５０℃〜４５０℃とし、後者の前記工程における成膜温度を１００℃〜４５０℃とすることを特徴とする。
【００７４】
態様３は、前記第１の態様に記載の配線の形成方法であり、前記中間層を形成する際に用いる化学気相成長による前記成膜原料がアミノジルコニウムであることを特徴とする。
【００７５】
態様４は、前記第１の態様に記載の配線の形成方法であり、前記下地層を形成した後にアニール処理を施すことを特徴とする。
【００７６】
態様５は、前記第１の態様に記載の配線の形成方法であり、前記中間層を形成した後にアニール処理を施すことを特徴とする。
【００７７】
態様６は、前記第１の態様に記載の配線の形成方法であり、前記Ｃｕシード層を形成した後にアニール処理を施すことを特徴とする。
【００７８】
態様７は、前記第１の態様に記載の配線の形成方法であり、前記中間層を形成した後、前記Ｃｕシード層を形成する前に、前記中間層にプラズマ処理を施すことを特徴とする。
【００７９】
態様８は、前記第１の態様に記載の配線の形成方法であり、前記中間層を形成した後、前記Ｃｕシード層を形成する前に、前記中間層にＨｈｆａｃ処理を施すことを特徴とする。
【００８０】
態様９は、前記第１の態様に記載の配線の形成方法であり、前記中間層を膜厚１０ｎｍ以下に形成することを特徴とする。
【００８１】
態様１０は、前記第２の態様に記載の半導体装置であり、前記態様１〜９を適用することを特徴とする。
【００８２】
【発明の効果】
本発明によれば、ダマシン法に電解メッキ法を併用して微細なＣｕ配線を形成するに際して、Ｃｕメッキ膜の表面被覆性のみならず下地膜との密着性を十分に確保して所望の微細配線の形成を可能とし、更なる微細化・高集積化に対応した信頼性の高い配線の形成が可能となる。
【図面の簡単な説明】
【図１】本発明の実施形態による多層配線の形成方法を工程順に示す概略断面図である。
【図２】図１に引き続き、本発明の実施形態による多層配線の形成方法を工程順に示す概略断面図である。
【図３】図２に引き続き、本発明の実施形態による多層配線の形成方法を工程順に示す概略断面図である。
【図４】中間層のＣＶＤ成膜原料であるＺｒ｛Ｎ（Ｃ2Ｈ5）2｝4の熱物性評価を示す特性図である。
【図５】中間層及びＣｕシード層を成膜するためのＣＶＤチャンバーを示す模式図である。
【図６】本実施形態の半導体装置の一例を示す概略断面図である。
【符号の説明】
２，８，１１，１０５ 層間絶縁膜
３，９ ＳｉＮ膜
４，１２ 配線溝
５，１４ 下地層（バリアメタル層）
６，１７ Ｃｕ層
７ 下部Ｃｕ配線
１０ 孔部
１３ ビア孔
１５ 中間層
１６ Ｃｕシード層
１８ 上部Ｃｕ配線
１０１ 半導体基板
１０２ ゲート絶縁膜
１０３ ゲート電極
１０４ ソース／ドレイン
１０６ コンタクト孔[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring formation method and a semiconductor device in which a wiring is filled in a fine groove of an insulating film by a so-called damascene method, and in particular, dual damascene formed so as to connect the wiring to a lower layer wiring through a via hole. It is suitable to apply to the law.
[0002]
[Prior art]
Conventionally, Cu wiring having low resistance and high electromigration (EM) resistance is expected as a highly reliable material capable of meeting the recent demand for higher integration and miniaturization of LSIs.
[0003]
On the other hand, Cu is a wiring material that is difficult to finely process, and there is a limit to fine processing in photolithography, for example, like ordinary metal wiring.
[0004]
Therefore, as one of the effective methods for fine processing of Cu wiring, via / groove processing is performed on the base insulating film covering the lower layer wiring, and the via hole and the groove are filled with Cu so that the via hole is connected. The dual damascene method for forming a multi-layer wiring has begun to attract attention. An electrolytic plating method has been studied as a method most suitable for practical use in which Cu is embedded using this dual damascene method.
[0005]
[Problems to be solved by the invention]
When forming a Cu wiring using the electrolytic plating method, a Cu seed layer is required as a plating base film, and the Cu seed layer is currently formed by sputtering. However, when a fine wiring (for example, an aspect ratio of 3 or more) is formed by using the dual damascene method together with the electrolytic plating method, a sputtering method is used so as to neatly cover the inner wall surface of the fine and complicated groove and via hole. It is extremely difficult to form a Cu seed layer.
[0006]
Therefore, instead of sputtering, application of chemical vapor deposition (CVD) is being studied as an effective technique for neatly forming a Cu seed layer on the inner wall surface having a high aspect ratio structure.
[0007]
As described above, the Cu seed layer is required to have excellent adhesion to the base film in addition to the surface coverage with respect to the base structure as described above. When the Cu seed layer is formed using the CVD method, a sufficient effect can be obtained with respect to the surface coverage, but there is a problem that the adhesion with the base film is weakened. If the Cu seed layer is inferior in adhesion, further deterioration of adhesion occurs in the state in which the subsequent Cu plating film is formed, and peeling of the Cu plating film occurs in the subsequent chemical mechanical polishing (CMP) process. Therefore, it cannot be said that it can be used as an actual process.
[0008]
As described above, when forming a fine Cu wiring by using the electrolytic plating method in combination with the dual damascene method, the improvement of the surface coverage of the Cu plating film can be solved by the introduction of the CVD method, but due to the decrease in adhesion. The adverse effects are enormous, and a suitable method to overcome this is being sought.
[0009]
The present invention has been made in view of the above problems, and in forming a fine Cu wiring by using an electroplating method in combination with a damascene method, not only the surface coverage of the Cu plating film but also the adhesion to the base film. It is an object of the present invention to provide a method for forming a highly reliable wiring corresponding to further miniaturization and higher integration, and a semiconductor device provided with the wiring, capable of forming a desired fine wiring by sufficiently securing To do.
[0010]
[Means for Solving the Problems]
As a result of intensive studies, the present inventors have arrived at the following aspects of the invention.
[0011]
The first aspect is a wiring forming method in which a fine Cu wiring is formed by using an electroplating method together with a damascene method. Specifically, a step of forming at least a wiring groove in an insulating film formed on the upper layer of the substrate and a base layer made of a material containing at least a refractory metal so as to cover the inner wall surface of the wiring groove are chemically vaporized. A step of forming by phase growth, a step of forming an intermediate layer made of Zr or a Zr compound by chemical vapor deposition, a step of forming a seed layer for electrolytic plating by chemical vapor deposition, and the wiring trench Forming a copper or copper-containing metal layer by an electrolytic plating method so as to embed the copper, and polishing the copper or copper-containing metal layer to fill the wiring groove so that the copper or copper-containing metal is filled Forming a wiring leaving a layer, and after forming the intermediate layer, Annealing and reducing the intermediate layer .
[0012]
Here, a film forming material by chemical vapor deposition used for forming the intermediate layer is a gas or a liquid at room temperature, an appropriate growth temperature of the intermediate layer is 350 ° C. to 450 ° C., and the growth temperature It is preferable to have a high vapor pressure in the following predetermined temperature range for handling.
[0013]
In this case, it is preferable that the step of forming the base layer and the step of forming the intermediate layer are continuously performed in the same film formation chamber.
[0014]
In addition, in the film-forming raw material by chemical vapor deposition used for forming the intermediate layer and the adduct chemically bonded to the refractory metal in the film-forming raw material by chemical vapor deposition used when forming the underlayer It is preferable that Zr and the chemically bonded adduct are the same.
[0015]
Further, the step of forming the base layer and the step of forming the intermediate layer may be performed in respective independent film formation chambers connected via a vacuum.
[0016]
In this case, a raw material for film formation by chemical vapor deposition used for forming the intermediate layer is a gas or a liquid at room temperature, an appropriate growth temperature of the intermediate layer is 100 ° C. to 450 ° C., and the growth temperature It is preferable to have a high vapor pressure in the following predetermined temperature range for handling.
[0017]
In addition, the first aspect is suitable for application to a dual damascene method that requires a more complicated and fine film formation as compared with the case where the damascene method is used. That is, a lower wiring is formed in an upper layer of the substrate, and when forming the wiring so as to be electrically connected to the lower wiring through a connection hole, the base film is formed in the wiring groove and the connection hole. After forming so as to cover the wall surface, the intermediate layer and the seed layer are formed, and the copper or a metal layer containing copper is formed so as to fill the wiring groove and the connection hole.
[0020]
[Action]
The chemical vapor deposition method (CVD method) is the most effective means for forming a film with excellent surface coverage on a finely shaped, high aspect ratio, complex shape portion. Therefore, in the present invention, when forming a fine Cu wiring with a high aspect ratio by using an electrolytic plating method together with a damascene method, a base film containing a refractory metal and a seed layer for electrolytic plating are formed by a CVD method. In addition, an intermediate layer made of Zr or a Zr compound is formed between the base film and the seed layer by a CVD method. Due to the presence of this intermediate layer, the seed layer is formed with excellent surface coverage and good adhesion, and depending on this, the copper layer or the metal layer containing copper by electroplating has fine adhesion and fine wiring grooves (and connection holes). The inside is filled and desired fine wiring is realized.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.
[0022]
(Formation of multilayer wiring according to this embodiment)
In the present embodiment, a suitable method for forming a high-aspect-ratio fine Cu or Cu-containing metal multilayer wiring, here, a multilayer Cu wiring by using an electroplating method in combination with a so-called dual damascene method is disclosed.
1 to 3 are schematic cross-sectional views showing a method of forming a multilayer Cu wiring (here, two layers) according to the present embodiment in the order of steps.
[0023]
First, as shown in FIG. 1A, SiO is formed so as to cover a semiconductor substrate (not shown) on which a predetermined semiconductor element is formed. 2 After the interlayer insulating film 2 is deposited and formed to a thickness of about 500 nm using the material as a material, a thin SiN film 3 having a thickness of about 30 nm is formed, and the SiN film 3 and the interlayer insulating film 2 are processed by photolithography and subsequent dry etching. Then, a pattern of the wiring trench 4 having a width of about 300 nm and a depth of about 530 nm is formed.
[0024]
Subsequently, on the SiN film 3 including the inner wall surface of the wiring trench 4, a base layer (barrier metal layer) 5 made of a material containing a refractory metal, here TiN or TaN, is formed to a film thickness of about 10 nm by the CVD method. Then, a Cu seed layer 1 for plating is formed to a film thickness of about 50 nm by a CVD method, and then a Cu layer 6 is deposited on the SiN film 3 so as to fill the wiring groove 4 by an electrolytic plating method.
[0025]
Then, using the SiN film 3 as a stopper, the Cu layer 6 is subjected to chemical mechanical polishing (CMP) to form a lower Cu wiring 7 filling the wiring groove 4.
[0026]
Subsequently, as shown in FIG. 1B, SiO 2 is formed on the SiN film 3 including the lower Cu wiring 7. 2 After the interlayer insulating film 8 is deposited and formed to a thickness of about 700 nm using as a material, a thin SiN film 9 having a thickness of about 30 nm is formed, and the SiN film 9 is processed by photolithography and subsequent dry etching to form a lower Cu wiring. The hole 10 is formed in a pattern immediately above the surface 7.
[0027]
Subsequently, as shown in FIG. 1C, SiON is formed on the SiN film 9 including the hole 10. 2 An interlayer insulating film 11 is deposited and formed to a thickness of about 500 nm using the above as a material, and the interlayer insulating films 8 and 11 are processed by photolithography and subsequent dry etching. At this time, the wiring groove 12 is patterned in the interlayer insulating film 11 following the resist mask shape on the interlayer insulating film 11, and the SiN film 9 existing at the bottom of the wiring groove 12 serves as a mask to form the hole 10. A pattern following the shape is formed in the interlayer insulating film 8, and a via hole 13 exposing a part of the surface of the lower Cu wiring 7 is formed.
[0028]
Subsequently, as shown in FIG. 2A, an underlying layer (barrier) made of a material containing a refractory metal, here TiN or TaN, is formed on the interlayer insulating film 11 including the inner wall surfaces of the wiring trench 12 and the via hole 13. A metal layer 14 is formed to a thickness of about 10 nm by a CVD method.
[0029]
Subsequently, as shown in FIG. 2B, an intermediate layer 15 made of Zr or a Zr compound, here Zr, is formed to a thickness of about 5 nm by a CVD method so as to cover the barrier metal layer 14. As will be described later, it is preferable to anneal the semiconductor substrate before and after forming the intermediate layer 15. After the annealing treatment, H 2 (H 2 + N 2 It is preferable to perform plasma treatment using gas and Hhfac treatment.
[0030]
Further, as will be described later, the formation process of the barrier metal layer 14 and the formation process of the intermediate layer 15 can be continuously performed at the same film formation temperature in the same film formation chamber by appropriately selecting each CVD film formation raw material. It becomes possible.
[0031]
Subsequently, as shown in FIG. 2C, a Cu seed layer 16 for Cu plating is formed to a thickness of about 50 nm by a CVD method so as to cover the intermediate layer 15. As will be described later, it is preferable to perform annealing again after the formation of the Cu seed layer 16.
[0032]
Subsequently, as shown in FIG. 3A, a Cu layer 17 is deposited on the Cu seed layer 16 so as to fill the wiring trench 12 and the via hole 13 by electrolytic plating.
[0033]
Then, as shown in FIG. 3B, the Cu layer 17 is subjected to chemical mechanical polishing (CMP) to form an upper Cu wiring 18 that fills the wiring groove 12 and the via hole 13.
Through the above steps, a fine multilayer wiring in which the lower Cu wiring 7 and the upper Cu wiring 18 are electrically connected through the via hole 13 is completed.
[0034]
Although an example in which the intermediate layer 15 is used only for the formation of the upper Cu wiring 18 is disclosed here, it may be applied to the lower Cu wiring 7 as a matter of course. In fact, when further miniaturizing the multilayer wiring, it is preferable to apply the intermediate layer 15 also to the lower Cu wiring 7 having no via hole 13.
[0035]
(Functions of main configuration according to this embodiment)
In the multilayer wiring formation method described above, the main configuration of the present embodiment is that when forming the upper Cu wiring 18 in which a fine and complicated portion in which the wiring groove 12 and the via hole 13 are integrated is filled with Cu. In addition to forming the barrier metal layer 14 and the Cu seed layer 16 by the CVD method, an intermediate layer 15 made of Zr or a Zr compound is formed by the CVD method between the barrier metal layer 14 and the Cu seed layer 16. There is.
[0036]
Here, in forming the intermediate layer 15, it is important to appropriately select a film forming raw material for CVD. Specifically, comprehensive consideration is given to the effects on other components, the ease of handling the film-forming materials, the simplicity of the formation process, and the relevance to other components, particularly the barrier metal layer 14. Need to select.
[0037]
First, the film forming temperature by the CVD method becomes a problem because of the demand for mitigating the influence on other components. When a film forming material that requires a high film forming temperature is used, there is a risk of adversely affecting wirings and semiconductor elements formed particularly in the lower layer. Therefore, it is required that the film forming temperature be relatively low (preferably 450 ° C. or lower).
[0038]
Next, from the request for ease of handling, the film forming raw material is required to be a gas or a liquid at room temperature. Of course, although it is ideal that it is a gas, from the request | requirement of the said film-forming temperature restriction | limiting, the liquid film-forming raw material is actually mentioned as a use candidate. Further, the film forming raw material needs to have a sufficient vapor pressure within a predetermined temperature range for handling that is equal to or lower than the film forming temperature.
[0039]
Satisfying the above requirements is essential for the formation of the intermediate layer 15 by the CVD method. In addition to these, the formation process should be simplified from the relevance to the barrier metal layer 14. Is requested. Specifically, it is preferable to continuously execute the step of forming the barrier metal layer 14 and the step of forming the intermediate layer 15 in the same film formation chamber. As a preferred example for realizing this, the adduct that chemically bonds to the refractory metal in the CVD film forming material of the barrier metal layer 14 and the adduct that chemically bonds to Zr in the CVD film forming material of the intermediate layer 15 are the same. It is conceivable to select the film forming raw material so that
[0040]
From the above consideration, the present inventors have used Zr {N (C 2 H Five ) 2 } Four We have found that aminozirconium such as (tetradiethylaminozirconium) is one of the most preferred compounds. In the following, Zr {N (C 2 H Five ) 2 } Four The usefulness of the intermediate layer 15 as a CVD film forming raw material will be described.
[0041]
That is, Zr {N (C 2 H Five ) 2 } Four Is a liquid at room temperature, has a relatively low film forming temperature of about 200 ° C., and has a sufficient vapor pressure in a predetermined temperature range of handling below the film forming temperature.
[0042]
Specifically, Zr {N (C 2 H Five ) 2 } Four The thermophysical property evaluation was performed.
First, using a pressure measuring device as shown in the circle of FIG. 4, Zr {N (C 2 H Five ) 2 } Four When the pressure was measured during heating, as shown in the characteristic curve of FIG. 4, it was found that the rate of increase in pressure changed from around 100 ° C., and thermal decomposition occurred from around this. As a result of obtaining the vapor pressure curve from the pressure change in the region below 100 ° C., the saturated vapor pressure P (Torr)
logP = −1756 / T + 4.727 (313 <T <353) (1)
It turned out to be. This is a satisfactory value as a CVD film forming material.
[0043]
Furthermore, it was found that the rate of pressure increase changed rapidly from around 200 ° C. As a result of FI-IR measurement of residual gas,
The change from around 100 ° C. is based on R as the predetermined hydrogen
Zr {N (C 2 H Five ) 2 } Four → Zr + 2HN (C 2 H Five ) 2 + N 2 + 2RH (2)
The change from around 200 ° C. is based on R as the predetermined hydrogen
2HN (C 2 H Five ) 2 → N 2 + 2RH (3)
It is predicted that
[0044]
From the above results, Zr {N (C 2 H Five ) 2 } Four Can be formed from a relatively low film formation temperature of about 100 ° C., preferably about 200 ° C., and has a sufficient saturated vapor pressure, and is easy to handle, It was found that the desired accurate film formation is possible.
[0045]
Furthermore, Zr {N (C 2 H Five ) 2 } Four Is Ti {N (C) used as a CVD film forming material for the barrier metal film 14. 2 H Five ) 2 } Four (Tetradiethylaminotitanium) and the part corresponding to the adduct, ie {N (C 2 H Five ) 2 } Are the same, there is no possibility of generating a side reaction product. Therefore, the step of forming the barrier metal layer 14 and the step of forming the intermediate layer 15 are continuously performed in the same film formation chamber. Is possible.
[0046]
Here, Ti {N (C 2 H Five ) 2 } Four The saturated vapor pressure P (Torr) of the temperature is T (K),
logP = -3038 / T + 7.906 (4)
Zr {N (C 2 H Five ) 2 } Four The saturated vapor pressure of Zr {N (C 2 H Five ) 2 } Four And Ti {N (C 2 H Five ) 2 } Four Since the decomposition temperatures are close to each other, continuous growth at the same temperature is possible. The deposition temperature is limited to 350 ° C. to 450 ° C. because the barrier metal layer 14 requires a higher temperature. Therefore, in this case, the barrier metal layer 14 and the intermediate layer 15 can be continuously formed only by switching the CVD film forming material, and the number of steps can be greatly reduced and simplified. Of course, when the barrier metal layer 14 and the intermediate layer 15 are formed in separate film formation chambers, the film formation temperature of the intermediate layer 15 is set within a range of 100 ° C. to 450 ° C. independently of the barrier metal layer 14. be able to.
[0047]
As explained above, Zr {N (C 2 H Five ) 2 } Four Was found to be optimal as a CVD film forming material for the intermediate layer 15. Then, by forming the intermediate layer 15 in this way, it is possible to form a fine Cu wiring with a high aspect ratio with excellent surface coverage and good adhesion by using the electroplating method together with the damascene method.
[0048]
Furthermore, it was confirmed that further improvement in adhesion was realized by performing an annealing process before and after each step of forming the intermediate layer 15 and the Cu seed layer 16. This is because the annealing process removes impurities remaining in the film for the barrier metal layer 14, removal of impurities remaining in the film for the intermediate layer 15, improvement of crystallinity and de-N, and Cu seed layer 16. This is because each effect of removing impurities remaining in the film is exhibited.
[0049]
Also, Zr {N (C 2 H Five ) 2 } Four Contains nitrogen (N), so that the deposited intermediate layer 15 made of Zr tends to be nitrided. The resistivity of ZrN is 13.6 μΩcm, which is lower than the resistivity of Zr, 40.0 μΩcm, but is Zr which is a tetravalent nitride. Three N Four Is a high-resistance material, and is slightly problematic when used for the via hole 13. Therefore, in order to prevent the resistance of the intermediate layer 15 from being increased, reduction treatment, in particular H, is performed after the intermediate layer 15 is formed. 2 (H 2 + N 2 It is effective to perform plasma treatment using gas or Hhfac treatment. Further, as the material of the barrier metal layer, it is preferable to use a refractory metal that can easily form nitrides such as Ta and Ti, thereby suppressing nitridation of Zr and preventing high resistance.
[0050]
(Experimental example)
Hereinafter, each experiment in which various effects of the main configuration according to the above-described embodiment are examined will be described.
Here, Zr {N (C 2 H Five ) 2 } Four As shown in FIG. 5, the intermediate layer 15 and the Cu seed layer 16 were formed using a CVD film forming chamber in which a reaction chamber A and a reaction chamber B were provided side by side through a transfer chamber.
[0051]
-Experiment 1
As the barrier metal layer 14, a base substrate on which a TaN film having a thickness of about 20 nm was formed by the PVD method was used. First, the intermediate layer 15 was formed in the reaction chamber A, and then the Cu seed layer 16 was formed in the reaction chamber B.
[0052]
Each film formation condition at this time is
For the intermediate layer 15, the bubbler temperature was 50 ° C., the supply amount was 200 sccm, the carrier gas was He, the supply amount was 500 sccm, the substrate temperature was 250 ° C., and the pressure was 1 kPa.
For the Cu seed layer 16, Cu (hfac) TMVS-1.0 g / min is used as the CVD film-forming material for Cu, and H is used as the carrier gas. 2 The supply amount was 500 sccm, the substrate temperature was 180 ° C., and the pressure was 1 kPa.
[0053]
The film thicknesses of the intermediate layer 15 and the Cu seed layer 16 formed were about 10 nm and about 50 nm, respectively.
As a result of plating the Cu layer 17 on the obtained Cu seed layer 16 to a thickness of about 1 μm and performing CMP, it was confirmed that no film peeling occurred.
[0054]
-Experiment 2-
An intermediate layer 15 and a Cu seed layer 16 were formed in the same manner as in Experiment 1 using a base substrate on which a TiN film having a thickness of about 10 nm was formed by CVD as the barrier metal layer 14. Here, before the intermediate layer 15 was formed, an annealing treatment was performed at 400 ° C. for 10 minutes.
A Cu layer 17 was plated on the obtained Cu seed layer 16 to a thickness of about 1 μm, and a tape test was performed. As a result, the adhesiveness was better than when the annealing treatment was not performed.
[0055]
-Experiment 3-
In the same manner as in Experiment 1, the intermediate layer 15 and the Cu seed layer 16 were formed. Here, after the intermediate layer 15 is formed, H 2 Was used for annealing at 300 ° C. for 10 minutes.
A Cu layer 17 was plated on the obtained Cu seed layer 16 to a thickness of about 1 μm, and a tape test was performed. As a result, the adhesiveness was better than when the annealing treatment was not performed.
[0056]
-Experiment 4
In the same manner as in Experiment 1, the intermediate layer 15 and the Cu seed layer 16 were formed. Here, H is formed before the Cu seed layer 16 is formed. 2 Plasma treatment using was performed.
As a result of measuring the resistance of the obtained Cu seed layer 16, it was confirmed that the specific resistance was 2.8 μΩcm, which was smaller than 3.5 μΩcm when the plasma treatment was not performed.
[0057]
-Experiment 5
In the same manner as in Experiment 1, the intermediate layer 15 and the Cu seed layer 16 were formed. Here, before the Cu seed layer 16 was formed, the Hhfac treatment was performed under conditions of a supply amount of 10 sccm, 1 min, and 180 ° C.
As a result of measuring the resistance of the obtained Cu seed layer 16, it was confirmed that the specific resistance was 2.9 μΩcm, which was smaller than 3.5 μΩcm when the Hhfac treatment was not performed.
[0058]
-Experiment 6
An intermediate layer 15 and a Cu seed layer 16 were formed in the same manner as in Experiment 1 using a base substrate on which a Ta film was formed by the PVD method as the barrier metal layer 14.
As a result of measuring the resistance of the obtained Cu seed layer 16, it was confirmed that the specific resistance was as low as 2.7 μΩcm.
[0059]
-Experiment 7-
In the same manner as in Experiment 1, the intermediate layer 15 and the Cu seed layer 16 were formed. Here, after the Cu seed layer 16 was formed, an annealing treatment was performed for 10 minutes at 350 ° C. in vacuum.
A Cu layer 17 was plated on the obtained Cu seed layer 16 to a thickness of about 1 μm, and a tape test was performed. As a result, the adhesiveness was better than when the annealing treatment was not performed.
[0060]
-Experiment 8-
First, Ti {N (C 2 H Five ) 2 } Four As a CVD film forming material, a barrier metal layer 14 made of TiN was formed to a thickness of about 10 nm at a film forming temperature of 350 ° C., and then an intermediate layer 15 was formed continuously in the same film forming chamber.
The deposition conditions of the intermediate layer 15 were as follows: the bubbler temperature was 50 ° C., the supply amount was 100 sccm, the carrier gas was He, the supply amount was 500 sccm, the substrate temperature was 350 ° C., and the pressure was 0.5 kPa.
A Cu layer 17 was plated to a thickness of about 1 μm on the Cu seed layer 16 having a thickness of about 50 nm, and a tape test was performed. As a result, good adhesion was shown.
[0061]
-Experiment 9-
A base substrate on which a TiN film having a thickness of about 10 nm is formed by a CVD method is used as the barrier metal layer 14, and the intermediate layer 15 is (1) about 10 nm thick, (2) about 20 nm thick, and (3) about 50 nm thick. Then, the Cu seed layer 16 was formed to a film thickness of about 50 nm.
As a result of plating a Cu layer 17 on the obtained Cu seed layer 16 to a film thickness of about 1 μm and performing a tape test, the adhesion strength was (1)>(2)> (3), and (1), About (2), it confirmed confirming favorable adhesiveness.
[0062]
The tape test results for various conditions including the experimental results are shown in Table 1 below.
[0063]
[Table 1]
Figure 0004733804
[0064]
As described above, according to the present embodiment, when a fine Cu wiring having a high aspect ratio is formed by using an electrolytic plating method together with a damascene method, the barrier metal layer 14 containing a refractory metal and the electrolytic plating are used. In addition to forming the Cu seed layer 16 by the CVD method, an intermediate layer 15 made of Zr or a Zr compound is formed by the CVD method between the barrier metal layer 14 and the Cu seed layer 16. Due to the presence of the intermediate layer 15, the Cu seed layer 16 is formed with excellent surface coverage and good adhesion, and depending on this, the Cu layer 17 formed by electrolytic plating has fine adhesion in the fine wiring grooves (and connection holes). The desired fine wiring 18 is realized.
[0065]
(Semiconductor device with multilayer wiring)
Specifically, FIG. 6 shows an example of a semiconductor device in which a semiconductor element is provided on a semiconductor substrate and a multilayer wiring is formed by the above-described steps.
[0066]
This semiconductor device includes a MOS transistor formed on a semiconductor substrate 101 and a multilayer wiring (here, two layers) connected to the MOS transistor.
[0067]
The MOS transistor has a configuration in which a strip-like gate electrode 103 is patterned through a gate insulating film 102, and impurities are introduced into the surface layer of the semiconductor substrate 1 on both sides of the gate electrode 103 to form a source / drain 104. .
[0068]
Further, an interlayer insulating film 105 covering the MOS transistor is formed, and the aforementioned lower Cu wiring 7 is formed via the source / drain 104 and the contact hole 106. Then, an upper Cu wiring 18 is formed so as to be connected to the lower Cu wiring 7 via the via hole 13 to constitute a semiconductor device. Here, the lower Cu wiring 7 and the upper Cu wiring 18 are formed by using the dual damascene method in combination with the electrolytic plating method as described above. In particular, the upper Cu wiring 18 includes the wiring groove 12 and the via hole 13. A barrier metal layer 14, an intermediate layer 15 made of Zr or a Zr compound, and a Cu seed layer 16 are sequentially formed on the inner wall surface of the substrate by a CVD method so that the wiring trench 12 and the via hole 13 are filled with Cu plating. Is.
[0069]
This semiconductor device has fine multilayer wiring that ensures excellent surface coverage and adhesion, and is highly reliable to meet the recent demand for miniaturization and high integration of devices. Is.
[0070]
In the present embodiment, the case of forming the multilayer Cu wiring is exemplified, but the present invention is not limited to this and can be applied to a metal multilayer wiring containing Cu. Specifically, Cu—Sn, Cu—Ag, or the like is preferable as the metal, and migration resistance can be greatly improved.
[0071]
The following aspects also constitute the present invention.
[0072]
Aspect 1 is the wiring formation method according to the first aspect, wherein the step of forming the base layer and the step of forming the intermediate layer are continuously performed in the same film formation chamber. In this case, the film forming temperature in both the steps is set to the same temperature of 350 ° C. to 450 ° C.
[0073]
Aspect 2 is the method for forming a wiring according to the first aspect, wherein the step of forming the base layer and the step of forming the intermediate layer are performed in independent film forming chambers. The film forming temperature in the former process is 350 ° C. to 450 ° C., and the film forming temperature in the latter process is 100 ° C. to 450 ° C.
[0074]
Aspect 3 is the wiring formation method according to the first aspect, characterized in that the film-forming raw material by chemical vapor deposition used for forming the intermediate layer is aminozirconium.
[0075]
Aspect 4 is the wiring formation method according to the first aspect, characterized in that an annealing treatment is performed after the foundation layer is formed.
[0076]
Aspect 5 is the wiring formation method according to the first aspect, and is characterized in that an annealing treatment is performed after the intermediate layer is formed.
[0077]
Aspect 6 is the wiring formation method according to the first aspect, characterized in that an annealing treatment is performed after the Cu seed layer is formed.
[0078]
Aspect 7 is the wiring forming method according to the first aspect, wherein after the intermediate layer is formed, the intermediate layer is subjected to plasma treatment before the Cu seed layer is formed. .
[0079]
Aspect 8 is the method for forming a wiring according to the first aspect, wherein the intermediate layer is subjected to Hhfac treatment after the intermediate layer is formed and before the Cu seed layer is formed. .
[0080]
Aspect 9 is the wiring formation method according to the first aspect, wherein the intermediate layer is formed to a thickness of 10 nm or less.
[0081]
A tenth aspect is the semiconductor device according to the second aspect, wherein the first to ninth aspects are applied.
[0082]
【The invention's effect】
According to the present invention, when forming a fine Cu wiring by using the electroplating method together with the damascene method, not only the surface coverage of the Cu plating film but also sufficient adhesion with the base film is ensured to obtain the desired fineness. Wiring can be formed, and highly reliable wiring corresponding to further miniaturization and higher integration can be formed.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view illustrating a multilayer wiring forming method according to an embodiment of the present invention in the order of steps.
FIG. 2 is a schematic cross-sectional view subsequent to FIG. 1, showing a multilayer wiring forming method according to an embodiment of the present invention in the order of steps.
FIG. 3 is a schematic cross-sectional view subsequent to FIG. 2, illustrating a multilayer wiring forming method according to an embodiment of the present invention in the order of steps.
FIG. 4 shows Zr {N (C 2 H Five ) 2 } Four It is a characteristic view which shows the thermophysical property evaluation of.
FIG. 5 is a schematic view showing a CVD chamber for forming an intermediate layer and a Cu seed layer.
FIG. 6 is a schematic cross-sectional view showing an example of a semiconductor device of the present embodiment.
[Explanation of symbols]
2, 8, 11, 105 Interlayer insulating film
3.9 SiN film
4,12 Wiring groove
5,14 Underlayer (barrier metal layer)
6,17 Cu layer
7 Lower Cu wiring
10 holes
13 Via hole
15 Middle layer
16 Cu seed layer
18 Upper Cu wiring
101 Semiconductor substrate
102 Gate insulation film
103 Gate electrode
104 source / drain
106 Contact hole

Claims (10)

基板の上層に形成された絶縁膜に少なくとも配線溝を形成する工程と、
前記配線溝の内壁面を覆うように、少なくとも高融点金属を含有する材料からなる下地層を化学気相成長法により形成する工程と、
Ｚｒ又はＺｒ化合物からなる中間層を化学気相成長法により形成する工程と、
電解メッキ用のシード層を化学気相成長法により形成する工程と、
前記配線溝を埋め込むように電解メッキ法により銅又は銅を含む金属層を形成する工程と、
前記銅又は銅を含む金属層を研磨して、前記配線溝内を充填するように前記銅又は銅を含む金属層を残して配線を形成する工程と
を有し、
前記中間層を形成した後に、前記中間層に対してアニール処理及び還元処理を施すことを特徴とする配線の形成方法。Forming at least a wiring groove in an insulating film formed in an upper layer of the substrate;
Forming a base layer made of a material containing at least a refractory metal by chemical vapor deposition so as to cover the inner wall surface of the wiring groove;
Forming an intermediate layer made of Zr or a Zr compound by chemical vapor deposition;
Forming a seed layer for electrolytic plating by chemical vapor deposition;
Forming a copper or copper-containing metal layer by electrolytic plating so as to fill the wiring groove;
Polishing the copper or copper-containing metal layer, and forming the wiring leaving the copper or copper-containing metal layer so as to fill the wiring groove,
After forming the said intermediate | middle layer, an annealing process and a reduction process are performed with respect to the said intermediate | middle layer, The formation method of the wiring characterized by the above-mentioned. 前記中間層を形成する際に用いる化学気相成長による成膜原料は、常温で気体又は液体であり、前記中間層を、３５０℃〜４５０℃の成長温度で形成することを特徴とする請求項１に記載の配線の形成方法。  The raw material for film formation by chemical vapor deposition used for forming the intermediate layer is a gas or a liquid at normal temperature, and the intermediate layer is formed at a growth temperature of 350 ° C. to 450 ° C. A method for forming a wiring according to 1. 前記下地層を形成する前記工程と、前記中間層を形成する前記工程とを同一の成膜室内で連続的に実行することを特徴とする請求項２に記載の配線の形成方法。  3. The method of forming a wiring according to claim 2, wherein the step of forming the base layer and the step of forming the intermediate layer are continuously performed in the same film formation chamber. 前記下地層を形成する際に用いる化学気相成長による成膜原料における前記高融点金属と化学結合した付加物と、前記中間層を形成する際に用いる化学気相成長による成膜原料におけるＺｒと化学結合した付加物とが同一であることを特徴とする請求項３に記載の配線の形成方法。  An adduct chemically bonded to the refractory metal in the film forming raw material by chemical vapor deposition used for forming the underlayer, and Zr in the film forming raw material by chemical vapor deposition used to form the intermediate layer, 4. The method of forming a wiring according to claim 3, wherein the chemically bonded adduct is the same. 前記中間層を形成する際に用いる化学気相成長による成膜原料は、常温で気体又は液体であり、前記中間層を、１００℃〜４５０℃の成長温度で形成することを特徴とする請求項１に記載の配線の形成方法。  The raw material for film formation by chemical vapor deposition used for forming the intermediate layer is a gas or a liquid at normal temperature, and the intermediate layer is formed at a growth temperature of 100 ° C to 450 ° C. A method for forming a wiring according to 1. 前記下地層を形成する前記工程と、前記中間層を形成する前記工程とを、真空を介して接続したそれぞれ独立の成膜室内で実行することを特徴とする請求項５に記載の配線の形成方法。  6. The wiring formation according to claim 5, wherein the step of forming the base layer and the step of forming the intermediate layer are performed in respective independent film formation chambers connected via a vacuum. Method. 前記基板の上層に下部配線が形成されており、前記下部配線と接続孔を通じて電気的に接続されるように前記配線を形成するに際して、前記下地膜を前記配線溝及び前記接続孔の内壁面を覆うように形成した後、前記中間層及び前記シード層を形成し、前記配線溝及び前記接続孔を埋め込むように前記銅又は銅を含む金属層を形成することを特徴とする請求項１に記載の配線の形成方法。  A lower wiring is formed in an upper layer of the substrate, and when forming the wiring so as to be electrically connected to the lower wiring through a connection hole, the base film is formed on the inner surface of the wiring groove and the connection hole. The said intermediate | middle layer and the said seed layer are formed after forming so that it may cover, The metal layer containing the said copper or copper is formed so that the said wiring groove | channel and the said connection hole may be embedded. Wiring formation method. 前記シード層を形成した後に、アニール処理を行うことを特徴とする請求項１〜７のいずれか１項に記載の配線の形成方法。  The method of forming a wiring according to claim 1, wherein annealing is performed after the seed layer is formed. 前記下地層を形成した後に、アニール処理を行うことを特徴とする請求項１〜８のいずれか１項に記載の配線の形成方法。  The method of forming a wiring according to claim 1, wherein an annealing process is performed after the foundation layer is formed. 前記還元処理がＨ2を用いたプラズマ処理又はＨｈｆａｃ処理であることを特徴とする請求項１〜９のいずれか１項に記載の配線の形成方法。The wiring forming method according to claim 1, wherein the reduction treatment is a plasma treatment using H 2 or an Hhfac treatment.
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