KR20030049355A - Method of forming an metal line in semiconductor device - Google Patents
Method of forming an metal line in semiconductor device Download PDFInfo
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- KR20030049355A KR20030049355A KR1020010079546A KR20010079546A KR20030049355A KR 20030049355 A KR20030049355 A KR 20030049355A KR 1020010079546 A KR1020010079546 A KR 1020010079546A KR 20010079546 A KR20010079546 A KR 20010079546A KR 20030049355 A KR20030049355 A KR 20030049355A
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- metal
- insulating layer
- forming
- insulating film
- insulating
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 69
- 239000002184 metal Substances 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 229910052718 tin Inorganic materials 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 7
- 238000005498 polishing Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 39
- 239000011229 interlayer Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 메탈 라인 형성 방법에 관한 것으로, 메탈 밀도(Metal density)에의해 나타나는 메탈 라인의 높이 차인 메탈 씬닝 형상을 제거하여 반도체 소자의 저항을 안정적으로 확보하여 소자의 신뢰성 향상, 동작 속도의 향상 및 수율 향상을 할 수 있는 반도체 소자의 메탈 라인 형성 방법에 관한 것이다.The present invention relates to a method for forming a metal line, by removing the metal thinning shape, which is the difference in height of the metal line due to the metal density, to secure the resistance of the semiconductor device to improve the reliability of the device, improve the operation speed and It relates to a metal line forming method of a semiconductor device capable of improving the yield.
종래의 다마스신(Damascene) 공정에서 메탈 증착시 메탈 라인이 밀한 곳과 소한 곳의 높이 차이가 생기게 된다.In the conventional Damasin process (Damascene), when the metal deposition in the metal line is a difference between the height of the dense place and the small place.
도 1은 종래 기술에 따른 메탈 라인을 형성하기 위해 메탈 층을 증착한 후의 단면도이다.1 is a cross-sectional view after depositing a metal layer to form a metal line according to the prior art.
도 1을 참조하면, 소정의 구조가 형성된 반도체 기판상에 제 1 및 제 2 영역(A 및 B)에 층간 절연막(1)이 형성되고 상기 층간 절연막(1)을 소정의 식각 공정을 통하여 식각한 후 상기 반도체 기판 상에 메탈 층(2)을 증착한다. 이때 제 1 및 제 2 영역(A 및 B)의 상기 메탈 층(2)의 두께차이가 발생한다. 즉 상기 메탈 라인이 밀한 곳은 소한 곳에 비해 상기 메탈 층(2)의 두께가 더 얇다.Referring to FIG. 1, an interlayer insulating film 1 is formed in first and second regions A and B on a semiconductor substrate on which a predetermined structure is formed, and the interlayer insulating film 1 is etched through a predetermined etching process. After that, a metal layer 2 is deposited on the semiconductor substrate. In this case, a thickness difference between the metal layers 2 of the first and second regions A and B occurs. That is, where the metal line is dense, the thickness of the metal layer 2 is thinner than the place where the metal line is dense.
도 2는 종래 기술에 따른 메탈 층을 CMP공정을 통하여 제거하여 메탈 라인을 형성한 단면도이다.2 is a cross-sectional view of a metal line formed by removing a metal layer according to the prior art through a CMP process.
도 2를 참조하면, 상기 메탈 층(2)의 두께 차에 의해 CMP공정 후 형성된 메탈 라인의 높이 차가 유발된다. 일반적으로 상기 메탈 층(2)에 비해 상기 층간 절연막(1)으로 사용되는 산화막의 제거 율이 낮아 제 1 영역이 제 2 영역에 비해 두께가 더 낮아지는 메탈 씬닝(Metal thinning) 현상을 유발한다.Referring to FIG. 2, the height difference of the metal line formed after the CMP process is caused by the thickness difference of the metal layer 2. In general, the removal rate of the oxide film used as the interlayer insulating film 1 is lower than that of the metal layer 2, thereby causing a metal thinning phenomenon in which the first region has a lower thickness than the second region.
상기 메탈 라인의 두께 차에 의한 메탈 씬닝 현상은 반도체 소자의 저항을증가 시켜 소자의 신뢰도와 동작 속도저하의 원인이 된다.The metal thinning phenomenon due to the thickness difference of the metal lines increases the resistance of the semiconductor device, causing the reliability and the operating speed of the device to decrease.
따라서 본 발명은 상술한 단점을 해소 할 수 있는 반도체 소자의 메탈 라인 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal line of a semiconductor device that can solve the above-mentioned disadvantages.
본 발명의 다른 목적은 구리층 상에 산화막을 형성하여 CMP 공정시 구리 층과 산화막의 식각 속도를 조절함으로써 메탈 라인이 밀한 곳과 소한 곳의 높이 차가없는 반도체 소자를 제공한다.It is another object of the present invention to provide a semiconductor device having no height difference between a dense and a small metal line by forming an oxide film on a copper layer and controlling the etching rates of the copper layer and the oxide film during the CMP process.
도 1은 종래 기술에 따른 메탈 라인을 형성하기 위해 메탈 층을 증착한 후의 단면도.1 is a cross-sectional view after depositing a metal layer to form a metal line according to the prior art.
도 2는 종래 기술에 따른 메탈 층을 CMP공정을 통하여 제거하여 메탈 라인을 형성한 단면도.Figure 2 is a cross-sectional view of the metal layer formed by removing the metal layer according to the prior art through the CMP process.
도 3a 내지 3e는 본 발명에 따른 메탈 라인 형성 방법을 설명하기 위한 단면도.3A to 3E are cross-sectional views illustrating a metal line forming method according to the present invention.
<도면의 주요 부분에 대한 부호의설명><Description of the symbols for the main parts of the drawings>
1, 11, 12, 14 : 절연막2, 13 : 메탈 층1, 11, 12, 14: insulating film 2, 13: metal layer
반도체 기판의 제 1 영역에 제 1 절연막 패턴이 형성되는 한편 상기 반도체 기판의 제 2 영역에 상기 제 1 절연막 패턴보다 밀도가 낮은 제 2 절연막 패턴이 형성되는 단계, 상기 제 1 및 제 2 절연막 패턴 상에 메탈 층을 형성하는 단계, 상기 메탈 층 상부에 제 3 절연막을 형성하는 단계, 상기 제 3 절연막을 패터닝 하는 단계, 및 상기 제 1 및 제 2 절연막 패턴이 노출되도록 평탄화 공정을 수행하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 메탈 라인 형성 방법을 제공한다.Forming a first insulating film pattern in the first region of the semiconductor substrate, and forming a second insulating film pattern having a lower density than the first insulating film pattern in the second region of the semiconductor substrate; Forming a metal layer on the metal layer, forming a third insulating film on the metal layer, patterning the third insulating film, and performing a planarization process so that the first and second insulating film patterns are exposed. It provides a metal line forming method of a semiconductor device characterized in that.
이하 첨부된 도면을 참조하며 본 발명의 바람직한 실시 예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 3e는 본 발명에 따른 메탈 라인 형성 방법을 설명하기 위한 단면도이다.3A to 3E are cross-sectional views illustrating a metal line forming method according to the present invention.
도 3a를 참조하면, 반도체 기판의 제 1 영역(A)에 메탈 마스크 패터닝으로 제 1 절연막(12) 패턴이 형성되는 한편 상기 반도체 기판의 제 2 영역(B)에 상기 제 1 절연막(12) 패턴보다 밀집도가 낮은 제 2 절연막(11) 패턴이 메탈 마스크 패터닝에 의해 형성된다.Referring to FIG. 3A, the first insulating layer 12 pattern is formed in the first region A of the semiconductor substrate by metal mask patterning, while the first insulating layer 12 pattern is formed in the second region B of the semiconductor substrate. The second insulating film 11 pattern having a lower density is formed by metal mask patterning.
상기 제 1 및 제 2 절연막(12 및 11)을 포함한 상기 반도체 기판 상부에 메탈 층(13)을 형성한다. 이때 제 1 영역(A)의 상기 메탈 층(13)의 두께가 제 2 영역(B)의 상기 메탈 층(13)의 두께보다 더 얇다.The metal layer 13 is formed on the semiconductor substrate including the first and second insulating layers 12 and 11. At this time, the thickness of the metal layer 13 of the first region A is thinner than the thickness of the metal layer 13 of the second region B.
도 3b를 참조하면, 상기 메탈 층(13) 상에 상기 제 1 및 제 2 절연막(12 및 11)과 같은 물질의 제 3 절연막(14)을 형성한다. 이때 상기 제 3 절연막(14)의 두께는 상기 제 3 절연막(14)과 메탈의 선택도(Selectivity)를 이용하여 조절한다.Referring to FIG. 3B, a third insulating layer 14 of the same material as the first and second insulating layers 12 and 11 is formed on the metal layer 13. In this case, the thickness of the third insulating layer 14 is adjusted by using the selectivity of the third insulating layer 14 and the metal.
도 3c를 참조하면, 상기 제 3 절연막(14)을 상기 제 1 및 제 2 절연막(12 및 11))을 식각하기 위한 메탈 마스킹 공정에서 역식각(reverse etchback)을 수행하여 상기 제 3 절연막(14)을 식각한다.Referring to FIG. 3C, a reverse etchback may be performed in a metal masking process for etching the third insulating layer 14 to the first and second insulating layers 12 and 11. Etch).
즉 상기 메탈 마스킹 공정에서 식각되지 않는 부분을 역으로 식각함으로 상기 제 3 절연막(14)의 식각 부분과 상기 제 1 영역(A)의 상기 제 1 절연막(12)의 잔류 부분이 일치하고 또한 상기 제 2 영역(B)의 상기 제 2 절연막(11)의 잔류 부분과 상기 제 3 절연막(14)의 식각 부분이 일치된다. 그러므로 상기 제 3 절연막(14)은 상기 제 1 영역(A)에 비해 상기 제 2 영역(B)에서 상대적으로 많이식각된다.That is, by etching back the portion not etched in the metal masking process, the etched portion of the third insulating film 14 and the remaining portion of the first insulating film 12 of the first region A coincide with each other. The remaining portion of the second insulating layer 11 and the etching portion of the third insulating layer 14 in the second region B coincide with each other. Therefore, the third insulating layer 14 is relatively more etched in the second region B than the first region A. FIG.
도 3d를 참조하면, 상기 제 3 절연막(14) 및 상기 메탈 층(13)을 CMP공정을 수행하여 제거한다. 상기 CMP공정시 상기 제 2 영역(B)의 두꺼운 상기 메탈 층(13)이 제거되는 동안 상기 제 1 영역(A)의 제 3 절연막(14)이 제거되어 상기 제 1 영역(A)의 제거 속도를 늦게 함으로써 제 1 및 제 2 영역(A 및 B)의 상기 메탈 층(13)이 제거되는 높이를 일정하게 유지한다.Referring to FIG. 3D, the third insulating layer 14 and the metal layer 13 are removed by performing a CMP process. During the CMP process, while the thick metal layer 13 of the second region B is removed, the third insulating layer 14 of the first region A is removed to remove the first region A. By delaying, the height at which the metal layer 13 in the first and second regions A and B is removed is kept constant.
도 3e를 참조하면, 상기 CMP공정을 수행하여 상기 메탈 층(13)을 높이 차가 형성되지 않도록 제거함으로 메탈 밀도에 상관없이 높이가 일정한 메탈 라인이 형성된다.Referring to FIG. 3E, a metal line having a constant height is formed regardless of the metal density by removing the metal layer 13 so that a height difference is not formed by performing the CMP process.
이와 같이 본 발명에 의한 반도체 소자의 메탈 라인 형성 방법은 상기 메탈 마스킹 공정에서 식각이 수행되는 부분을 역으로 수행함으로 메탈 층 상부에 절연막을 형성함으로써 메탈 씬닝 현상이 없는 메탈 라인을 형성 할 수 있다.As described above, in the method for forming a metal line of the semiconductor device according to the present invention, the metal line without the metal thinning may be formed by forming an insulating film on the metal layer by performing an inverse portion in which the etching is performed in the metal masking process.
또한 메탈 씬닝 현상이 없는 메탈 라인으로 인해 안정적인 저항을 확보할 수 있어서 소자의 신뢰성 향상, 동작 속도의 향상 및 수율을 향상 할 수 있다.In addition, the metal line without the metal thinning phenomenon can ensure a stable resistance to improve the reliability of the device, improve the operating speed and improve the yield.
Claims (5)
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| KR1020010079546A KR20030049355A (en) | 2001-12-14 | 2001-12-14 | Method of forming an metal line in semiconductor device |
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| KR1020010079546A KR20030049355A (en) | 2001-12-14 | 2001-12-14 | Method of forming an metal line in semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113437134A (en) * | 2021-06-22 | 2021-09-24 | 福建省晋华集成电路有限公司 | Semiconductor structure, semiconductor structure preparation method and semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113437134A (en) * | 2021-06-22 | 2021-09-24 | 福建省晋华集成电路有限公司 | Semiconductor structure, semiconductor structure preparation method and semiconductor device |
| CN113437134B (en) * | 2021-06-22 | 2022-09-02 | 福建省晋华集成电路有限公司 | Semiconductor structure, semiconductor structure preparation method and semiconductor device |
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