KR20030049165A - Fabricating method of image sensor - Google Patents
Fabricating method of image sensor Download PDFInfo
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- KR20030049165A KR20030049165A KR1020010079304A KR20010079304A KR20030049165A KR 20030049165 A KR20030049165 A KR 20030049165A KR 1020010079304 A KR1020010079304 A KR 1020010079304A KR 20010079304 A KR20010079304 A KR 20010079304A KR 20030049165 A KR20030049165 A KR 20030049165A
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 abstract description 3
- 230000036211 photosensitivity Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 206010034960 Photophobia Diseases 0.000 description 7
- 208000013469 light sensitivity Diseases 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
Abstract
Description
본 발명은 반도체 소자에 관한 것으로 특히, 이미지센서에 관한 것으로, 더욱 상세하게는 이미지 센서의 광감도 향상을 위한 센싱 확산영역 형성 방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to an image sensor, and more particularly, to a method for forming a sensing diffusion region for improving light sensitivity of an image sensor.
일반적으로, 이미지센서라 함은 광학 영상(Optical image)을 전기 신호로 변환시키는 반도체소자로서, 이중 전하결합소자(CCD : Charge Coupled Device)는 개개의 MOS(Metal-Oxide-Silicon) 커패시터가 서로 매우 근접한 위치에 있으면서 전하 캐리어가 커패시터에 저장되고 이송되는 소자이며, CMOS(Complementary MOS; 이하 CMOS) 이미지센서는 제어회로(Control circuit) 및 신호처리회로(Signal processing circuit)를 주변회로로 사용하는 CMOS 기술을 이용하여 화소수만큼 MOS트랜지스터를 만들고 이것을 이용하여 차례차례 출력(Output)을 검출하는 스위칭 방식을 채용하는 소자이다.In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. In a double charge coupled device (CCD), individual metal-oxide-silicon (MOS) capacitors are very different from each other. A device in which charge carriers are stored and transported in a capacitor while being located in close proximity, and CMOS (Complementary MOS) image sensor is a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. Is a device that employs a switching method that creates MOS transistors by the number of pixels and sequentially detects the output using them.
이러한 다양한 이미지센서를 제조함에 있어서, 이미지센서의 감광도(Photo sensitivity)를 증가시키기 위한 노력들이 진행되고 있는 바, 그 중 하나가 집광기술이다. 예컨대, CMOS 이미지센서는 빛을 감지하는 포토다이오드와 감지된 빛을 전기적 신호로 처리하여 데이터화하는 CMOS 로직회로부분으로 구성되어 있는 바, 광감도를 높이기 위해서는 전체 이미지센서 면적에서 포토다이오드의 면적이 차지하는 비율(이를 통상 Fill Factor"라 한다)을 크게 하려는 노력이 진행되고 있다.In the manufacture of such various image sensors, efforts are being made to increase the photo sensitivity of the image sensor, one of which is a condensing technology. For example, a CMOS image sensor is composed of a photodiode for detecting light and a portion of a CMOS logic circuit for processing the detected light into an electrical signal to make data. To increase light sensitivity, the ratio of the photodiode to the total image sensor area is increased. Efforts have been made to increase (usually referred to as Fill Factor).
도 1은 종래기술에 따른 이미지센서를 도시한 평면도이며, 도 2는 단면도이다.1 is a plan view showing an image sensor according to the prior art, Figure 2 is a cross-sectional view.
도 1을 참조하면, 종래의 이미지센서는 기판(도시하지 않음)에 포토다이오드(이하 PD라 함)가 형성되어 있으며, PD와 이격되는 위치의 기판(도시하지 않음)에 센싱확산영역(이하 FD라 함)이 형성되어 있으며, PD와 FD의 일단에 각각 오버랩되어 온-오프 동작을 통해 PD로 부터의 광신호를 FD로 전달하는 게이트전극(예컨대, 트랜스퍼 게이트, 이하 G라 함)이 형성되어 있다. 또한, FD에 콘택되며 G에 일정 간격 'A'를 갖고 배치된 후속 금속배선과의 연결을 위한 플러그(P)를 포함하는 바, 도 1은 FD에 금속배선 연결을 위한 플러그(P) 형성 공정이 완료된 상태를 나타낸다.Referring to FIG. 1, in the conventional image sensor, a photodiode (hereinafter referred to as PD) is formed on a substrate (not shown), and a sensing diffusion region (hereinafter referred to as FD) is disposed on a substrate (not shown) at a position spaced apart from the PD. A gate electrode (for example, a transfer gate, hereinafter referred to as G) that overlaps one end of the PD and the FD, and transfers the optical signal from the PD to the FD through an on-off operation. have. In addition, it comprises a plug (P) for connecting to the subsequent metal wiring contacted to the FD and arranged at a predetermined interval 'A' in G, Figure 1 is a process for forming a plug (P) for connecting the metal wiring to the FD This indicates a completed state.
전술한 도 1을 보다 상세하게 도시한 도 2를 참조하면, 기판(10) 상에 국부적으로 필드절연막(11)이 형성되어 있으며, 필드절연막(11)과 인접하는 기판(10) 하부에 이온주입 등을 통해 형성된 PD가 형성되어 있으며, 폴리실리콘막(12)과 텅스텐막(13)이 적층된 구조의 게이트전극(G)이 PD에 인접하여 기판(10) 상에 형성되어 있으며, 게이트전극(G)은 그 측면에 산화막 계열의 스페이서(14)를 구비한다. 이웃하는 게이트전극(G) 사이의 기판(10) 표면으로 부터 내부로 확장된 FD(15)가 형성되어 있으며, 게이트전극(G) 및 PD 상부에는 절연막(16)이 형성되어 있으며, 절연막(16)을 관통하여 전술한 FD(15)에 콘택된 플러그(P, 17)가 형성되어 있으며, 플러그(17) 상에는 금속배선(18)이 형성되어 있다.Referring to FIG. 2, which is described in more detail with reference to FIG. 1, a field insulating film 11 is locally formed on a substrate 10, and ion implantation is performed under the substrate 10 adjacent to the field insulating film 11. PD is formed through, and the like, a gate electrode G having a structure in which the polysilicon film 12 and the tungsten film 13 is stacked is formed on the substrate 10 adjacent to the PD, the gate electrode ( G) has an oxide film spacer 14 on its side. An FD 15 extending inwardly from the surface of the substrate 10 between neighboring gate electrodes G is formed, an insulating film 16 is formed on the gate electrode G and the PD, and an insulating film 16 Plugs P and 17 contacted to the above-described FD 15 are formed, and metal wires 18 are formed on the plug 17.
여기서, 기판(10)은 고농도인 P++ 층 및 P-Epi층이 적층된 것을 이용하는 바, 이하 도면의 간략화를 위해 기판(10)으로 칭한다.Here, the substrate 10 is a layer in which a high concentration of the P + + layer and the P-Epi layer is laminated, referred to as the substrate 10 for the sake of simplicity of the drawings.
전술한 바와 같이, PD는 P형의 기판 하부에 형성된 N형의 포토다이오드영역(이하 n-영역이라 함)과, 기판 표면으로부터 n-영역으로 확장되어 형성된 P형의 포토다이오드영역(이하 P0라 함)을 포함하며, FD는 기판 표면으로부터 하부로 확장되어 형성된 고농도의 N형(n+)이다.As described above, the PD is an N-type photodiode region (hereinafter referred to as n-region) formed under the P-type substrate, and a P-type photodiode region (hereinafter referred to as P0) formed extending from the substrate surface to the n-region. FD is a high concentration N-type (n +) formed extending downward from the substrate surface.
한편, 도시된 바와 같이 도 1과 동일하게 게이트전극(G)은 플러그(P, 17)와 'A'의 간격만큼 이격되어 있는 바와 같이, FD에 콘택된 플러그(17) 형성시 게이트전극(G)과 플러그(17) 간의 간격을 'A'와 같이 일정하게 유지하여야 한다. 이는 플러그 형성을 위한 콘택 식각시 게이트전극(G)에 영향을 미칠 수 있기 때문이며, FD의 경우 그 용량(Capacitance)이 작아질수록 전체적인 이미지센서의 광감도를 향상시킬 수 있기 때문에 이러한 FD의 면적 및 단위화소 이외의 영역 즉, 주변영역의 사이즈를 줄여야 한다. 그러나 전술한 종래의 이미지센서에서는 공정 마진을 확보하기 위해 게이트전극(G)과 FD의 콘택 플러그(17) 사이에 일정한 간격을 확보해야 하므로 더이상의 면적 감소는 힘든 상황이다. 따라서, 이미지센서의 광감도를 향상시키는 것에도 한계점에 다다르고 있다.As shown in FIG. 1, as shown in FIG. 1, the gate electrode G is spaced apart from the plugs P and 17 by an interval of 'A', and the gate electrode G is formed when the plug 17 contacted to the FD is formed. ) And the plug 17 should be kept constant as 'A'. This is because the gate electrode G may be affected during the etching of the contact for forming the plug. In the case of the FD, the light sensitivity of the overall image sensor may be improved as the capacitance thereof decreases, so that the area and the unit of the FD may be improved. The size of the area other than the pixel, that is, the peripheral area should be reduced. However, in the above-described conventional image sensor, it is difficult to further reduce the area because a certain distance must be secured between the gate electrode G and the contact plug 17 of the FD in order to secure a process margin. Therefore, the limit is also reached to improve the light sensitivity of the image sensor.
상기와 같은 종래 기술의 문제점을 해결하기 위해 제안된 본 발명은, 광감도를 향상시킬 수 있는 이미지센서 제조 방법을 제공하는데 그 목적이 있다.The present invention proposed to solve the problems of the prior art as described above, an object thereof is to provide a method for manufacturing an image sensor that can improve the light sensitivity.
도 1은 종래기술에 따른 이미지센서를 도시한 평면도,1 is a plan view showing an image sensor according to the prior art,
도 2는 종래기술에 따른 이미지센서를 도시한 단면도,2 is a cross-sectional view showing an image sensor according to the prior art,
도 3a 내지 도 3c는 본 발명의 일실시예에 따른 이미지센서 제조 공정을 도시한 단면도,3A to 3C are cross-sectional views illustrating an image sensor manufacturing process according to an embodiment of the present invention;
도 4는 본 발명에 따라 형성된 이미지센서를 도시한 평면도.4 is a plan view showing an image sensor formed according to the present invention;
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
20 : 기판21 : 필드절연막20: substrate 21: field insulating film
22 : 폴리실리콘막23 : 텅스텐실리사이드막22 polysilicon film 23 tungsten silicide film
24 : 하드마스크 절연막25 : 스페이서24 hard mask insulating film 25 spacer
26: 센싱확산영역27 : 절연막26: sensing diffusion region 27: insulating film
28 : 플러그29 : 금속배선28: plug 29: metal wiring
PD : 포토다이오드PD: Photodiode
상기 목적을 달성하기 위하여 본 발명은, 포토다이오드와 이웃하는 게이트전극 및 상기 이웃하는 게이트전극 사이의 기판 하부에 형성된 센싱확산영역을 포함하는 전체 구조 상부에 절연막을 형성하는 단계; 및 상기 절연막을 관통하여 상기 이웃하는 게이트전극에 동시에 접하며 상기 센싱확산영역에 콘택된 플러그를 형성하는 단계를 포함하는 이미지센서 제조 방법을 제공한다.In order to achieve the above object, the present invention includes forming an insulating film on an entire structure including a photodiode and a neighboring gate electrode and a sensing diffusion region formed under the substrate between the neighboring gate electrode; And forming a plug penetrating through the insulating layer and in contact with the neighboring gate electrode at the same time and contacting the sensing diffusion region.
본 발명은 게이트전극의 전도성 물질 위에 질화막 또는 산화질화막을 일정 두께로 증착하여 게이트전극 패턴을 정의한 후, 스페이서 형성시 기존의 산화막 대신 질화막 또는 산화질화막을 사용하여 후속 센싱확산영역의 금속배선을 위한 콘택 형성 공정에서 게이트전극의 손실을 방지하도로 하여 게이트전극 패턴과 플러그 간의 간격을 최소로 하며, 이에 따라 센싱확산영역의 면적을 감소시켜 그 용량을 감소시킴으로써 이미지센서의 광감도를 향상시키는 것을 기술적 특징으로 한다.The present invention defines a gate electrode pattern by depositing a nitride film or an oxynitride film to a predetermined thickness on the conductive material of the gate electrode, and then using a nitride film or an oxynitride film instead of the conventional oxide film when forming a spacer, for the metal wiring of the subsequent sensing diffusion region. In order to prevent the loss of the gate electrode in the forming process, the gap between the gate electrode pattern and the plug is minimized, thereby reducing the area of the sensing diffusion region and reducing its capacity, thereby improving the light sensitivity of the image sensor. do.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 설명하는 바, 도 3a 내지 도 3c는 본 발명의 일실시예에 따른 이미지센서 제조 공정을 도시한 단면도이며, 도 4는 전술한 본 발명의 공정 적용에 따라 형성된 이미지센서를 도시한 평면도이다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. 3A to 3C are cross-sectional views illustrating an image sensor manufacturing process according to an embodiment of the present invention, and FIG. 4 is a plan view illustrating an image sensor formed according to the process application of the present invention described above.
먼저, 도 3a에 도시된 바와 같이 필드영역과 활성영역(Active region)을 정의하기 위한 소자분리를 위하여 고농도 P++층과 P-Epi층이 적층된 기판(20) 상에국부적으로 필드절연막(21)을 형성한 다음, 폴리실리콘막(22)과 텅스텐실리사이드막(23)을 차례로 형성한 다음, 그 상부에 후속 콘택 형성에 따른 게이트전극의 손실을 방지하기 위해 식각내성이 약한 산화막을 제외한 질화막 또는 산화질화막을 이용하여 하드마스크 절연막(24)을 적층구조로 형성한 다음, 게이트전극을 정의하기 위한 일련의 사진식각 공정을 통해 폴리실리콘막(22)과 텅스텐실리사이드막(23) 및 하드마스크 절연막(24)으로 이루어진 게이트전극 패턴을 형성하는 바, 게이트전극 패턴을 필드절연막(21)과 이격되어 있다.First, as shown in FIG. 3A, a field insulating film 21 is locally formed on a substrate 20 on which a high concentration P ++ layer and a P-Epi layer are stacked for device isolation to define a field region and an active region. Next, the polysilicon layer 22 and the tungsten silicide layer 23 are sequentially formed, and then nitride or oxide except for the oxide layer having weak etching resistance to prevent loss of the gate electrode due to subsequent contact formation thereon. After forming the hard mask insulating film 24 using a nitride film in a stacked structure, a polysilicon film 22, a tungsten silicide film 23, and a hard mask insulating film 24 through a series of photolithography processes for defining a gate electrode. The gate electrode pattern is formed of (), and the gate electrode pattern is spaced apart from the field insulating film 21.
한편, 이후 형성되는 게이트전극 패턴 특히, 트랜스퍼 트랜지스터의 일측면에 근접하여 형성되는 저전압 베리드 포토다이오드의 도핑 프로파일(Doping profile)이 전하운송효율(Charge transfer efficiency)을 결정하게 되므로, 게이트전극 패턴의 두꼐를 충분히 두껍게 하여 저전압 베리드 포토다이오드의 P0영역과 n-영역을 각각 형성하기 위한 P0이온주입과 n-이온주입을 게이트전극 패턴의 일측면에서 자기정렬할 수 있도록 하는데, 만일 게이트전극의 두꼐를 충분히 두껍게 하지 않으면, 고에너지 N형 이온주입시 도펀트인 인(P31)이 게이트전극을 뚫고 들어가 자기정렬이 이루어지지 않으므로 전하운송효율은 저감된다.On the other hand, since the doping profile of the gate electrode pattern formed later, in particular, the low voltage buried photodiode formed near one side of the transfer transistor determines the charge transfer efficiency, The thickness of the gate electrode pattern can be self-aligned so that the P0 ion implantation and the n-ion implantation for forming the P0 region and the n- region of the low voltage buried photodiode are sufficiently thickened on one side of the gate electrode pattern. If the thickness is not sufficiently thick, phosphorus (P 31 ), which is a dopant during high-energy N-type ion implantation, penetrates through the gate electrode and does not undergo self-alignment, thereby reducing charge transport efficiency.
따라서, 게이트전극의 두께는 두껍게 하는 것이 바람직하며 특히, 전술한 하드마스크 절연막(24)은1000Å ∼ 4000Å의 두께로 형성한다.Therefore, it is preferable to increase the thickness of the gate electrode, and in particular, the above-described hard mask insulating film 24 is formed to a thickness of 1000 kPa to 4000 kPa .
이어서, 저전압 베리드 포토다이오드의 저농도 n-영역을 형성하기 위해 이온주입 마스크(도시하지 않음)를 형성하고 고에너지 및 저농도의 N- 이온주입을 실시하여, 게이트전극 패턴의 일측에 정렬된 PD용 n-영역을 형성한다.Subsequently, an ion implantation mask (not shown) is formed to form a low concentration n-region of the low voltage buried photodiode, and high energy and low concentration N-ion implantation are performed to form PDs aligned on one side of the gate electrode pattern. forms an n-region.
다음으로, 도 3b에 도시된 바와 같이 n-영역을 형성하기 위해 사용된 이온주입 마스크를 제거한 다음, 다시 P0 이온주입을 위한 마스크 패턴(도시하지 않음)을 형성하고 P0 이온주입을 실시하여 n-영역 상의 기판(20) 표면으로 n-영역을 확장된 P0영역을 형성함으로써, P(P-Epi)-N(n-)-P(P0)로 이루어진 PD가 형성된다.Next, as shown in FIG. 3B, the ion implantation mask used to form the n-region is removed, and then a mask pattern (not shown) for P0 ion implantation is formed again and P0 ion implantation is performed to perform n- By forming the P0 region in which the n-region is extended to the surface of the substrate 20 on the region, a PD composed of P (P-Epi) -N (n-)-P (P0) is formed.
야기서, P0영역과 하부의 P-Epi층이 전기적으로 충분히 연결될 수 있는 통로가 제공됨으로써, 5V 이하의 저전압에서 P0영역과 P-Epi층은 서로 등전위를 갖게되어 n-영역은 약 1.2V ~ 2.8V에서 완전 공핍이 가능하다. 만약, 저에너지 P0도핑영역이 P에피층과 전기적으로 연결되지 않으면, 저전압 베리드 포토 다이오드는 정상적으로 동작하지 않고 단순한 PN 접합과 같이 동작할 것이다.Thus, by providing a path through which the P0 region and the lower P-Epi layer can be sufficiently electrically connected, the P0 region and the P-Epi layer have an equipotential with each other at a low voltage of 5V or less, and the n-region is about 1.2V to ~. Full depletion is possible at 2.8V. If the low energy P0 doped region is not electrically connected to the P epi layer, the low voltage buried photodiode will not function normally but will act like a simple PN junction.
이어서, 게이트전극 패턴을 포함한 전체 구조의 프로파일을 따라 질화막 또는 산화질화막 등을 이용하여 스페이서용 절연막을 증착한 후, 전면식각을 통해 게이트전극 패턴 측벽에 스페이서(25)를 형성하는 바, 스페이서(25)는 후속 콘택 식각 후에도 잔류할 수 있도록 적당한 두꼐로 형성한다.Subsequently, an insulating film for a spacer is deposited using a nitride film, an oxynitride film, or the like along the profile of the entire structure including the gate electrode pattern, and then the spacer 25 is formed on the sidewall of the gate electrode pattern through front etching. ) Is formed to a suitable thickness so that it remains after subsequent contact etching.
이어서, LDD이온주입을 실시하여 게이트전극 사이에 n+영역 즉, 센싱확산영역(FD)을 형성하는 바, FD는 이웃하는 게이트전극의 스페이서와 동시에 오버랩되도록 한다.Subsequently, LDD ion implantation is performed to form an n + region, that is, a sensing diffusion region FD, between the gate electrodes, so that the FD overlaps with the spacers of the neighboring gate electrodes.
이어서, 절연막(26)을 두껍게 증착한다.Next, the insulating film 26 is thickly deposited.
다음으로, 도 3c에 도시된 바와 같이 절연막(27)을 선택적으로 식각하여 게이트전극 사이의 센싱확산영역(26) 표면을 노출시키는 콘택홀(도시하지 않음)을 형성하는 바, 이 때 이웃하는 두 게이트전극 사이의 절연막(27) 모두 제거되도로 하는 바, 이 때 이웃하는 게이트전극의 스페이서(25)에서 식각이 멈추며 그 표면이 노출된다.Next, as shown in FIG. 3C, the insulating layer 27 is selectively etched to form a contact hole (not shown) exposing the surface of the sensing diffusion region 26 between the gate electrodes. All of the insulating layers 27 between the gate electrodes are removed. At this time, the etching stops at the spacers 25 of the neighboring gate electrodes and the surface thereof is exposed.
이어서, 콘택홀을 충분히 매립하도록 텅스텐 또는 그외의 전도성 물질을 형성한 후, 절연막(27) 표면이 노출될 때까지 평탄화 공정을 실시하여 FD에 콘택된 플러그(28)를 형성하는 바, 도 4는 전술한 플러그(28)가 형성된 이미지센서의 평면도이다.Subsequently, after forming tungsten or other conductive material to sufficiently fill the contact hole, a planarization process is performed until the surface of the insulating film 27 is exposed to form the plug 28 contacted with the FD. The top view of the image sensor in which the plug 28 mentioned above is formed.
즉, 도 4에 도시된 바와 같이 PD와 FD가 이격되어 배치되어 있으며, PD의 일단과 FD의 일단에 각각 오버랩되어 온-오프 동작을 통해 광신호를 FD로 전달하는 게이트전극(G)이 배치되어 있는 바, 여기서 이웃하는 두 게이트전극(G)은 서로 FD에 물리적으로 접하는 형태로 전술한 종래와 같이 일정한 간격을 갖지 않는다.That is, as shown in FIG. 4, the PD and the FD are spaced apart from each other, and the gate electrode G for transmitting the optical signal to the FD through an on-off operation is overlapped with one end of the PD and one end of the FD, respectively. In this case, the two neighboring gate electrodes G do not have a constant distance as described above in the form of physically contacting each other with the FD.
따라서, 하부의 FD 형성시 그 면적을 보다 작게 할 수 있어 그 용얄을 감소시킬 수 있게 된다. 한편 도시된 'B'의 폭을 최대한 넓게 함으로써 플러그(P)와 FD의 접촉면적을 넓힘으로써 콘택저항 또한 감소시킬 수 있다.Therefore, when forming the lower FD, the area can be made smaller, and the molten metal can be reduced. Meanwhile, the contact resistance may also be reduced by increasing the contact area between the plug P and the FD by increasing the width of 'B' as shown.
이어서, 플러그(28) 상에 금속배선(29)을 형성한다.Subsequently, a metal wiring 29 is formed on the plug 28.
전술한 본 발명은, 게이트전극 상부에 하드마스크와 그 측벽에 스페이서를 각각 질화막 등의 식각 내성이 있는 물질을 사용하며, 센싱확산영역을 금속배선 콘택 플러그 형성시 플러그가 이웃하는 게이트전극에 각각 접하도록 함으로써 그 하부의 센싱확산영역의 면적 또한 감소시킬 수 있어, 이에 따라 이미지센서의 광감도를 향상시킬 수 있음을 실시예를 통해 알아 보았다.According to the present invention, a hard mask on the gate electrode and a spacer on a sidewall of the spacer are used to etch resistant materials such as a nitride film, respectively, and the sensing diffusion region is in contact with a gate electrode adjacent to each other when the metal wiring contact plug is formed. By reducing the area of the sensing diffusion area of the lower part by doing so, it was found through the embodiment that the light sensitivity of the image sensor can be improved accordingly.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은, 광감도를 향상시킬 수 있어, 궁극적으로 이미지센서의 성능을 크게 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.The present invention described above can improve the photosensitivity, and can be expected to have an excellent effect that can ultimately greatly improve the performance of the image sensor.
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KR100539253B1 (en) * | 2004-03-10 | 2005-12-27 | 삼성전자주식회사 | CMOS image device with contact studs comprising of poly silicon |
KR100729735B1 (en) * | 2005-12-22 | 2007-06-20 | 매그나칩 반도체 유한회사 | Method of manufacturing image sensor |
KR100757654B1 (en) * | 2006-05-26 | 2007-09-10 | 매그나칩 반도체 유한회사 | Cmos image sensor and method for manufacturing the same |
CN108565272A (en) * | 2018-01-30 | 2018-09-21 | 德淮半导体有限公司 | Imaging sensor, forming method and its working method |
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KR100539253B1 (en) * | 2004-03-10 | 2005-12-27 | 삼성전자주식회사 | CMOS image device with contact studs comprising of poly silicon |
KR100729735B1 (en) * | 2005-12-22 | 2007-06-20 | 매그나칩 반도체 유한회사 | Method of manufacturing image sensor |
KR100757654B1 (en) * | 2006-05-26 | 2007-09-10 | 매그나칩 반도체 유한회사 | Cmos image sensor and method for manufacturing the same |
US8154055B2 (en) | 2006-05-26 | 2012-04-10 | Intellectual Ventures Ii Llc | CMOS image sensor and method for fabricating the same |
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