KR20030049002A - Multi chip package - Google Patents

Abstract

PURPOSE: A multi chip package and a fabricating method thereof are provided to mount a plurality of chips without increasing the area of the multi chip package by attaching a semiconductor chip to the package while the semiconductor chip is vertically installed. CONSTITUTION: A package board(100) includes a plurality of pads. A plurality of semiconductor chips(300) are attached to the upper surface of the package board wherein the sawing surface of the semiconductor chip comes in contact with the surface of the package board. A plurality of leads electrically connect the semiconductor chips with the outside, arranged in the back surface of the package board. Conductive pads are exposed to the sawing surface of the semiconductor chip.

Description

Multi chip package and its manufacturing method {Multi chip package}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a multi-chip package capable of loading a plurality of chips.

As the capacity and speed of electronic devices including personal portable electronic products have increased and the size has also been miniaturized, semiconductor packages have also become larger, faster, and lighter and smaller.

Currently, in order to reduce the size of the package, a ball grid array package (BGA) using balls instead of pins and a chip scale package that can be assembled within a range that does not significantly exceed the chip size (CSP) has been proposed. In addition, a multi chip package has been proposed in which a plurality of chips are mounted in one package so as to perform a plurality of functions as one package while increasing the density mounted per unit semiconductor package.

1 is a plan view schematically illustrating a conventional multi-chip package, and FIG. 2 is a cross-sectional view of the conventional multi-chip package. Referring to FIGS. 1 and 2, the conventional multi-chip package will be described.

1 and 2, a lead frame 15 having a plurality of leads 10 arranged at regular equal intervals on an edge surface is prepared. The package substrate 20 is attached to the lead frame 15 by the adhesive 18a. The first chip 25 and the second chip 28 are attached to the predetermined portion of the substrate 20 by the adhesive 18b. Here, the first chip 25 and the second chip 28 may be spaced apart from each other by a predetermined distance as shown in FIG. 1, or may be stacked. In this case, the first pads 20a are arranged at regular intervals on the upper edge of the package substrate 20, and the second pads 25 and 28 surround the first and second chips 25 and 28 inside the first pad 20a. The pads 20b are arranged. In addition, electrical pads 25a and 28b are provided at upper edges of the first and second chips 25 and 28, respectively.

The pads 25a and 28a of the chips 25 and 28 are first bonded to the second pad 20b by wires 29 and are electrically connected to the second pad 30b in the substrate. ) Is bonded by the lead 10 and the wire 29.

However, in the case of mounting two chips as described above, the package can be implemented to a certain extent. However, when three or more chips are multi-mounted, the package area is greatly increased, so that the thin and small size of the package cannot be achieved.

In addition, conventional multi-chip packages connect the pads with the wires. At this time, since the wire 29 is a thin and long wire, the longer the length of the wire 29, the higher the inductance, the poor the speed characteristics and noise characteristics of the semiconductor package.

In addition, in another conventional method, a structure in which semiconductor chips are stacked to miniaturize a semiconductor package has been proposed, which will be described with reference to FIG. 3.

As shown in FIG. 3, the first chip 33 and the second chip 35 are sequentially stacked and attached on the package substrate 31. Here, the first chip 33, the package substrate 31, the second chip 35, and the first chip 33 are bonded by an adhesive 37. In addition, since the pads 33a and 35a are arranged at both edges of the upper ends of the respective chips 33 and 35, and the first chip 33 disposed below is larger in size than the second chip 35, The pad 33a of the first chip 33 is exposed. In addition, pads 31a and 31b to be connected to the pads 33a and 35a of the first and second chips 33 and 35 are formed at the edges of the package substrate 31.

The pads 33a and 35b of the first and second chips 33 and 35 are bonded to the pads 31a and 31b of the package substrate 31 by the wire 39. The wire-bonded semiconductor chips 33 and 35 are sealed by the resin 40 to complete the package body 42. Here, reference numeral 43 is a solder ball 43 for electrically connecting the chips 33 and 35 to the outside.

This stacked package also has a problem that the inductance is still increased because the pads are connected by the wires 39. In addition, when the second package 35 is attached to the stacked package, a stress may be applied to the lower first chip 33 by a load, thereby causing a problem such as a crack.

Accordingly, the technical problem to be achieved by the present invention is to provide a multi-chip package capable of mounting multiple chips without increasing the size.

Another object of the present invention is to provide a multichip package capable of improving speed characteristics and noise characteristics.

In addition, another technical problem to be achieved by the present invention is to provide a multi-chip package that can prevent cracks when the chip is attached.

1 is a plan view showing a conventional multi-chip package.

2 is a cross-sectional view of the multichip package of FIG. 1.

3 is a cross-sectional view illustrating a conventional stacked multi-chip package.

4 is a cross-sectional view of a multichip package according to the present invention.

5 is a cross-sectional view of a semiconductor chip according to the present invention.

(Explanation of symbols for the main parts of the drawing)

100-Package Board 130-Conductive Bump

200-semiconductor substrate 210-pad or pad metal wiring on chip

300-semiconductor chip

Other objects and novel features as well as the objects of the present invention will become apparent from the description of the specification and the accompanying drawings.

In order to achieve the above technical problem to be achieved, the multi-chip package of the present invention, the package substrate having a plurality of pads, and the surface sawed on top of the package substrate is attached so as to contact the package substrate A plurality of semiconductor chips, and a plurality of leads arranged on the back of the package substrate, and a plurality of leads for electrically connecting the chips to the outside, the conductive pad is exposed on the sawed surface of the semiconductor chip.

The semiconductor chip is attached so that the conductive pad exposed on the sawed surface and the pad of the package substrate surface are in electrical contact. In addition, the semiconductor chip and the package substrate are adhered by conductive bumps, and preferably the conductive bumps are interposed between pads of the chip and pads of the package substrate. As the conductive bumps, Ag glass may be used.

In addition, the method for manufacturing a multi-chip package according to the present invention provides a semiconductor substrate in which a scribe line is limited and a semiconductor element is formed. Subsequently, a pad metal wiring is formed on the semiconductor substrate so that an end thereof extends into the scribe line. Then, the scribe line of the semiconductor substrate is sawed to form a semiconductor chip having exposed pad metal wiring on a sawing surface. Next, the semiconductor chip is attached onto a package substrate having a plurality of pads such that the sawed surface of the semiconductor substrate contacts the package substrate surface.

At this time, in the step of attaching the semiconductor chip, it is preferable to attach so that the pad exposed on the sawed surface of the semiconductor chip and the pad of the package substrate. In addition, in the attaching of the semiconductor chip, the semiconductor chip is bonded between the pad of the semiconductor chip and the pad of the package substrate through a conductive bump.

According to the present invention, after the pad of the chip is formed to be exposed to the sawing surface, the sawing surface is attached so as to contact the package substrate surface. That is, since the semiconductor chip is attached in a vertical position, many chips can be mounted without increasing the area. In addition, since the pad of the chip and the pad of the package substrate are directly contacted by bumps, wire bonding is not required, thereby reducing speed degradation and noise generation. In addition, since the chip and the chip are not stacked, the load generated when the chip is stacked on the chip is not generated. Accordingly, problems such as cracks do not occur.

(Example)

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or semiconductor substrate, a layer may exist in direct contact with the other layer or semiconductor substrate, or a third layer therebetween. Can be done.

4 is a cross-sectional view of a multi-chip package according to the present invention, Figure 5 is a cross-sectional view of a semiconductor chip according to the present invention.

First, referring to FIG. 4, a multi-chip package according to an exemplary embodiment of the present invention is provided with a plurality of semiconductor chips 300 attached to one surface of a package substrate 100. At this time, the plurality of chips 300 are attached so that the sawed surface 220 is in contact with the package substrate 100 surface, and the conductive pad 210 is exposed on the sawed surface 220 of the chip 300. It is. In addition, the plurality of chips 300 are spaced at regular intervals, and pads (not shown) are formed on portions of the package substrate 100 attached to the pads 210 of the chips 300. Here, the plurality of chips 300 and the package substrate 100 are attached by an adhesive, for example, a conductive bump 130 such as Ag glass, and preferably, the pad 210 and the package of the chip 300 are packaged. Conductive bumps 130 are interposed between pads (not shown) of the substrate 100.

In addition, a plurality of leads 150 are formed on the rear surface of the package substrate 100. In this case, the lead 150 is for electrically connecting the external electrical terminal and the package. For example, a pin or a ball may be used.

The semiconductor chip 300 and the multi-chip package are manufactured by the following method.

Referring to FIG. 5, multilayer insulating layers 202 and 204 and multilayer wirings 206 are formed on a semiconductor substrate 200 on which scribe lines SC are defined. At this time, the figure schematically shows the internal structure of the semiconductor device, and shows a simplified illustration of the multilayer wiring. Subsequently, the pad metal wiring 210 is formed to be connected to a predetermined portion of the multilayer wiring. In this case, the pad metal line 210 is formed to extend to the scribe line SC area. Thereafter, the insulating film 212 is formed to cover the pad metal wiring 210, and then the semiconductor substrate 200 is sawed for each unit chip. At this time, sawing cuts the part defined by the scribe line SC of the semiconductor substrate 100 with a diamond saw, etc. as is known. Then, since the pad metal wiring 210 is exposed on the sawed surface 220 of the semiconductor chip 300, the exposed pad metal wiring 210 becomes the conductive pad 210 of the present invention. Thereafter, as described above, the sawed surface 220 is attached so as to contact the surface of the package substrate 100, thereby completing the package of the present invention.

As described in detail above, according to the present invention, after the pad of the chip is formed to be exposed to the sawing surface, the sawing surface is attached to contact the package substrate surface. That is, since the semiconductor chip is attached in a vertical position, many chips can be mounted without increasing the area.

In addition, since the pad of the chip and the pad of the package substrate are directly contacted by bumps, wire bonding is not required, thereby reducing speed degradation and noise generation.

In addition, since the chip and the chip are not stacked, the load occurring when the chip is stacked on the chip is not generated. Accordingly, problems such as cracks do not occur.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

Claims (9)

A package substrate having a plurality of pads; A plurality of semiconductor chips attached to the top surface of the package substrate so as to contact the package substrate surface; And Is arranged on the back of the package substrate, and has a plurality of leads for electrically connecting the chips to the outside, And a conductive pad is exposed on the sawed surface of the semiconductor chip. The method of claim 1, The semiconductor chip is attached to the conductive pad exposed to the sawed surface and the pad on the surface of the package substrate is attached to the electrical contact. The method according to claim 1 or 2, And the semiconductor chip and the package substrate are bonded by conductive bumps. The multi-chip package of claim 3, wherein the conductive bumps are interposed between pads of the chip and pads of a package substrate. The method of claim 4, wherein The conductive bump is a multi-chip package, characterized in that the Ag glass. Providing a semiconductor substrate on which a scribe line is defined and in which a semiconductor element is formed; Forming a pad metal line on the semiconductor substrate such that an end portion extends into a scribe line; Sawing a scribe line of the semiconductor substrate to form a semiconductor chip having exposed pad metal wiring on a sawing surface; And Attaching a semiconductor chip on a package substrate having a plurality of pads such that the sawed surface of the semiconductor substrate is in contact with the package substrate surface. The method of claim 6, Attaching the semiconductor chip, And attaching the pad exposed to the sawed surface of the semiconductor chip to be in contact with the pad of the package substrate. The method of claim 7, wherein Attaching the semiconductor chip, And bonding conductive bumps between the pads of the semiconductor chip and the pads of the package substrate. The method of claim 8, The conductive bump is Ag glass manufacturing method of the multi-chip package, characterized in that.