KR20030048202A - a method for forming of dual gate of semiconductor device - Google Patents
a method for forming of dual gate of semiconductor device Download PDFInfo
- Publication number
- KR20030048202A KR20030048202A KR1020010078069A KR20010078069A KR20030048202A KR 20030048202 A KR20030048202 A KR 20030048202A KR 1020010078069 A KR1020010078069 A KR 1020010078069A KR 20010078069 A KR20010078069 A KR 20010078069A KR 20030048202 A KR20030048202 A KR 20030048202A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- conductivity type
- gate
- intrinsic semiconductor
- conductive
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 28
- 230000009977 dual effect Effects 0.000 title abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000002513 implantation Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 24
- 229920005591 polysilicon Polymers 0.000 abstract description 24
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052796 boron Inorganic materials 0.000 abstract description 12
- 238000001764 infiltration Methods 0.000 abstract 1
- 230000008595 infiltration Effects 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 21
- 238000010438 heat treatment Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 230000035515 penetration Effects 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
Abstract
Description
본 발명은 반도체 소자의 듀얼 게이트 형성방법에 관한 것으로, 특히 보론(Boron)이 게이트 산화막내로 침투하는 것을 방지하여 안정된 듀얼 게이트를 구현한 반도체 소자의 듀얼 게이트 형성방법에 관한 것이다.The present invention relates to a method of forming a dual gate of a semiconductor device, and more particularly, to a method of forming a dual gate of a semiconductor device in which boron is prevented from penetrating into a gate oxide layer to realize a stable dual gate.
디자인 루울 감소에 따라 워드라인 저항 감소와 함께 베리드 채널 PMOS의 후속 열처리 효과에 의한 TED에 의해 펀치 마진(margin)이 점차 부족하여 표면 채널 PMOS 개발이 필요하게 되었다.As the design ruin decreases, the punch margin is gradually lacking due to TED due to the subsequent heat treatment effect of the buried channel PMOS along with the decrease of the word line resistance, which requires the development of the surface channel PMOS.
우수한 표면 채널 PMOS의 개발을 위해서는 이온주입된 폴리를 구현하기 위해 주입된 보론이 게이트 산화막내로 침투되는 것을 억제하여야 한다. 그러나 디바이스가 감소됨에 따라 듀얼 게이트를 사용하는 디바이스에서의 보론 침투 현상을 해결하기 위해 후속 열 공정을 감소시키거나 NO 게이트를 사용하고 있는 실정이다.In order to develop an excellent surface channel PMOS, the implanted boron must be suppressed from penetrating into the gate oxide to realize the ion implanted poly. However, as the number of devices decreases, subsequent thermal processes have been reduced or NO gates have been used to address boron penetration in devices using dual gates.
이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 듀얼 게이트 형성방법에 대하여 설명하기로 한다.Hereinafter, a method of forming a dual gate of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1e는 종래의 반도체 소자의 듀얼 게이트 형성방법을 나타낸 공정 단면도이다.1A to 1E are cross-sectional views illustrating a method of forming a dual gate of a conventional semiconductor device.
도 1a에 도시한 바와 같이 반도체 기판(10)에 선택적으로 p형 웰(11)과 n형 웰(12)을 형성한 후, 활성영역을 정의하여 소자 격리영역으로 이용되는 필드 산화막(13)을 형성한다. 그리고 활성영역에 게이트 산화막(14)을 형성한 후, 상기 게이트 산화막(14)상에 진성 폴리 실리콘층(15)을 형성한다.As shown in FIG. 1A, after the p-type well 11 and the n-type well 12 are selectively formed in the semiconductor substrate 10, the field oxide film 13 used as the device isolation region is defined by defining an active region. Form. After the gate oxide layer 14 is formed in the active region, an intrinsic polysilicon layer 15 is formed on the gate oxide layer 14.
도 1b에 도시한 바와 같이 상기 진성 폴리 실리콘층(15)상에 제 1 포토레지스트(16)를 증착하고, 노광 및 현상공정을 이용하여 상기 n형 웰(12)영역에만 남도록 패터닝한 후, 상기 패터닝된 제 1 포토레지스트(16)를 마스크로 하여 P 또는 As 불순물 이온주입을 통해 도핑된 n+폴리 실리콘층(15a)을 형성한다.As shown in FIG. 1B, a first photoresist 16 is deposited on the intrinsic polysilicon layer 15, and patterned so as to remain only in the n-type well 12 region using an exposure and development process. The doped n + polysilicon layer 15a is formed using P or As impurity ion implantation using the patterned first photoresist 16 as a mask.
도 1c에 도시한 바와 같이 상기 제 1 포토레지스트(16)를 제거한 후, n+폴리 실리콘층(15a)을 포함한 전면에 제 2 포토레지스트(17)를 증착하고, 노광 및 현상공정을 이용하여 상기 p형 웰(11) 영역에만 남도록 패터닝한다. 그리고 상기 패터닝된 제 2 포토레지스트(17)를 마스크로 이용하여 B 불순물 이온주입을 통해 도핑된 p+폴리 실리콘층(15b)을 형성한다.After removing the first photoresist 16 as shown in FIG. 1C, the second photoresist 17 is deposited on the entire surface including the n + polysilicon layer 15a, and the exposure and development processes are performed. The patterning is performed so that only the p-type well 11 region remains. In addition, the doped p + polysilicon layer 15b is formed by implanting B impurity ions using the patterned second photoresist 17 as a mask.
도 1d에 도시한 바와 같이 상기 제 2 포토레지스트(17)를 제거한 후, 전면에 제 3 포토레지스트(18)를 증착하고, 노광 및 현상공정을 이용하여 패터닝한다.After removing the second photoresist 17 as shown in FIG. 1D, the third photoresist 18 is deposited on the entire surface, and patterned using an exposure and development process.
그리고 상기 패터닝된 제 3 포토레지스트(18)를 마스크로 하여 상기 게이트 산화막(14)과 n+, p+폴리 실리콘층(15a)(15b)을 선택적으로 제거하여 NMOS 게이트 전극(20a)과, PMOS 게이트 전극(20b)을 형성한다.The gate oxide layer 14 and the n + , p + polysilicon layers 15a and 15b are selectively removed by using the patterned third photoresist 18 as a mask to form an NMOS gate electrode 20a and a PMOS. The gate electrode 20b is formed.
도 1e에 도시한 바와 같이 상기 패터닝된 제 3 포토레지스트(18)를 제거한 후, 상기 NMOS 게이트 전극(20a)과 PMOS 게이트 전극(20b)을 마스크로 하여 불순물 이온주입을 통해 소오스/드레인 영역(19)을 형성한 후, 열처리 공정을 실시한다.이때, 상기 PMOS 게이트 전극(20b)에 함유된 B 불순물이 상기 게이트 산화막(14)으로 침투되는 현상이 발생한다.After removing the patterned third photoresist 18 as shown in FIG. 1E, source / drain regions 19 are formed through impurity ion implantation using the NMOS gate electrode 20a and the PMOS gate electrode 20b as masks. ), And then a heat treatment process is performed. At this time, a phenomenon in which B impurities contained in the PMOS gate electrode 20b penetrates into the gate oxide film 14 occurs.
따라서, 보론 침투 현상을 억제하기 위해 NO 게이트를 사용하거나 질소가스 분위기에서 열처리를 통해 보론을 억제한다.Therefore, the boron is suppressed by using an NO gate to suppress boron penetration or by heat treatment in a nitrogen gas atmosphere.
즉, 종래와 같은 반도체 소자의 듀얼 게이트 형성방법에 있어서는 트랜지스터의 후속 열처리 공정시 PMOS 게이트 전극에 함유된 보론 불순물이 게이트 산화막으로 침투하여 소자의 특성을 유발하는 문제점이 있었다.That is, in the conventional method of forming a dual gate of a semiconductor device, a boron impurity contained in the PMOS gate electrode penetrates into the gate oxide layer in a subsequent heat treatment process of the transistor, causing a problem of device characteristics.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 다층으로 폴리 실리콘층을 증착하여 게이트 산화막으로 보론 침투를 억제시켜 안정화된 듀얼 게이트를 형성할 수 있는 반도체 소자의 듀얼 게이트 형성방법을 제공하는데 그 목적이 있다.The present invention provides a dual gate formation method of a semiconductor device capable of forming a stabilized dual gate by suppressing boron penetration into a gate oxide film by depositing a polysilicon layer in multiple layers to solve the above problems. There is a purpose.
도 1a 내지 도 1e는 종래의 반도체 소자의 듀얼 게이트 형성방법을 나타낸 공정 단면도1A to 1E are cross-sectional views illustrating a method of forming a dual gate of a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명의 일실시예에 따른 반도체 소자의 듀얼 게이트 형성방법을 나타낸 공정 단면도2A through 2E are cross-sectional views illustrating a method of forming a dual gate of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
100 : 반도체 기판 101 : p형 웰100 semiconductor substrate 101 p-type well
102 : n형 웰 103 : 필드 산화막102: n-type well 103: field oxide film
104 : 게이트 산화막 105 : 제 1 진성 폴리 실리콘층104: gate oxide film 105: first intrinsic polysilicon layer
106 : 제 2 진성 폴리 실리콘층 107 : 제 3 진성 폴리 실리콘층106: second intrinsic polysilicon layer 107: third intrinsic polysilicon layer
108 : 제 1 포토레지스트 109a : n+폴리 실리콘층108: first photoresist 109a: n + polysilicon layer
109b : p+폴리 실리콘층 110 : 제 2 포토레지스트109b: p + polysilicon layer 110: second photoresist
111 : 평탄화용 절연막 112 : 질화막111 insulating film for planarization 112 nitride film
113 : 제 3 포토레지스트 114 : 소오스/드레인 영역113: third photoresist 114 source / drain regions
120a : NMOS 게이트 전극 120b : PMOS 게이트 전극120a: NMOS gate electrode 120b: PMOS gate electrode
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 듀얼 게이트 형성방법은 반도체 기판에 선택적으로 제 1 도전형 웰 및 제 2 도전형 웰을 형성하는 단계와, 상기 제 1 도전형 웰 및 제 2 도전형 웰 계면의 반도체 기판상에 필드 절연막을 형성하고 상기 반도체 기판 표면에 게이트 절연막을 형성하는 단계와, 상기 결과물 상부에 다층의 진성 반도체층을 증착하는 단계와, 상기 제 1 도전형 웰상측의 다층 진성 반도체층에 제 2 도전형 불순물을 주입하여 제 1 게이트 전극을 형성하는 단계와, 상기 제 2 도전형 웰 상측의 다층 진성 반도체층에 제 1 도전형 불순물 주입하여 제 2 게이트 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.The dual gate forming method of the semiconductor device of the present invention for achieving the above object comprises the steps of selectively forming a first conductivity type well and a second conductivity type well in the semiconductor substrate, the first conductivity type well and second Forming a field insulating film on the semiconductor substrate of the conductive well interface and forming a gate insulating film on the surface of the semiconductor substrate, depositing a multilayered intrinsic semiconductor layer on the resultant, Forming a first gate electrode by injecting a second conductivity type impurity into the multilayer intrinsic semiconductor layer, and forming a second gate electrode by implanting a first conductivity type impurity into the multilayer intrinsic semiconductor layer above the second conductivity type well Characterized in that it comprises a step.
또한, 상기 제 1 도전형 웰은 p형이고, 상기 제 2 도전형 웰은 n형인 것이 바람직하다.In addition, it is preferable that the first conductivity type well is p-type and the second conductivity type well is n-type.
또한, 상기 다층 진성폴리층의 두께는 1800∼2000Å인 것이 바람직하다.Moreover, it is preferable that the thickness of the said multilayer intrinsic polylayer is 1800-2000 micrometers.
또한, 상기 다층 진성폴리층의 증착온도는 500∼530℃이고, 압력은 200∼400mT이며, SiH4를 100∼200sccm을 사용하는 것이 바람직하다.In addition, the deposition temperature of the multilayered intrinsic polylayer is 500 to 530 캜, the pressure is 200 to 400mT, it is preferable to use SiH 4 100-200sccm.
또한, 상기 제 1 도전형 게이트 전극과 제 2 도전형 게이트 전극상에 질화막을 형성하는 것이 바람직하다.In addition, it is preferable to form a nitride film on the first conductive gate electrode and the second conductive gate electrode.
또한, 상기 제 2 도전형 불순물은 BF2이고, 주입량 영역은 1E14∼1E16 ion/㎤이며, 주입시 사용되는 에너지는 5∼30KeV인 것이 바람직하다.The second conductivity type impurity is BF 2 , the implantation region is 1E14 to 1E16 ions / cm 3, and the energy used during implantation is 5 to 30 KeV.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 듀얼 게이트 형성방법에 대하여 보다 상세히 설명하기로 한다.Hereinafter, a method of forming a dual gate of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2는 본 발명의 일실시예에 따른 반도체 소자의 듀얼 게이트 형성방법을 나타낸 공정 단면도이다.2A through 2 are cross-sectional views illustrating a method of forming a dual gate of a semiconductor device in accordance with an embodiment of the present invention.
도 2a에 도시한 바와 같이 반도체 기판(100)에 선택적으로 p형 웰(101)과 n형 웰(102)을 형성한 후, 활성영역을 정의하여 소자 격리영역으로 이용되는 필드 산화막(103)을 형성한다. 그리고 상기 활성영역에 게이트 산화막(104)을 형성한 후, 상기 게이트 산화막(104)상에 제 1, 제 2, 제 3 진성 폴리 실리콘층(105)(106)(107)을 차례로 형성한다. 이때, 상기 제 1 진성 폴리실리콘층(105)의 두께는 450∼500Å, 상기 제 2 진성 폴리 실리콘층(106)의 두께는 450∼500Å이고, 상기 제 3 진성 폴리 실리콘층(107)의 두께는 900∼1000Å이다.As shown in FIG. 2A, after the p-type well 101 and the n-type well 102 are selectively formed in the semiconductor substrate 100, the field oxide film 103 used as the device isolation region is defined by defining an active region. Form. After the gate oxide film 104 is formed in the active region, first, second and third intrinsic polysilicon layers 105, 106 and 107 are sequentially formed on the gate oxide film 104. In this case, the thickness of the first intrinsic polysilicon layer 105 is 450 to 500 kPa, the thickness of the second intrinsic polysilicon layer 106 is 450 to 500 kPa, and the thickness of the third intrinsic polysilicon layer 107 is 900-1000 Hz.
그리고 상기 제 1, 제 2, 제 3 진성 폴리 실리콘층(105)(106)(107)의 증착온도는 500∼530℃이고, 압력은 200∼400mT이며, SiH4를 100∼200sccm을 사용한다.And it uses the first, second, and third intrinsic poly is the deposition temperature, and 500~530 ℃ pressure of the silicon layer 105, 106, 107 200~400mT, 100~200sccm the SiH 4.
또한, 상기 제 1, 제 2, 제 3 진성 폴리 실리콘층(105)(106)(107)을 증착한후, 전체 균일도를 3% 이하로 컨트롤하고, 그레인 사이즈(Grain Size)가 후속 열처리 후 0.05∼0.1㎛이다. 즉, 장비의 로딩 존 효과(Loading Zone Effect)를 최소화시킬 수 있다.In addition, after depositing the first, second and third intrinsic polysilicon layers 105, 106 and 107, the overall uniformity is controlled to 3% or less, and the grain size is 0.05 after the subsequent heat treatment. It is -0.1 micrometer. That is, the loading zone effect of the equipment can be minimized.
도 2b에 도시한 바와 같이 상기 제 1, 제 2, 제 3 진성 폴리 실리콘층(105)(106)(107)상에 제 1 포토레지스트(108)를 증착하고, 노광 및 현상공정을 이용하여 상기 n형 웰(101)영역에만 남도록 패터닝한 후, 상기 패터닝된 제 1 포토레지스트(108)를 마스크로 하여 P 또는 As 불순물 이온주입을 통해 도핑된 n+폴리 실리콘층(109a)을 형성한다.As shown in FIG. 2B, a first photoresist 108 is deposited on the first, second, and third intrinsic polysilicon layers 105, 106, and 107, and the exposure and development processes are used to form the first photoresist 108. After patterning so as to remain only in the n-type well 101 region, the n + polysilicon layer 109a is formed using P or As impurity ion implantation using the patterned first photoresist 108 as a mask.
도 2c에 도시한 바와 같이 상기 제 1 포토레지스트(108)를 제거한 후, n+폴리 실리콘층(109a)을 포함한 전면에 제 2 포토레지스트(110)를 증착하고, 노광 및 현상공정을 이용하여 상기 p형 웰(102) 영역에만 남도록 패터닝한다. 그리고 상기 패터닝된 제 2 포토레지스트(110)를 마스크로 이용하여 보론(B) 불순물 또는 BF2이온주입을 통해 도핑된 p+폴리 실리콘층(109b)을 형성한다. 이때, 상기 불순물 주입량 영역은 1E14∼1E16 ion/㎤이며, 주입시 사용되는 에너지는 5∼30KeV이다.After removing the first photoresist 108 as illustrated in FIG. 2C, the second photoresist 110 is deposited on the entire surface including the n + polysilicon layer 109a, and the exposure and development processes are performed. Patterned so that it remains only in the p-type well 102 region. In addition, the doped p + polysilicon layer 109b is formed using boron (B) impurities or BF 2 ion implantation using the patterned second photoresist 110 as a mask. At this time, the impurity implantation region is 1E14 to 1E16 ion / cm 3, and the energy used during implantation is 5 to 30 KeV.
한편, 상기 제 1, 제 2, 제 3 진성 폴리 실리콘층(105)(106)(107)의 계면과 계면 사이에서 보론을 분리하여 전체적인 보론 침투를 방지할 수 있다.Meanwhile, boron may be separated between an interface between the first, second, and third intrinsic polysilicon layers 105, 106, and 107 to prevent total boron penetration.
도 2d에 도시한 바와 같이 상기 제 2 포토레지스트(110)를 제거한 후, 상기 결과물 상부에 평탄화용 절연막(111) 및 하드 마스크용 절연막(113)을 증착한다. 이때, 상기 평탄화용 절연막(111)은 PE-TEOS(Plasma Enhanced-Tetra Ethyl Ortho Silicate)이다.After removing the second photoresist 110 as shown in FIG. 2D, a planarization insulating film 111 and a hard mask insulating film 113 are deposited on the resultant. In this case, the planarization insulating layer 111 is PE-TEOS (Plasma Enhanced-Tetra Ethyl Ortho Silicate).
그리고 상기 결과물 상부에 제 3 포토레지스트(113)를 증착하고, 노광 및 현상공정을 이용하여 패터닝한 후, 상기 패터닝된 제 3 포토레지스트(113)를 마스크로 하여 상기 평탄화용 절연막(111), 하드 마스크용 절연막(112) 그리고 상기 게이트 산화막(104)과 n+, p+폴리 실리콘층(109a)(109b)을 선택적으로 제거하여 NMOS, PMOS 게이트 전극(120a)(120b)을 형성한다.The third photoresist 113 is deposited on the resultant, and patterned by using an exposure and development process, and then the planarization insulating layer 111 and hard are formed using the patterned third photoresist 113 as a mask. The mask insulating film 112 and the gate oxide film 104 and the n + , p + polysilicon layers 109a and 109b are selectively removed to form NMOS and PMOS gate electrodes 120a and 120b.
이어서, 도 2e에 도시한 바와 같이 상기 NMOS, PMOS 게이트 전극(120a)(120b)을 마스크로 하여 불순물 이온주입을 통해 소오스/드레인 영역(114)을 형성한 후, 열처리 공정을 실시한다.Subsequently, as shown in FIG. 2E, the source / drain regions 114 are formed by impurity ion implantation using the NMOS and PMOS gate electrodes 120a and 120b as masks, and then a heat treatment process is performed.
이상에서 설명한 바와 같이 본 발명의 반도체 소자의 듀얼 게이트 형성방법에 의하면, PMOS 게이트 전극 형성시 발생하는 게이트 산화막내로 보론 침투를 억제하여 소자 특성을 향상시킬 수 있다.As described above, according to the dual gate forming method of the semiconductor device of the present invention, it is possible to suppress boron penetration into the gate oxide film generated when the PMOS gate electrode is formed, thereby improving device characteristics.
또한, 안정화된 듀얼 게이트 형성을 형성하므로 각각의 트랜지스터간의 문턱전압을 안정화시킬 수 있고, 문턱전압의 변화를 방지할 수 있다.In addition, since the stabilized dual gate formation is formed, it is possible to stabilize the threshold voltage between each transistor and to prevent the change of the threshold voltage.
그리고 다층으로 증착된 폴리층을 이용하므로 기타 다른 물질을 사용하는데서 발생하는 이종물질에 대한 저항력을 증가시킬 수 있다.In addition, the use of poly-layers deposited in multiple layers can increase the resistance to heterogeneous materials generated by using other materials.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010078069A KR20030048202A (en) | 2001-12-11 | 2001-12-11 | a method for forming of dual gate of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010078069A KR20030048202A (en) | 2001-12-11 | 2001-12-11 | a method for forming of dual gate of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20030048202A true KR20030048202A (en) | 2003-06-19 |
Family
ID=29574157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010078069A KR20030048202A (en) | 2001-12-11 | 2001-12-11 | a method for forming of dual gate of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20030048202A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1012744A (en) * | 1996-06-24 | 1998-01-16 | Sony Corp | Manufacture of semiconductor device |
| KR19990083170A (en) * | 1998-04-14 | 1999-11-25 | 이데이 노부유끼 | Semiconductor device and method of manufacturing the same |
-
2001
- 2001-12-11 KR KR1020010078069A patent/KR20030048202A/en not_active Application Discontinuation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1012744A (en) * | 1996-06-24 | 1998-01-16 | Sony Corp | Manufacture of semiconductor device |
| KR19990083170A (en) * | 1998-04-14 | 1999-11-25 | 이데이 노부유끼 | Semiconductor device and method of manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20020066137A (en) | Cmos transistor having germanium-contained policrystalline silicon gate and method of forming the same | |
| US7790588B2 (en) | Dual gate of semiconductor device capable of forming a layer doped in high concentration over a recessed portion of substrate for forming dual gate with recess channel structure and method for manufacturing the same | |
| KR20060134500A (en) | Isolation layer and method of manufacturing using the same, apparatus for a semiconductor device having the isolation layer and method of manufacturing using the same | |
| TW200532856A (en) | Spacer approach for CMOS device | |
| US7186631B2 (en) | Method for manufacturing a semiconductor device | |
| KR20030048202A (en) | a method for forming of dual gate of semiconductor device | |
| KR20000050588A (en) | Method for forming dual gate of semiconductor device | |
| KR20070002872A (en) | Semiconductor device with dual polysilicon gate and method for manufacturing the same | |
| KR20080082132A (en) | Method for manufacturing dual poly gate of semiconductor device | |
| KR100915165B1 (en) | Method for fabricating semiconductor device | |
| KR20010065915A (en) | A method for forming dual-implanted polysilicon gate of semiconductor device | |
| KR20010045183A (en) | Method for manufacturing dual gate electrodes of CMOS device | |
| KR20080060339A (en) | Method for fabricating dual poly gate in semiconductor device | |
| KR100311177B1 (en) | A method of fabricating semiconductor device | |
| KR20050101030A (en) | Method for forming a transistor in a semiconductor device | |
| KR100333356B1 (en) | A method of fabricating a semiconductor device | |
| KR100271801B1 (en) | Manufacturing Method of Semiconductor Device | |
| KR100473734B1 (en) | Method of manufacturing a transistor in a semiconductor device | |
| KR20010004934A (en) | Method of manufacturing semiconductor device | |
| KR20060037776A (en) | Method for fabricating semiconductor device with gate spacer by ald | |
| KR100618807B1 (en) | Method for manufacturing a semiconductor device having dual gate poly structure available self-aligned contact and gate layers structure thereof | |
| KR100636912B1 (en) | Method for forming dual gate of semiconductor device | |
| KR100357173B1 (en) | Method for manufacturing thin film transistor | |
| KR100842747B1 (en) | Method for fabricating dual poly gate in semiconductor device | |
| KR20080056918A (en) | Method for fabricating dual poly gate in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |