KR20030047032A - A method for forming a semiconductor device - Google Patents
A method for forming a semiconductor device Download PDFInfo
- Publication number
- KR20030047032A KR20030047032A KR1020010077407A KR20010077407A KR20030047032A KR 20030047032 A KR20030047032 A KR 20030047032A KR 1020010077407 A KR1020010077407 A KR 1020010077407A KR 20010077407 A KR20010077407 A KR 20010077407A KR 20030047032 A KR20030047032 A KR 20030047032A
- Authority
- KR
- South Korea
- Prior art keywords
- gate electrode
- etching
- forming
- nitride film
- oxide film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 150000004767 nitrides Chemical class 0.000 claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 27
- 125000006850 spacer group Chemical group 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- ADDWXBZCQABCGO-UHFFFAOYSA-N titanium(iii) phosphide Chemical compound [Ti]#P ADDWXBZCQABCGO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
본 발명은 반도체소자의 형성방법에 관한 것으로, 특히 반도체 기판의 손상없이 게이트 전극의 양측에 절연막 스페이서를 형성하되, 후속공정으로 실시되는 살리사이드 공정을 용이하게 하고 그에 따른 소자의 특성을 향상시킬 수 있도록 하는 방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device, and in particular, to form insulating film spacers on both sides of the gate electrode without damaging the semiconductor substrate, to facilitate the salicide process to be performed in a subsequent process and thereby improve the characteristics of the device It's about how to do that.
반도체소자의 제조공정중 게이트전극 측벽의 절연막 스페이서 형성공정은,핫 캐리어 효과를 감소시키기 위한 LDD 구조의 소오스/드레인 영역을 형성할 때 이용되며, 샐리사이드 공정에서 반도체 기판 및 게이트 전극 상부의 폴리실리콘막 상부에만 선택적으로 성장시켜 게이트와 반도체 기판의 단락을 방지하는데 이용된다.The insulating film spacer forming step of the gate electrode sidewall during the manufacturing process of the semiconductor device is used to form the source / drain regions of the LDD structure to reduce the hot carrier effect, and the polysilicon on the semiconductor substrate and the gate electrode in the salicide process It selectively grows only on top of the film and is used to prevent short circuit between the gate and the semiconductor substrate.
도 1 은 종래기술에 따른 반도체소자의 형성방법을 도시한 단면도이다.1 is a cross-sectional view showing a method of forming a semiconductor device according to the prior art.
도 1를 참조하면, 상기 반도체기판(10) 상에 활성영역을 정의하는 소자분리막(도시안됨)을 형성한다.Referring to FIG. 1, an isolation layer (not shown) defining an active region is formed on the semiconductor substrate 10.
그리고, 상기 반도체기판(10) 표면에 게이트산화막(20) 및 게이트전극용 도전층을 증착하고 이를 게이트전극 마스크(도시안됨)를 이용한 사진식각공정으로 식각하여 게이트전극(30)을 형성한다.The gate oxide layer 20 and the conductive layer for the gate electrode are deposited on the surface of the semiconductor substrate 10 and etched by a photolithography process using a gate electrode mask (not shown) to form the gate electrode 30.
그리고, 상기 게이트전극(30) 마스크로 사용하는 이온주입공정으로 상기 반도체기판(10)에 저농도의 불순물 접합영역(도시안됨)을 형성한다.A low concentration impurity junction region (not shown) is formed in the semiconductor substrate 10 by an ion implantation process used as a mask of the gate electrode 30.
그리고, 상기 게이트전극(30) 측벽에 절연막 스페이서(40)를 형성한다.The insulating layer spacer 40 is formed on sidewalls of the gate electrode 30.
이때, 상기 절연막 스페이서(40)는 전체표면상부에 절연막을 증착하고 이를 CF4/CHF3/Ar 가스의 조합을 이용하여 식각함으로써 형성한 것이다.In this case, the insulating film spacer 40 is formed by depositing an insulating film on the entire surface and etching it using a combination of CF 4 / CHF 3 / Ar gas.
그 다음, 상기 절연막 스페이서(40)를 마스크로 하여 상기 반도체기판(10)에 고농도의 불순물을 이온주입하여 고농도의 불순물 접합영역(도시안됨)을 형성함으로써 트랜지스터를 형성한다.Next, a transistor is formed by ion implanting a high concentration of impurities into the semiconductor substrate 10 using the insulating film spacer 40 as a mask to form a high concentration of impurity junction regions (not shown).
후속공정으로 상기 고농도의 불순물 접합영역이 형성된 반도체기판(10)과 상기 게이트전극(30) 상부를 포함한 전체표면상부에 Ti 이나 Co 와 같은 고융점금속을 일정두께 증착하고 열처리하여 실리사이드층을 형성하는 살리사이드 공정으로 반도체소자의 고속 동작을 가능하게 한다.In the subsequent process, a silicide layer is formed by depositing and heat-treating a high melting point metal such as Ti or Co on the entire surface including the semiconductor substrate 10 having the high concentration impurity junction region and the upper portion of the gate electrode 30. The salicide process enables high speed operation of the semiconductor device.
상기한 바와같이 종래기술에 따른 반도체소자의 형성방법은, 살리사이드의 소오스 금속으로 코발트를 사용하는 경우 티타늄을 사용하는 경우에 비하여 게이트 선폭에 대한 저항 의존도가 거의 없으나 살리사이드 형성 후에 적용되는 열공정에 따라 게이트 선폭에 대해 저항 의존도를 가지게 된다. 따라서 샐리사이드 형성 이후에 적용되는 열공정의 온도를 감소시키면 되나 이것은 소자의 특성에 미치는 영향이 너무 크다는 문제점이 있었다.As described above, the method of forming a semiconductor device according to the related art has a little resistance dependence on the gate line width when cobalt is used as the source metal of salicide, compared with the case of using titanium, but a thermal process applied after salicide formation. As a result, there is a resistance dependence on the gate line width. Therefore, the temperature of the thermal process applied after forming the salicide may be reduced, but this has a problem in that the influence on the device characteristics is too large.
본 발명은 이러한 문제를 해결하기 위해, 활성영역의 반도체기판 손상을 방지하는 동시에 살리사이드 면적을 증가시켜 동일한 게이트전극의 선폭에서 살리사이드 저항을 감소시키고 그에 따른 소자의 열적 안정성을 향상시키는 반도체소자의 형성방법을 제공하는데 그 목적이 있다.In order to solve this problem, the present invention provides a semiconductor device that prevents damage to the semiconductor substrate in the active region and simultaneously increases the salicide area to reduce the salicide resistance at the line width of the same gate electrode, thereby improving the thermal stability of the device. The purpose is to provide a formation method.
도 1 은 종래 기술에 따른 반도체소자의 형성방법을 도시한 단면도.1 is a cross-sectional view showing a method of forming a semiconductor device according to the prior art.
도 2a 내지 도 2f는 본 발명에 따른 반도체소자의 형성방법을 도시한 단면도.2A to 2F are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.
< 도면의 주요부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>
10,100 : 반도체기판20,110 : 게이트산화막10,100 semiconductor substrate 20,110 gate oxide film
30 : 게이트전극40 : 절연막 스페이서30 gate electrode 40 insulating film spacer
120 : 게이트전극130 : 산화막120 gate electrode 130 oxide film
140 : 질화막140: nitride film
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 형성방법은,In order to achieve the above object, a method of forming a semiconductor device according to the present invention,
반도체기판 상에 게이트전극을 형성하는 공정과,Forming a gate electrode on the semiconductor substrate;
상기 게이트전극을 포함한 전체표면상부에 산화막과 질화막을 일정두께 형성하는 공정과,Forming a predetermined thickness of an oxide film and a nitride film on the entire surface including the gate electrode;
상기 산화막/질화막을 3 단계로 이방성식각하여 절연막 스페이서를 형성하는 공정을 포함하는 것과,Anisotropically etching the oxide film / nitride film in three steps to form an insulating film spacer;
상기 산화막은 150 ∼ 200 Å 의 두께인 것과,The oxide film has a thickness of 150 to 200 kPa,
상기 질화막은 500 ∼ 900 Å 의 두께인 것과,The nitride film has a thickness of 500 to 900 kPa,
상기 질화막을 상기 질화막 두께의 소정 비율만큼 식각하는 단계는 상기 질화막 두께의 70 내지 80% 식각하는 공정인 것과,Etching the nitride film by a predetermined ratio of the thickness of the nitride film is a process of etching 70 to 80% of the thickness of the nitride film,
상기 3 단계 식각공정은, 상기 질화막을 소정두께 식각하는 제1단계, 상기 게이트전극과 같은 높이로 산화막/질화막을 식각하는 제2단계, 상기 게이트전극보다 소정두께 낮게 산화막/질화막을 식각하는 제3단계로 실시하되,In the three-step etching process, a first step of etching the nitride film by a predetermined thickness, a second step of etching an oxide film / nitride film to the same height as the gate electrode, and a third step of etching the oxide film / nitride film by a predetermined thickness lower than the gate electrode Step by step,
상기 제1단계는 100 ∼ 150 mTorr 의 압력, 700 ∼ 900 W 의 소오스 전력, CF4및 Ar 의 혼합 가스를 이용하여 실시하고,The first step is performed using a pressure of 100 to 150 mTorr, a source power of 700 to 900 W, a mixed gas of CF 4 and Ar,
상기 제2단계는, 10 ∼ 15 mTorr 의 압력, 300 내지 400W의 소오스 전력, CHF3및 O2의 혼합 가스를 이용하여 실시하고,The second step is carried out using a pressure of 10 to 15 mTorr, a source power of 300 to 400 W, a mixed gas of CHF 3 and O 2 ,
상기 제3단계는 상기 게이트전극보다 300 ∼ 500 Å 만큼 낮게 100 ∼ 150 mTorr 의 압력, 300 ∼ 500 W 의 소오스 전력, CHF3및 Ar 의 혼합 가스를 이용하여 실시하는 것을 특징으로 한다.The third step may be performed by using a pressure of 100 to 150 mTorr, a source power of 300 to 500 W, and a mixed gas of CHF 3 and Ar, which is 300 to 500 kW lower than that of the gate electrode.
한편, 본 발명의 원리는,On the other hand, the principle of the present invention,
반도체기판 상부에 게이트전극을 형성하고 전체표면상부에 산화막과 질화막 적층구조를 형성하고 이들을 식각하여 적층구조의 절연막 스페이서를 형성하되,A gate electrode is formed on the semiconductor substrate, and an oxide film and a nitride film stacked structure are formed on the entire surface of the semiconductor substrate, and the insulating layers are formed by etching them.
상기 절연막 스페이서 형성공정을 삼단계로 실시하여 절연막 스페이서의 높이를 상기 게이트전극 보다 300 ∼ 500 Å 정도 낮게 형성함으로써 게이트전극 상에 형성되는 살리사이드층의 면적을 크게 함으로써 소자의 동작 특성을 향상시킬 수 있도록 하며, 소자의 열적 안정성을 향상시키는 것이다.By forming the insulating film spacer in three steps, the height of the insulating film spacer is 300 to 500 Å lower than that of the gate electrode, thereby increasing the area of the salicide layer formed on the gate electrode, thereby improving operation characteristics of the device. It is to improve the thermal stability of the device.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 따른 반도체소자의 형성방법을 도시한 단면도이다.2A to 2F are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.
도 2a를 참조하면, 반도체 기판(100) 상에 게이트 산화막(110) 및 폴리실리콘막을 순차적으로 형성한다.Referring to FIG. 2A, a gate oxide film 110 and a polysilicon film are sequentially formed on the semiconductor substrate 100.
그리고, 게이트전극 마스크를 이용한 사진식각공정으로 패터닝하여 게이트전극(120)을 형성한다.The gate electrode 120 is formed by patterning the photolithography process using the gate electrode mask.
그리고, 상기 게이트전극(120)을 마스크로 하여 상기 반도체기판(100)에 저농도의 불순물을 이온주입함으로써 저농도의 불순물 접합영역(도시안됨)을 형성한다.A low concentration of impurity junction regions (not shown) are formed by ion implanting impurities of low concentration into the semiconductor substrate 100 using the gate electrode 120 as a mask.
도 2b를 참조하면, 전면에 균일한 두께의 산화막(130)을 형성한다.Referring to FIG. 2B, an oxide film 130 having a uniform thickness is formed on the entire surface.
이때, 상기 산화막(130)은 150 내지 200 Å 의 두께로 형성한다.In this case, the oxide film 130 is formed to a thickness of 150 to 200 Å.
도 2c를 참조하면, 전면에 500 ∼ 900 Å 두께의 질화막(140)을 형성한다.Referring to FIG. 2C, a nitride film 140 having a thickness of 500 to 900 mm is formed on the entire surface.
도 2d, 도 2e 및 도 2f 를 참조하면, 상기 질화막(140)과 산화막(130)을 3단계로 식각하여 상기 게이트전극(120) 측벽에 산화막/질화막 적층구조의 절연막 스페이서를 형성한다.2D, 2E, and 2F, the nitride film 140 and the oxide film 130 are etched in three steps to form an insulating film spacer having an oxide film / nitride layer structure on the sidewall of the gate electrode 120.
여기서, 상기 3 단계 식각공정은 다음과 같다.Here, the three-step etching process is as follows.
제1단계, 상기 질화막(140)을 전체두께의 70 내지 80% 정도 식각한다. 이때,상기 질화막(140)의 식각공정은 플라즈마를 이용한 이방성 식각공정으로 실시한다. 상기 이방성식각공정은 100 ∼ 150 mTorr 의 압력, 700 ∼ 900 W 의 소오스 전력, CF4및 Ar 의 혼합가스를 이용하여 실시한다. 여기서, 상기 질화막(140)을 부분 식각하는 이유는 CF4및 Ar 의 혼합가스를 이용하는 경우 적절한 절연막 스페이서 프로파일을 형성할 수 있으나, 절연막 스페이서 하부 영역의 식각 속도가 다른 영역에 비해 빠르므로 식각 종료 후에 산화막이 남아 있는 경우라도 절연막 스페이서 하부의 반도체 기판이 손상되기 때문이다.In the first step, the nitride film 140 is etched about 70 to 80% of the total thickness. At this time, the etching process of the nitride film 140 is performed by an anisotropic etching process using a plasma. The anisotropic etching process is performed using a pressure of 100 to 150 mTorr, a source power of 700 to 900 W, and a mixed gas of CF 4 and Ar. Here, the reason for the partial etching of the nitride film 140 may be to form an appropriate insulating film spacer profile when using a mixed gas of CF 4 and Ar, but since the etching speed of the lower region of the insulating film spacer is faster than other regions, This is because even if the oxide film remains, the semiconductor substrate under the insulating film spacer is damaged.
제2단계, 남아있는 상기 질화막(140) 및 산화막(130)을 식각하여 상기 게이트 전극의 측벽에 절연막 스페이서를 형성함으로써 절연막 스페이서의 높이와 게이트전극(120)의 높이가 거의 동일하게 유지된다. 이때, 상기 산화막(130)은 산화막 두께의 소정 비율만큼만 식각한다. 이때의 공정조건은 절연막 스페이서 하부의 반도체 기판 손상을 방지하기 위하여 질화막(140)과 산화막(130)의 선택비가 높은 공정을 이용하여야 하므로 CHF3와 O2의 혼합 가스를 이용하여 CHF3와 O2의 혼합 가스를 10 ∼ 15 sccm 정도로 유지하면서 300 ∼ 400 W 의 소오스 전력으로 한다.In the second step, the remaining nitride film 140 and the oxide film 130 are etched to form insulating film spacers on the sidewalls of the gate electrode, whereby the height of the insulating film spacer and the height of the gate electrode 120 are maintained to be substantially the same. In this case, the oxide film 130 is etched only by a predetermined ratio of the oxide film thickness. The process conditions are the nitride film 140, and therefore should use the ratio of high process selection of the oxide film 130 using the mixed gas of CHF 3 and O 2 CHF 3 and O 2 in order to prevent the semiconductor substrate, damage to the lower insulating spacer To a source power of 300 to 400 W while maintaining a mixed gas of about 10 to 15 sccm.
제3단계, 산화막/질화막 적층구조의 절연막 스페이서와 제2단계에서 남은 산화막(130)을 식각한다. 이때, 상기 산화막(130)은 전부 식각하고 절연막 스페이서는 상부로부터 300 ∼ 500 Å 식각한다.The insulating film spacer having the oxide film / nitride film stacked structure and the oxide film 130 remaining in the second step are etched. At this time, all of the oxide film 130 is etched and the insulating film spacer is etched 300 to 500 로부터 from the top.
이때, 상기 제3단계 식각공정은 CHF3와 Ar 의 혼합 가스를 이용하여 실시하되, 100 ∼ 150 mTorr 의 압력, 300 ∼ 500 W 의 전력으로 실시한다.In this case, the third step etching process is performed using a mixed gas of CHF 3 and Ar, but the pressure of 100 ~ 150 mTorr, 300 ~ 500W power.
여기서, 상기 CHF3와 Ar 의 혼합 가스를 사용하는 이유는, 질화막과 산화막에 대한 식각선택비는 매우 낮으나 반도체 기판 과의 식각선택비가 매우 높으므로 반도체 기판에 거의 손상을 주지 않고 절연막 스페이서만 식각할 수 있기 때문이다.Here, the reason why the mixed gas of CHF 3 and Ar is used is that the etching selectivity with respect to the nitride film and the oxide film is very low, but the etching selectivity with the semiconductor substrate is very high, so that only the insulating film spacer can be etched with little damage to the semiconductor substrate. Because it can.
후속공정으로 상기 게이트전극(120) 및 절연막 스페이서를 마스크로 하여 상기 반도체기판(100)에 고농도의 불순물을 이온주입하여 고농도의 불순물 접합영역(도시안됨)을 형성하고, 전체표면상부에 고융점금속인 티타늄이나 코발트를 형성한 다음 열처리하여 상기 반도체기판의 불순물 접합영역과 게이트전극 표면에 살리사이드층을 형성한다.In a subsequent process, a high concentration of impurity junction regions (not shown) are formed by implanting high concentrations of impurities into the semiconductor substrate 100 using the gate electrode 120 and the insulating layer spacers as masks, and a high melting point metal is formed on the entire surface. Phosphorus titanium or cobalt is formed and then heat-treated to form a salicide layer on the impurity junction region and the gate electrode surface of the semiconductor substrate.
이때, 상기 절연막 스페이서의 높이가 낮아 게이트전극(120)의 노출된 면이 많으므로 같은 게이트전극 선폭에 살리사이드층 많이 형성되어 소자의 동작특성을 향상시키고 소자의 열적 특성을 안정화시킨다.In this case, since the height of the insulating layer spacer is low, many exposed surfaces of the gate electrode 120 are formed, so that many salicide layers are formed on the same gate electrode line width, thereby improving the operation characteristics of the device and stabilizing the thermal properties of the device.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 형성방법은, 게이트전극 측벽에 산화막/질화막 적층구조의 스페이서를 형성하되, 게이트전극 높이보다 소정두께 낮게 형성함으로써 게이트전극 상에 형성되는 살리사이드층 면적을 증가시켜 소자의 동작 특성을 향상시키는 동시에 열적 안정성을 향상시키고 그에 따르 소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, in the method of forming a semiconductor device according to the present invention, a salicide layer is formed on a gate electrode by forming a spacer having an oxide / nitride stacked structure on the sidewall of the gate electrode, and forming a spacer having a predetermined thickness lower than the height of the gate electrode. Increasing the area improves the operating characteristics of the device while at the same time providing the effect of improving thermal stability and thus enabling high integration of the device.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010077407A KR20030047032A (en) | 2001-12-07 | 2001-12-07 | A method for forming a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010077407A KR20030047032A (en) | 2001-12-07 | 2001-12-07 | A method for forming a semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20030047032A true KR20030047032A (en) | 2003-06-18 |
Family
ID=29573690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010077407A KR20030047032A (en) | 2001-12-07 | 2001-12-07 | A method for forming a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20030047032A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100959448B1 (en) * | 2007-12-04 | 2010-05-26 | 주식회사 동부하이텍 | Semiconductor Device and Method for Manufacturing the same |
-
2001
- 2001-12-07 KR KR1020010077407A patent/KR20030047032A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100959448B1 (en) * | 2007-12-04 | 2010-05-26 | 주식회사 동부하이텍 | Semiconductor Device and Method for Manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5783475A (en) | Method of forming a spacer | |
| KR100396895B1 (en) | Method of fabricating semiconductor device having L-type spacer | |
| JPH081957B2 (en) | Method for manufacturing semiconductor device | |
| US6869839B2 (en) | Method of fabricating a semiconductor device having an L-shaped spacer | |
| US6969646B2 (en) | Method of activating polysilicon gate structure dopants after offset spacer deposition | |
| JPH0661487A (en) | Semiconductor device and its manufacture | |
| KR100223736B1 (en) | Method of manufacturing semiconductor device | |
| KR100313089B1 (en) | Method for manufacturing semiconductor device | |
| US6221745B1 (en) | High selectivity mask oxide etching to suppress silicon pits | |
| KR20030089082A (en) | Method for fabricating semiconductor device | |
| KR101062835B1 (en) | Method for manufacturing gate electrode of semiconductor device using double hard mask | |
| KR20030047032A (en) | A method for forming a semiconductor device | |
| JPH09213941A (en) | Semiconductor device and manufacture of semiconductor device | |
| US6238958B1 (en) | Method for forming a transistor with reduced source/drain series resistance | |
| KR100806136B1 (en) | Method for fabricating semiconductor device having meta-gate electrode | |
| US6790720B1 (en) | Method for fabricating a MOSFET and reducing line width of gate structure | |
| KR100433054B1 (en) | Method For Manufacturing Semiconductor Devices | |
| KR100451033B1 (en) | Fabricating method of semiconductor device | |
| KR100268865B1 (en) | Method for fabricating semiconductor device | |
| KR100474744B1 (en) | Method for fabricating gate spacer of semiconductor device | |
| GB2327296A (en) | Reverse self aligned narrow gate fet | |
| KR20020032740A (en) | method for manufacturing semiconductor device | |
| KR20040028244A (en) | Fabricating method of semiconductor device | |
| KR20010008564A (en) | Method for manufacturing transistor of a semiconductor device | |
| KR20050064010A (en) | Method for fabricating semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| WITN | Withdrawal due to no request for examination |