KR20030042535A - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent the short between a contact plug and a conductive layer pattern by minimizing the etched portion of the first nitride layer using the second nitride layer. CONSTITUTION: After sequentially forming the first polysilicon plug(33) and a bit line pattern made of a metal line(34a) and the first nitride layer(34b) on a semiconductor substrate(31), the second nitride layer(35) having a thickness of 200-500 angstrom is deposited on the entire surface of the resultant structure. After sequentially forming the second interlayer dielectric(36) and a contact mask on the resultant structure, a contact hole is formed by etching the second interlayer dielectric(36) using the contact mask. At the time, the second nitride layer portion formed on the bit line pattern, is thicker than any other portion, so that the etched portion of the first nitride layer(34b) is minimized, thereby preventing the bit line pattern from being exposed. Then, a storage node contact plug(40) is formed in the contact hole for contacting the first polysilicon plug(33).

Description

Manufacturing Method of Semiconductor Device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a short between a contact and a conductive layer pattern is suppressed.

In recent years, as the integration of devices increases, the size of memory cells decreases gradually, so that margins of word lines and capacitor contacts, bit lines and capacitor contacts become smaller, and thus capacitor capacitors must be made smaller.

In addition, as semiconductor integrated circuits become highly integrated, mis-align margins between a plurality of wiring layers or contact holes are gradually decreasing. Furthermore, in the case where there is no room in a design rule like a semiconductor memory cell and a pattern of the same pattern is repeated, a method of reducing the area of the memory cell by forming a contact hole in a self-aligned manner is studied. Developed. This is to form a contact hole by using the step of the peripheral structure, the contact hole of various sizes can be obtained without using a mask by the height of the peripheral structure, the thickness of the insulating material to be formed and the etching method, etc. It is used in a method suitable for the implementation of the semiconductor device to be miniaturized.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, a first interlayer insulating film 12 is deposited on a semiconductor substrate 11 on which a transistor including a word line and a source / drain (not shown) is formed. A contact mask (not shown) using a photoresist film is formed thereon, and the first interlayer insulating film 12 is etched with the contact mask to form a contact hole through which a predetermined portion of the semiconductor substrate 11 is exposed.

Next, polysilicon is deposited and planarized on the entire surface including the contact hole to form the first polysilicon plug 13 connected to the semiconductor substrate 11 through the contact hole, and then the first polysilicon plug 13 is formed. A bit line pattern having a stacked structure of the bit line wiring film 14a and the nitride film 14b is formed on the first interlayer insulating film 12 that is included. At this time, the bit line pattern is formed on a predetermined surface of the first interlayer insulating film 12 so as not to be connected to the first polysilicon plug 13, and the nitride film 14b is formed during etching of the second interlayer insulating film for subsequent contact hole formation. It is an etch stop film for preventing the bit line wiring film 14a from being exposed.

Next, after the nitride film is deposited as a spacer insulating film on the entire surface including the bit line pattern, the entire surface is etched to form a spacer nitride film 14c in contact with both sidewalls of the bit line pattern, and then the bit line pattern having the spacer nitride film 14c formed thereon. The second interlayer insulating film 15 is deposited on the entire surface including the film.

Subsequently, a storage node contact mask 16 using a photosensitive film is formed on the second interlayer insulating film 15.

As shown in FIG. 1B, the contact hole 17 exposing the surface of the first polysilicon plug 13 between the bit line patterns by etching the second interlayer insulating layer 15 with the storage node contact mask 16 is formed. After the formation, the storage node contact mask 16 is removed.

As shown in FIG. 1C, a second poly is deposited on the front surface including the contact hole 17 and chemically polished or etched back to be connected to the first polysilicon plug 13 through the contact hole 17. A silicon plug (hereinafter referred to as a storage node contact plug) 18 is formed.

Although not shown in the drawings, a capacitor connected to the semiconductor substrate 11 through the storage node contact plug 18 and formed of a lower electrode, a dielectric film, and an upper electrode is formed in a subsequent process.

In the above-described conventional technique, the nitride layer 14b and the spacer nitride layer may be formed of an etch stop layer and a spacer, respectively, to prevent the bit line wiring layer 14a from being exposed when the second interlayer insulating layer 15 for forming the contact hole 17 is etched. 14c) is used, and an ordinary oxide film is used as the second interlayer insulating film 15. That is, as the design rule becomes smaller, the etching method using the high etching selectivity of the oxide film and the nitride film is applied due to the difficulty of contact formation.

However, when the exposed area of the nitride stop film 14b, which is an etch stop film, is small, sufficient polymers, which serve as etch stops during contact etching, may not be sufficiently formed to be etched at almost the same speed as the oxide film, thereby forming the bit line interconnection film 14a. ) Is exposed, thereby shorting the storage node contact plug 18 and the bit line interconnection film 14a, thereby reducing the yield of the device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and is a semiconductor device suitable for suppressing a short between a contact and a conductive layer pattern as a conductive layer pattern such as a bit line and a word line is exposed during contact hole etching. It is an object to provide a manufacturing method.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention;

3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 first interlayer insulating film

33: first polysilicon plug 34a: bit line wiring film

34b: first nitride film 35: second nitride film

36: second interlayer insulating film 37: contact mask

38: contact hole 39: spacer

40: Storage node contact plug

A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a plurality of first conductive film patterns stacked on the semiconductor substrate in the order of the first conductive film and the etch stop film, the first conductive film pattern Forming a spacer insulating layer on the entire surface including a spacer layer having a thickness thicker than a bottom surface at an upper portion of the first conductive layer pattern and a corner portion of the upper layer portion of the first conductive layer pattern; forming an interlayer dielectric layer on the spacer insulating layer Forming a contact hole by selectively etching the interlayer insulating layer so that the etching is stopped on the spacer insulating layer, selectively etching the spacer insulating layer exposed after forming the contact hole to expose the semiconductor substrate, and simultaneously Forming a spacer on sidewalls of the film pattern, and plugging a second conductive film into the contact hole. It characterized by yirueojim including system.

In addition, the method of manufacturing a semiconductor device of the present invention comprises the steps of forming a first interlayer insulating film on a semiconductor substrate, forming a first contact plug connected to the semiconductor substrate through the first interlayer insulating film, the first Forming a plurality of bit line patterns stacked in the order of the first conductive film and the first nitride film on a predetermined surface of the interlayer insulating film, and forming an upper layer portion of the bit line pattern and the bit line pattern on the entire surface including the bit line pattern. Forming a second nitride film to have a thickness relatively thicker than a bottom surface at an upper edge portion, forming a second interlayer insulating film on the second nitride film, and etching the second interlayer insulating film to stop etching in the second nitride film. Selectively etching to form a contact hole exposing between the bit line patterns, and etching the entire surface of the second nitride layer exposed after forming the contact hole And exposing the first contact plug and simultaneously forming spacers on sidewalls of the bit line pattern, and plugging the storage node contact plug into the contact hole.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

As shown in FIG. 2A, a plurality of word line patterns formed of a stacked film of a word line wiring film 22a and a first nitride film 22b are formed on a semiconductor substrate 21 on which a gate oxide film (not shown) is formed. Thereafter, source / drain regions 23 are formed in the semiconductor substrate 21 on both sides of the word line pattern through ion implantation. In this case, the first nitride layer 22b serves as an etch stop layer to prevent the word line wiring layer 22a from being exposed during subsequent contact etching, and a conventional oxide layer may be used.

Subsequently, the second nitride film 24 is deposited on the entire surface as an insulating film used as a spacer of the conventional word line wiring film 22a, but the plasma enhanced chemical vapor deposition method has poor step coverage; PECVD) to deposit a thickness of 200 kPa to 500 kPa.

At this time, the second nitride film 24 is deposited under the condition that the step coverage of the upper and upper edges of the word line pattern has 30% to 60%, and the deposition thickness is about 2.5 times that of the bottom surface and side surface. thick.

Next, an interlayer insulating film 25 is deposited on the second nitride film 24, and then a contact mask 26 by a photosensitive film is formed on the interlayer insulating film 25. Here, the interlayer insulating film 25 uses an insulating film of an ordinary oxide film series.

As shown in FIG. 2B, the interlayer insulating layer 25 is etched with the contact mask 26 to form the contact hole 27, wherein the second nitride layer 24 has a selectivity with the interlayer insulating layer 25. It acts as an etch stop.

When etching the interlayer insulating layer 25 for forming the above-described contact hole 27, a second nitride layer 24 is deposited on the upper side and the upper side of the word line pattern to be thicker than the bottom surface to expose the second insulating layer 25. By increasing the area of the nitride film 24, the amount of polymer deposited on the surface of the first nitride film 22b, which is exposed even when all of the second nitride film 24 is etched, is increased so that the first nitride film 22b is etched on the upper portion of the word line pattern. Minimize the amount.

Subsequently, the contact mask 26 is removed.

As shown in FIG. 2C, the second nitride layer 24 remaining after the formation of the contact hole 27 is etched to expose the contact hole 27 exposing the surface of the source / drain region 23 between the word line patterns. At the same time, the spacer 28 is opened while being fully open and in contact with the sidewall of the word line pattern.

Subsequently, after depositing a contact material such as polysilicon on the front surface, a contact plug 29 connected to the source / drain 23 through the contact hole 27 through chemical mechanical polishing or etch back is formed.

In the above-described first embodiment, the etching amount of the first nitride film 22b is increased even when the first nitride film 22b included in the word line pattern is exposed by widening the exposed area of the spacer second nitride film 24 during the contact hole etching. By minimizing this, the word line wiring layer 22a is prevented from being exposed, thereby preventing a short between the contact (or plug) and the word line wiring layer embedded in the subsequent contact hole.

3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

As shown in FIG. 3A, after depositing the first interlayer insulating film 32 on the semiconductor substrate 31 on which the transistor including the word line and the source / drain (not shown) is formed, the first interlayer insulating film 32 is formed. Is selectively etched to form a contact hole through which a predetermined portion of the semiconductor substrate 31 is exposed.

Next, polysilicon is deposited and planarized on the entire surface including the contact hole to form a first polysilicon plug 33 connected to the semiconductor substrate 31 through the contact hole, and then the first polysilicon plug 33 is formed. A bit line pattern having a stacked structure of the bit line wiring film 34a and the first nitride film 34b is formed on the included first interlayer insulating film 32.

Here, the first nitride film 34b acts as an etch stop film.

Next, the second nitride film 35 is deposited on the entire surface including the bit line pattern as a spacer of the conventional bit line pattern, but has a thickness of 200 mW to 500 mW by plasma chemical vapor deposition (PECVD) with poor step coverage. Deposit.

At this time, the second nitride film 35 is deposited under the condition that the step coverage of the upper and upper edges of the bit line pattern has 30% to 60%, and the deposition thickness thereof is about 2.5 times thicker than the bottom and side surfaces.

Next, a second interlayer insulating film 36 is deposited on the second nitride film 35, and then a contact mask 37 using a photosensitive film is formed on the second interlayer insulating film 36.

As shown in FIG. 3B, the second interlayer insulating layer 36 is etched with the contact mask 37 to form the contact hole 38. At this time, the second nitride film 35 has a selectivity with the second interlayer insulating film 36 to serve as an etch stop film.

When forming the contact hole 38 described above, an area of the second nitride film 35 that is exposed when the second interlayer insulating film 36 is etched by depositing the second nitride film 35 on the upper side of the bit line pattern and the upper side thereof is thicker than the bottom surface. By increasing the width of the second nitride film 35, the amount of polymer deposited on the surface of the first nitride film 34b that is exposed even when all of the second nitride film 35 is etched is increased to minimize the amount of the first nitride film 34b etched on the upper part of the bit line pattern.

As shown in FIG. 3C, the second nitride layer 35 exposed after the formation of the contact hole 38 is etched to expose the surface of the first polysilicon plug 33 between the bit line patterns. Is completely opened and at the same time the spacer 39 is formed on the sidewall of the bit line pattern, and then the contact mask 37 is removed.

Next, a second polysilicon plug, that is, a storage, is deposited on the front surface including the contact hole 38 and chemically polished or etched back to be connected to the first polysilicon plug 33 through the contact hole 38. The node contact plug 40 is formed.

Although not shown in the drawings, a capacitor connected to the semiconductor substrate 31 through the storage node contact plug 40 is formed in a subsequent process to form a capacitor including a lower electrode, a dielectric film, and an upper electrode.

In the above-described second embodiment, the second nitride layer having poor step coverage is formed on the upper and upper edges of the bit line pattern to prevent the bit line wiring layer from being exposed when forming the contact hole where the storage node contact plug is to be formed.

Although not shown in the drawings, in the above-described second embodiment, when the contact hole for forming the first polysilicon plug is formed, the first nitride silicon film is applied even when the first polysilicon plug is buried between the word lines. The short between the polysilicon plug and the word line can be suppressed.

Meanwhile, the present invention can be applied to the contact etching process and the plug process of all the highly integrated semiconductor devices as well as the first and second embodiments described above.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can reduce the loss of the nitride film used as the etch stop layer of the conductive layer patterns (bit line and word line), thereby reducing the short between the conductive layer pattern and the contact plug, thereby improving the electrical characteristics and the yield of the device. It can be effected.

Claims (9)

Forming a plurality of first conductive film patterns stacked on the semiconductor substrate in the order of the first conductive film and the etch stop film; Forming a spacer insulating film on the entire surface including the first conductive film pattern so as to have a thickness relatively thicker than a bottom surface at an upper portion of the first conductive film pattern and a corner portion of the upper layer of the first conductive film pattern; Forming an interlayer insulating film on the spacer insulating film; Forming a contact hole by selectively etching the interlayer insulating layer so that etching is stopped on the spacer insulating layer; Selectively etching the spacer insulating layer exposed after the contact hole is formed to expose the semiconductor substrate and to form a spacer on sidewalls of the first conductive layer pattern; And Plugging a second conductive film into the contact hole Method for manufacturing a semiconductor device comprising the. The method of claim 1, Forming the spacer insulating film, A method for manufacturing a semiconductor device, characterized by a plasma chemical vapor deposition method. The method of claim 1, And the spacer insulating film is deposited under the condition that the step coverage of the upper layer portion of the first conductive layer pattern and the corner portion of the upper layer portion of the first conductive layer pattern has 30% to 60%. The method of claim 1, And the etching stop film and the spacer insulating film are nitride films. The method of claim 1, The spacer insulating film is a semiconductor device manufacturing method, characterized in that formed in a thickness of 200 ~ 500Å. Forming a first interlayer insulating film on the semiconductor substrate; Forming a first contact plug penetrating the first interlayer insulating film and connected to the semiconductor substrate; Forming a plurality of bit line patterns stacked in the order of the first conductive film and the first nitride film on a predetermined surface of the first interlayer insulating film; Forming a second nitride film on the entire surface including the bit line pattern to have a thickness relatively thicker than a bottom surface at an upper portion of the bit line pattern and an edge portion of the upper layer portion of the bit line pattern; Forming a second interlayer insulating film on the second nitride film; Selectively etching the second interlayer insulating layer so as to stop etching in the second nitride layer to form a contact hole exposing between the bit line patterns; Forming a spacer on the sidewall of the bit line pattern while simultaneously etching the second nitride film exposed after the contact hole to expose the first contact plug; And Plugging a storage node contact plug into the contact hole Method for manufacturing a semiconductor device comprising the. The method of claim 6, Forming the second nitride film, A method for manufacturing a semiconductor device, characterized by a plasma chemical vapor deposition method. The method of claim 6, And the second nitride film is deposited under the condition that the step coverage of the upper layer portion of the bit line pattern and the corner portion of the upper layer portion of the bit line pattern has 30% to 60%. The method of claim 6, And the second nitride film is formed to a thickness of 200 kPa to 500 kPa.