KR20030042493A - Method for surface defect removal after CMP process in semiconductor proecess - Google Patents
Method for surface defect removal after CMP process in semiconductor proecess Download PDFInfo
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- KR20030042493A KR20030042493A KR1020010072965A KR20010072965A KR20030042493A KR 20030042493 A KR20030042493 A KR 20030042493A KR 1020010072965 A KR1020010072965 A KR 1020010072965A KR 20010072965 A KR20010072965 A KR 20010072965A KR 20030042493 A KR20030042493 A KR 20030042493A
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- copper
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title abstract description 12
- 230000007547 defect Effects 0.000 title abstract description 11
- 241000430093 Proeces Species 0.000 title 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910052802 copper Inorganic materials 0.000 claims abstract description 50
- 239000010949 copper Substances 0.000 claims abstract description 50
- 239000010410 layer Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000000126 substance Substances 0.000 claims abstract description 5
- 239000002344 surface layer Substances 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 239000007800 oxidant agent Substances 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 150000001879 copper Chemical class 0.000 claims description 2
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 8
- 239000011229 interlayer Substances 0.000 abstract description 7
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 238000005498 polishing Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 9
- 239000002002 slurry Substances 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000908 ammonium hydroxide Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- XTEGARKTQYYJKE-UHFFFAOYSA-N chloric acid Chemical compound OCl(=O)=O XTEGARKTQYYJKE-UHFFFAOYSA-N 0.000 description 1
- 229940005991 chloric acid Drugs 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
Description
본 발명은 반도체 장치 제조 공정에 관한 것으로, 보다 상세하게는 반도체 장치 제조 공정에서 구리 배선이나 전극을 다마신 공정으로 형성하면서 발생하는 구리 패턴 표면의 결함을 제거하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing process, and more particularly, to a method of removing defects on the surface of a copper pattern generated while forming a copper wiring or an electrode by a damascene process in a semiconductor device manufacturing process.
반도체 장치 제조 공정에서 층간 절연막의 평탄화 방법으로, 다마신 공정에서의 콘택 플러그나 배선의 분리 형성 방법으로 CMP 가공이 많이 사용되고 있다. 특히, 구리 배선을 이용하는 반도체 장치에서 CMP 가공은 필수적인 공정으로 생각된다. 즉, 소자 고집적화에 따른 크기 감소로 배선이나 콘택 플러그 저항이 늘고, 배선 내의 전자적 이동(electromigration)이 큰 문제가 됨에 따라 도전성이 높은 구리를 콘택 플러그나 배선의 재료로 사용된다. 이때, 구리는 통상의 산에 식각되지 않으므로 패터닝이 어렵다. 따라서, 먼저 하부 절연막에 배선 홈이나 콘택 홀을형성하고, 이들을 구리층으로 채운 뒤, 하부 절연막 상면 위쪽에 적층된 잔여 구리층은 CMP로 제거하는 공정을 사용하게 된다.BACKGROUND OF THE INVENTION CMP processing is widely used as a method of planarization of an interlayer insulating film in a semiconductor device manufacturing process, and as a method of separately forming contact plugs and wirings in a damascene process. In particular, CMP processing is considered to be an essential process in a semiconductor device using copper wiring. That is, as the size decrease due to the high integration of the device increases the wiring or contact plug resistance, and the electromigration in the wiring becomes a big problem, copper having high conductivity is used as the material of the contact plug or the wiring. At this time, since copper is not etched in a conventional acid, patterning is difficult. Accordingly, a process of forming a wiring groove or a contact hole in the lower insulating film, filling them with a copper layer, and then removing the remaining copper layer stacked on the upper surface of the lower insulating film by CMP.
CMP 가공은 일정 거칠기를 가지는 패드로 기판면을 마찰시키고, 그 접촉면에 슬러리라고 통칭되는 식각 물질을 공급하는 방식으로 이루어진다. 슬러리는 CMP를 통해 제거하는 물질의 종류에 따라 달라질 수 있다. 가령, 실리콘 산화막 CMP에는 염기성 물질이 제공되고, 금속 CMP에는 금속을 산화시킬 수 있는 산성 물질들이 공급될 수 있다.CMP processing is performed by rubbing the substrate surface with a pad having a constant roughness, and supplying an etching material, commonly referred to as slurry, to the contact surface. The slurry may vary depending on the type of material removed through CMP. For example, the silicon oxide film CMP may be provided with a basic material, and the metal CMP may be supplied with acidic materials capable of oxidizing the metal.
그런데, 구리는 재질이 무른 금속이고 표면이 거칠어지기 쉬운 금속이다. 따라서, CMP와 같은 가공이 이루어질 때 CMP 패드와의 마찰면에서 압력과 슬러리 입자의 작용으로 인하여 산화된 부분뿐 아니라 금속 부분까지 거칠게 떨어져 나가 마이크로 스크래치가 많이 발생하는 문제가 있다. 마이크로 스크래치와 같은 작은 결함은 비록 제품의 수명에 직접 영향을 미치지 않는 경우에도, 구리 배선의 외관 불량과 신뢰성에 간접적인 영향을 미칠 수 있다. 구리층이 가령, 캐퍼시터의 전극으로 사용되는 경우 마이크로 스크래치는 전극 표면을 거칠게 하면서 전극 간격이 일정치 않도록 하고, 캐퍼시터 용량에 영향을 미칠 수도 있다. 또한, 스크래치는 배선 내에서 전기적 이동(electro migration)을 시발시키는 취약점이 될 수도 있다.By the way, copper is a soft metal and the surface is a metal which is easy to be rough. Therefore, when a process such as CMP is made, there is a problem in that micro scratches occur a lot from the oxidized part as well as the metal part due to the action of pressure and slurry particles in the friction surface with the CMP pad. Small defects, such as micro scratches, can indirectly affect the appearance and reliability of copper interconnects, even if they do not directly affect the life of the product. If a copper layer is used, for example, as the electrode of the capacitor, the microscratches may roughen the electrode surface, resulting in uneven electrode spacing, and may affect capacitor capacity. Scratch may also be a vulnerability that initiates electro migration within the wiring.
본 발명은 상술한 바와 같이 구리 배선을 채택한 반도체 장치에서, 다마신 공정을 위한 CMP 가공에 따라 발생하는 배선 표면에 발생하는 결함을 제거하기 위한 것으로, CMP 가공에 따른 구리 패턴 표면의 결함을 제거할 수 있는 방법을 제공하는 것을 목적으로 한다.The present invention is to remove defects on the wiring surface generated by the CMP process for the damascene process in the semiconductor device adopting the copper wiring as described above, to eliminate the defects on the surface of the copper pattern according to the CMP process It aims to provide a way to.
본 발명은 또한, 반도체 장치의 신뢰성을 높일 수 있도록 CMP 후의 구리 패턴의 표면 결함을 제거하는 방법을 제공하는 것을 목적으로 한다.It is another object of the present invention to provide a method for removing surface defects of a copper pattern after CMP so as to increase the reliability of the semiconductor device.
도1 내지 도5는 본 발명의 일 실시예에 따른 공정의 각 단계를 나타내는 공정 단면도들이다.1 to 5 are process cross-sectional views illustrating respective steps of a process according to an embodiment of the present invention.
상기 목적을 달성하기 위한 반도체 장치 구리 패턴의 표면 결함 제거 방법은, 다마신 공정을 위해 형성된 홈에 구리층을 적층하고 CMP 가공을 통해 홈에만 구리층을 남긴 상태에서 손상된 구리층 표면을 일정 깊이로 변성시키는 단계와 변성된 부분의 구리층을 식각 물질로 제거하는 단계를 구비하여 이루어진다.In order to achieve the above object, a method for removing surface defects of a copper pattern of a semiconductor device may be performed by stacking a copper layer in a groove formed for a damascene process and leaving the copper layer only in the groove through a CMP process to a predetermined depth. And modifying the copper layer of the modified portion with an etching material.
즉, 본 발명의 방법은, 기판 절연막에 배선용 음각 패턴을 형성하는 단계, 음각 패턴이 형성된 기판에 구리를 적층하여 음각 패턴을 채우는 단계, 상기 절연막 상면에 덮인 구리층을 CMP 가공을 통해 제거하는 단계, 음각 패턴에 잔류된 구리 패턴의 노출면을 일정 깊이로 변성시키는 단계, 변성된 구리층을 식각 제거하는 단계를 구비하여 이루어진다.That is, the method of the present invention comprises the steps of: forming a wiring intaglio pattern on the substrate insulating film, laminating copper on the substrate on which the intaglio pattern is formed, filling the intaglio pattern, and removing the copper layer covered on the top surface of the insulating film through CMP processing. And modifying the exposed surface of the copper pattern remaining in the intaglio pattern to a predetermined depth, and etching away the modified copper layer.
본 발명의 구리 패턴을 변성시키는 단계에서 통상, 산화 방법을 사용할 수 있다. 구리 패턴의 표층을 산화시키는 방법은 금속 산화제로 사용될 수 있는 과산화수소, 질산, 수산화암모늄 등의 화학약품 용액으로 습식 처리하는 방법과 산소 원자를 포함하는 라디칼을 플라즈마 에칭 방식으로 작용시키는 방법 등을 들 수 있다. 그리고, 구리 산화층에 대한 제거는 불산 등 산화물 제거용 물질에 의한 식각을 통해 이루어질 수 있다.In the step of modifying the copper pattern of the present invention, an oxidation method can be generally used. The method of oxidizing the surface layer of a copper pattern includes a wet treatment with a chemical solution such as hydrogen peroxide, nitric acid, and ammonium hydroxide, which can be used as a metal oxidant, and a method of operating a radical containing oxygen atoms by plasma etching. have. The copper oxide layer may be removed by etching with an oxide removing material such as hydrofluoric acid.
한편, CMP 가공에서 슬러리 물질 입자에 의한 구리층 표면 결함은 통상 수십내지 수백 옹스트롬 깊이까지 이루어질 수 있으므로 변성층의 깊이는 슬러리 성질과 CMP 가공의 특성을 고려하여 10 내지 1000 옹스트롬으로 할 수 있다.On the other hand, the copper layer surface defects due to the slurry material particles in the CMP process can usually be made up to several tens to hundreds of angstroms deep, the depth of the modified layer may be 10 to 1000 angstroms in consideration of the slurry properties and the characteristics of the CMP process.
이하 도면을 참조하면서 본 발명의 실시예를 통해 본 발명의 진행을 상세히 설명한다.Hereinafter, the progress of the present invention will be described in detail with reference to the accompanying drawings.
도1은 기판(10)에 반도체 장치 하부 구조가 이루어진 뒤 층간 절연막(11)이 기판(10)에 적층된 상태에서 구리 배선을 위한 홈(13)이 형성된 단면을 나타낸다. 층간 절연막(11)으로 흔히 실리콘 산화막이 사용되면, 기생 용량(parasitic capacitance)을 줄이기 위한 저유전 물질을 사용할 수 있다.FIG. 1 shows a cross section in which a groove 13 for copper wiring is formed in a state in which an interlayer insulating film 11 is stacked on the substrate 10 after the semiconductor device lower structure is formed on the substrate 10. When a silicon oxide film is often used as the interlayer insulating film 11, a low dielectric material for reducing parasitic capacitance may be used.
도2를 참조하면, 기판의 배선 홈(13)에 베리어 메탈층(15)으로 티타늄 질화막이 적층된다. 베리어 메탈로는 그 외에 탄탈륨 질화막 등의 구리에 대한 베리어막이 이용될 수 있다. 베리어 메탈층(15)은 통상 스퍼터링이나 CVD 방법으로 수백 옹스트롬 두께로 적층된다. 이어서, 구리층(17)이 형성된다. 구리층(17) 형성을 위해 먼저 구리 시드층이 스퍼터링이나 CVD 방법으로 적층된다. 시드층은 수십 내지 수백 옹스트롬으로 적층하며 적층 속도가 낮다. 시드층에 이어 전기 도금(electroplating) 방법으로 배선 홈(13)을 완전히 채운다. 이 과정에서 층간 절연막(11) 상면 위에도 베리어 메탈층(15)과 구리층(17)이 적층된다.Referring to FIG. 2, a titanium nitride film is stacked as a barrier metal layer 15 in a wiring groove 13 of a substrate. As the barrier metal, a barrier film for copper such as a tantalum nitride film may be used. The barrier metal layer 15 is typically laminated to a few hundred angstroms in thickness by sputtering or CVD. Next, a copper layer 17 is formed. To form the copper layer 17, a copper seed layer is first deposited by sputtering or CVD. The seed layer is stacked in tens to hundreds of angstroms and has a low deposition rate. Following the seed layer, the wiring groove 13 is completely filled by electroplating. In this process, the barrier metal layer 15 and the copper layer 17 are stacked on the upper surface of the interlayer insulating layer 11.
도3을 참조하면, 기판 전면에 CMP 가공을 통해 층간 절연막(11) 위쪽에 쌓인 베리어 메탈층(13)과 구리층(15)을 제거한다. 따라서, 배선 홈(13)에만 구리층이 잔류하여 배선 패턴(19)을 형성한다. 이때, 배선 패턴(19)의 상면에는 CMP 가공으로 인한 마이크로 스크래치(21)가 수십 내지 수백 옹스트롬 깊이까지 발생될 수 있다.Referring to FIG. 3, the barrier metal layer 13 and the copper layer 15 stacked on the interlayer insulating layer 11 are removed by CMP processing on the entire surface of the substrate. Therefore, the copper layer remains only in the wiring groove 13 to form the wiring pattern 19. In this case, the micro scratch 21 due to the CMP process may be generated to a depth of several tens to several hundred angstroms on the upper surface of the wiring pattern 19.
도4를 참조하면, 기판에 강력한 산화성을 가지는 물질들을 작용시켜 강제 산화를 실시한다. 가령, 금속 산화제로 흔히 사용되는 과산화수소, 질산, 수산화암모늄, 염소산 등의 화학약품 용액을 기판에 고르게 분사하거나, 화학약품 용액이 담긴 수조에 기판을 담근다. 혹은, 산소 가스를 공급하면서 공정 챔버에 고주파 전계를 인가하여 산소를 포함하는 플라즈마를 형성하고, 플라즈마에 포함되는 산소 포함 라디칼을 플라즈마 에칭 방식으로 기판에 작용시키는 방법 등을 들 수 있다. 이때, 공정의 온도나 시간 기타 공정 조건은 구리 배선 패턴(19) 표면에 형성되는 산화층(23)이 CMP에 의한 결함이 발생되는 깊이보다 두껍게 형성되도록 조절한다.Referring to FIG. 4, forced oxidation is performed by applying materials having strong oxidizing property to a substrate. For example, a chemical solution, such as hydrogen peroxide, nitric acid, ammonium hydroxide, or chloric acid, which is commonly used as a metal oxidant, is evenly sprayed onto the substrate, or the substrate is immersed in a tank containing the chemical solution. Alternatively, a method in which a high frequency electric field is applied to the process chamber while supplying oxygen gas to form a plasma containing oxygen, and the oxygen-containing radicals contained in the plasma are acted on the substrate by a plasma etching method. At this time, the temperature or time and other process conditions of the process is adjusted so that the oxide layer 23 formed on the surface of the copper wiring pattern 19 is thicker than the depth at which defects caused by CMP are generated.
도4 및 도5를 참조하면, 구리 배선 패턴(19) 표면에 형성된 강제 산화층(23)에 불산 용액등을 작용시켜 산화층(23)을 식각, 제거한다. 산화층(23) 제거와 함께 산화층에 있는 마이크로 스크래치(21)도 제거된다. 산화층(23) 제거에는 습식 식각을 이용하는 것이 잔존하는 구리 배선(19')의 표면 거칠기를 줄이는 데 바람직하다.4 and 5, a hydrofluoric acid solution or the like is applied to the forced oxide layer 23 formed on the copper wiring pattern 19 to etch and remove the oxide layer 23. Along with removing the oxide layer 23, the micro scratches 21 in the oxide layer are also removed. It is preferable to use wet etching to remove the oxide layer 23 to reduce the surface roughness of the remaining copper wiring 19 '.
본 발명에 따르면, 구리 배선, 전극 기타 패턴을 CMP를 통해 형성할 때 구리의 무른 성질 등으로 마이크로 스크래치 같은 결함이 발생하는 경우에도 사후적으로 이를 제거할 수 있다. 따라서, 패턴의 외관을 공정에 적합하게 유지하고, 전자적 이동에 의한 단절점 발생 가능성 등을 사전에 제거하여 반도체 장치의 신뢰성을 높일 수 있다.According to the present invention, even when defects such as micro scratches occur due to the soft nature of copper when forming copper wirings, electrodes and other patterns through CMP, they can be removed afterwards. Therefore, it is possible to maintain the appearance of the pattern appropriately for the process and to eliminate the possibility of breakpoints caused by electronic movement in advance, thereby increasing the reliability of the semiconductor device.
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