KR20030039236A - Method of forming concave type capacitor for ferroelectric memory device - Google Patents

Abstract

PURPOSE: A method for forming a concave-type capacitor in a ferroelectric memory device is provided to prevent oxidation of a plug by preventing over-etch of a lower insulating layer. CONSTITUTION: The first interlayer dielectric(53) is formed on a substrate(50) having a junction region(52). A plug(57) is formed to connect the junction region via a contact hole. A barrier pattern including the first diffusion barrier layer(58), an oxidation barrier layer(59) and the second diffusion barrier layer(60), is formed on the resultant structure. After forming the second interlayer dielectric(61) on the barrier pattern, the resultant structure is planarized to expose the barrier pattern. The third interlayer dielectric(62) is formed on the resultant structure. A concave-type structure is formed by selectively etching the third interlayer dielectric to expose the barrier pattern. At the time, the barrier pattern has a relatively wide width compared to the width of the concave-type structure.

Description

FIELD OF CONFORMING CONCAVE TYPE CAPACITOR FOR FERROELECTRIC MEMORY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor of a memory device, and more particularly to a method of forming a concave type capacitor of a ferroelectric memory device.

By using a ferroelectric material in a capacitor in a semiconductor memory device, the development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a conventional DRAM (Dynamic Random Access Memory) device has been in progress. A ferroelectric random access memory (FeRAM) device is a nonvolatile memory device that not only stores stored information even when a power supply is cut off, but also has an operation speed comparable to that of a conventional DRAM. In addition, as a ferroelectric material of the FeRAM device, PZT, SBT, SBTN and the like are generally used. In this case, the upper electrode is made of metal such as Pt, Ir, Ru, Pt alloy, or the like.

On the other hand, in order to secure sufficient cell capacitance due to high integration, the capacitors are formed in a three-dimensional structure such as a stack type and a concave type. Since capacitors must be patterned in units of four capacitors, capacitors are formed in a concave type structure rather than a stacked type.

1 is a cross-sectional view for explaining a method of forming a concave capacitor of a conventional FeRAM memory device.

Referring to FIG. 1, a first interlayer insulating layer 13 is formed on a semiconductor substrate 10 on which a field insulating layer 11 and a junction region 12 are formed, and the first interlayer insulating layer 13 is exposed to expose the junction region 12. 13) is etched to form a contact hole for contacting the lower electrode of the capacitor with the junction region 12. Subsequently, a laminated film of the Ti / TiN film 14 is formed on the contact hole surface and the first interlayer insulating film 13, and heat treatment is performed to react silicon and Ti in the junction region 12 so as to react in the contact hole. A titanium silicide (TiSi 2) film 15 is formed on the junction region 12. Thereafter, a TiN film 16 is formed on the contact hole surface and the Ti / TiN film 14 on which the titanium silicide film 15 is formed, and a tungsten film is formed on the TiN film 16 to be filled in the contact hole. The tungsten plug 17 is formed by etching the entire surface of the tungsten film, the TiN film 16, and the Ti / TiN film 14 so that the surface of the first interlayer insulating film 13 is exposed.

Then, the first diffusion barrier film 18 of the TiN film, the antioxidant film 19 of the Ir film, and the second diffusion barrier film 20 of the IrOx film were sequentially stacked on the entire surface of the substrate, and patterned so as to remain only on the plug 17. The barrier pattern of the layer is formed. Here, the barrier pattern is formed only on the plug 17 to prevent diffusion between the plug 17 and the lower electrode formed thereafter and oxidation of the plug, and the first diffusion barrier 18 is formed of the plug 17 and the antioxidant film. The diffusion between the layers 19 is prevented, and the antioxidant layer 19 prevents oxidation of the plug 17 during the heat treatment process, and the second diffusion barrier layer 20 is formed between the antioxidant layer 19 and the lower electrode formed thereafter. Prevents spread. Thereafter, the second interlayer insulating film 21 is formed on the entire surface of the substrate, the entire surface is etched so that the surface of the second diffusion barrier film 20 is exposed, and the surface is planarized. Then, the third interlayer insulating film 22 is formed. Next, the third interlayer insulating film 22 is etched to expose the surface of the second diffusion barrier film 20 and the second interlayer insulating film 21 to form a concave structure 23, and then a subsequent process is performed. .

However, in the above-described conventional concave type capacitor forming method, since the barrier pattern for preventing diffusion and oxidation between the plug 17 and the lower electrode is formed only on the upper part of the plug, the concave type structure 23 is formed. When the third interlayer dielectric layer 22 is etched, as shown in FIG. 1, over-etch of the second interlayer dielectric layer 21 is severely generated. Accordingly, since the barrier pattern is exposed and part of the Ir film, which is the antioxidant film 19, is partially lost, the oxidation resistance of the plug 17 in the subsequent heat treatment at high temperature is lowered, and the oxidation of the plug 17 is prevented. In order to limit the heat treatment temperature there was a problem.

Accordingly, the present invention is to solve the above problems, a method of forming a concave-type capacitor of a ferroelectric memory device that can improve the oxidation resistance of the plug by preventing over-etching of the lower insulating film during the etching for forming the concave structure The purpose is to provide.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view for explaining a method of forming a concave capacitor in a conventional FeRAM memory device.

2A to 2F are cross-sectional views illustrating a method of forming a concave capacitor in a FeRAM memory device according to an embodiment of the present invention.

※ Explanation of codes for main parts of drawing

50 semiconductor substrate 51 field insulating film

52 junction region 53 first interlayer insulating film

54: Ti / TiN film 55: titanium silicide film

56 TiN film 57 plug

58: first diffusion barrier 59: antioxidant

60 second diffusion barrier 61 second interlayer insulating film

62: third interlayer insulating film 63: concave type structure

64: adhesive film 65: first metal film

66 ferroelectric film 67 second metal film

In order to achieve the object of the present invention, the method of manufacturing a concave type capacitor of the ferroelectric memory device according to the present invention has a predetermined junction region, a first interlayer insulating film is formed on the top, the contact provided in the first interlayer insulating film Preparing a semiconductor substrate having a plug in contact with a junction region through a hole; Forming a predetermined barrier pattern on the substrate to sufficiently cover the plug; Forming a second interlayer insulating film on the entire surface of the substrate to cover the barrier pattern; Etching the second interlayer insulating film to expose the surface of the barrier pattern to planarize the surface of the substrate; Forming a third interlayer insulating film on the planarized substrate; Etching the third interlayer insulating film to expose the barrier pattern to form a concave structure; Forming a predetermined adhesive film on the sidewall of the concave structure; Forming an upper electrode on a sidewall and a bottom of a concave structure having an adhesive film formed thereon; Depositing a ferroelectric film and a second metal film for the upper electrode on the entire surface of the substrate on which the upper electrode is formed; And forming a capacitor by patterning the second metal film and the ferroelectric film, wherein the barrier pattern is formed to have a width larger than that of the concave type structure, and serves as an etch stop film during etching of the third interlayer insulating film.

The barrier pattern is formed by sequentially etching the first diffusion barrier, the antioxidant layer, and the second diffusion barrier.

Preferably, the first diffusion barrier is formed of a TiN film, the second antioxidant layer is formed of an Ir film, and the third diffusion barrier is formed of an IrOx film. In addition, the etching for forming the barrier pattern is performed using a gradient etching or a separate hard mask.

In addition, the adhesive film is formed of an Al ₂ O ₃ film, the first metal film is formed of a Pt film, the ferroelectric film is formed of one film selected from SBT film, SBTN film, PZT film, and BLT film, and the second metal film is It is formed of a Pt film.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2A to 2F are cross-sectional views illustrating a method of forming a concave capacitor of a ferroelectric memory device according to an embodiment of the present invention.

Referring to FIG. 2A, a first interlayer insulating film 53 is formed on a semiconductor substrate 50 on which a field insulating film 51 and a junction region 52 are formed, and the junction region 52 is exposed by photolithography and etching processes. The first interlayer insulating layer 53 is etched to form a contact hole for contacting the lower electrode of the capacitor with the junction region 52. Next, a stacked film of the Ti / TiN film 54 is formed on the contact hole surface and the first interlayer insulating film 53, and heat treatment is performed in an N ₂ atmosphere using Rapid Thermal Processing (RTP). Silicon and Ti in the junction region 52 are reacted to form a titanium silicide film 55 of TiSi or TiSi 2 for improving electrical characteristics on the junction region 52 in the contact hole. Here, the titanium silicide film 55 may be replaced with a cobalt silicide film such as CoSi or CoSi2 by applying Co instead of Ti.

Thereafter, a TiN film 56 is formed on the contact hole surface and the Ti / TiN film 54 on which the titanium silicide film 55 is formed, and a tungsten (W) film is formed on the TiN film 56 so as to be filled in the contact hole. Form. In this case, the tungsten film may be replaced with a conductive film such as a TiN film, a TaN film, and a polysilicon film. The tungsten film, the TiN film 56, and the Ti / TiN are then exposed to expose the surface of the first interlayer insulating film 53 by using a chemical mechanical polishing (CMP) or etch back process. The film 54 is etched entirely to form a tungsten plug 57.

Referring to FIG. 2B, on the substrate on which the plug 57 is formed, it serves as a predetermined barrier film for preventing diffusion between the plug 57 and the subsequent lower electrode and oxidation of the plug 57 at a high temperature. , Chemical vapor deposition (CVD), atomic layer deposition (ALD), or plasma vapor deposition (Plasma) of the first diffusion barrier 58, the antioxidant layer 59, and the second diffusion barrier 60. Laminate sequentially using Vapor Deposition (PVD) method. The first diffusion barrier 58 is a film that prevents diffusion between the plug 57 and the antioxidant layer 59, and includes a TiN film, a TaN film, a TiAlN film, a TiSiN film, a TaAlN film, a TaSiN film, a RuTiN film, and a RuTiO film. One film selected from among them, preferably a TiN film, is formed to a thickness of 50 to 1000 kPa. The anti-oxidation film 59 is a film that prevents oxidation of the plug 57. The anti-oxidation film 59 is one selected from an Ir film, a Ru film, a RuTiN film, and a RuTaN film having excellent barrier properties against oxygen. To 2000 mm thick. The second diffusion barrier 60 is a film that prevents the diffusion between the antioxidant layer 59 and the lower electrode. The second diffusion barrier 60 is formed of an IrOx film or a RuOx film, preferably an IrOx film, having a thickness of 50 to 2000 mW. In addition, in order to improve the anti-diffusion characteristic and the anti-oxidation characteristic, for example, N ₂ or O ₂ plasma treatment may be performed after the formation of the first diffusion barrier layer 58, and after the formation of the antioxidant layer 59, The heat treatment may be performed for 1 second to 5 hours at a temperature of 300 to 700 ° C. in a N ₂ , O ₂ or other inert gas atmosphere using a diffusion furnace or RTP.

Next, the second diffusion barrier 60, the antioxidant layer 59, and the first diffusion barrier layer 58 are formed by using the photolithography and etching process, and the second interlayer dielectric layer 53 around the plug 57 and the plug 57. ) Is patterned to be relatively wider than the conventional one (see Fig. 1) to form a barrier pattern. In addition to the diffusion and oxidation prevention described above, the barrier pattern also acts as an etch stop layer when forming the concave structure, and the etching process may be performed by a slope etch so that a fence of the antioxidant layer 59 does not occur. , A hard mask such as a TiN film having a thickness of 100 to 1000 μs may be applied.

Referring to FIG. 2C, the second interlayer insulating layer 61 is formed on the entire surface of the substrate to cover the barrier pattern by using a CVD, PVD, ALD, or spin-on method, and heat-treated to improve insulation characteristics. Perform The second interlayer insulating film 61 is one of a SiOx film, a SiON film, and a Si3N4 film, preferably a SiOx film, which is formed to a thickness thicker than the barrier pattern, preferably 1000 to 6000 GPa, and the heat treatment is diffused. The furnace or RTP is used for 1 second to 5 hours at a temperature of 400 to 800 ° C. in an N ₂ , O ₂ or other inert gas atmosphere. Next, the surface of the second diffusion barrier layer 60 is exposed by using a CMP process to etch the entire surface of the second interlayer insulating layer 61 to planarize the surface. In this case, the CMP process is performed by over etching so that the surface of the second diffusion barrier layer 60 is completely exposed. When the IrOx layer is used as the second diffusion barrier layer 60, the IrOx layer is overetched because CMP is not good. If you do not have a problem.

Referring to FIG. 2D, a third interlayer dielectric layer 62 is formed on the entire surface of the planarized substrate to have a thickness of 5000 to 20000 GPa, and the third interlayer dielectric layer 62 is formed using the barrier pattern as an etch stop layer by photolithography and etching. ) Is etched to form a concave structure 63. At this time, the concave structure 63 is formed to be narrower than the width of the barrier pattern, and the over pattern of the lower second interlayer insulating film 61 as in the related art (see Fig. 1) does not occur by the barrier pattern.

Referring to FIG. 2E, in order to improve adhesion to the lower electrode of the capacitor to be formed later on the surface of the concave structure 63 and the third interlayer insulating layer 62, CVD or ALD having excellent step coverage characteristics. A predetermined adhesive film 64 is formed using the method, and the entire surface is etched by an etch back process so that only the sidewall of the concave structure 63 remains. Preferably, the adhesive film 64 is formed of an Al ₂ O ₃ film with a thickness of 50 to 500 kPa.

Referring to FIG. 2F, the first metal film 65 for the lower electrode is deposited on the structure of FIG. 2E by CVD or ALD with excellent step coverage characteristics. The first metal film 65 is one film selected from a film consisting of a Pt film, an Ir film, a Ru film, a RuOx film, and a combination thereof, preferably a Pt film, and has a thickness of 500 to 5000 kPa. Then, by using an etch back process using a CMP or photoresist film, the first metal film 65 is etched so as to remain only at the bottom and the side of the concave structure 63 to form the lower electrode of the capacitor. Then, the substrate on which the lower electrode is formed is heat-treated in an O ₂ , O ₃ , N ₂ , or Ar atmosphere at a temperature of 200 to 800 ° C. using a furnace or RTP process, or O ₂ , O ₃ , or N _2. Plasma treatment is performed using plasma of N ₂ O, or NH 3. In the case of using the furnace process, heat treatment is performed for 10 minutes to 5 hours, and in the case of using the RTP process, heat treatment is performed for 1 second to 10 minutes.

Then, the ferroelectric film 66 is formed on the entire surface of the substrate using CVD or ALD having excellent step coverage characteristics, and heat treatment is performed to improve the film quality of the ferroelectric 66. The ferroelectric film 66 is one film selected from an SBT film, an SBTN film, a PZT film, and a BLT film, and has a thickness of 50 to 3000 kPa. The heat treatment is performed by using a diffusion furnace or an RTP method. It is performed for 10 minutes to 5 hours in an O ₂ , N ₂ , Ar, O ₃ , He, Ne or Kr atmosphere at a temperature of 800 ℃. Thereafter, the second metal film 67 is deposited on the ferroelectric film 66 using CVD or ALD having excellent step coverage characteristics. The second metal film 67 is formed of a Pt film with a thickness of 500 to 5000 kPa. Thereafter, the second metal film 67 and the ferroelectric film 66 are patterned to form a capacitor.

As described above, according to the present invention, the barrier pattern for diffusion prevention and oxidation prevention is formed wider than the concave type structure to cover the plug and the plug periphery, and also acts as an etch stop layer during etching for forming the concave type capacitor. By doing so, it is possible to prevent overetching of the lower insulating film and the like, thereby improving the oxidation resistance of the plug for the subsequent heat treatment at high temperature.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the technical spirit of the present invention.

The present invention described above has the effect of improving the characteristics of the device by securing the oxidation resistance of the capacitor contact plug.

Claims (25)

A method of forming a concave capacitor of a ferroelectric memory device, Preparing a semiconductor substrate having a predetermined junction region and having a first interlayer dielectric layer formed thereon and having a plug contacting the junction region through a contact hole provided in the first interlayer dielectric layer; Forming a predetermined barrier pattern on the substrate to sufficiently cover the plug; Forming a second interlayer insulating film on an entire surface of the substrate to cover the barrier pattern; Etching the second interlayer insulating film to expose the surface of the barrier pattern to planarize the surface of the substrate; Forming a third interlayer insulating film on the planarized substrate; And Etching the third interlayer insulating film to expose the barrier pattern to form a concave structure; The barrier pattern is formed to have a width larger than the width of the concave-type structure, and the capacitor forming method, characterized in that acts as an etch stop film during the etching of the third interlayer insulating film. The method of claim 1, Forming a predetermined adhesive film on the sidewalls of the concave structure; Forming an upper electrode on a sidewall and a bottom of the concave structure in which the adhesive film is formed; Depositing a ferroelectric film and a second metal film for the upper electrode on the entire surface of the substrate on which the upper electrode is formed; And And forming a capacitor by patterning the second metal film and the ferroelectric film. The method according to claim 1 or 2, Forming the barrier pattern Sequentially forming a first diffusion barrier, an oxidation barrier, and a second diffusion barrier on the substrate; And And etching the second diffusion barrier, the oxidation barrier, and the first diffusion barrier. The method of claim 3, wherein And the first diffusion barrier layer is formed of one of a TiN film, a TaN film, a TiAlN film, a TiSiN film, a TaAlN film, a TaSiN film, a RuTiN film, and a RuTiO film. The method of claim 4, wherein The anti-oxidation film is a capacitor forming method, characterized in that for forming one film selected from Ir film, Ru film, RuTiN film, RuTaN film. The method of claim 4, wherein And the second diffusion barrier layer is formed of an IrOx film or a RuOx film. The method of claim 4, wherein The first diffusion barrier layer is formed of a TiN film, The second antioxidant film is formed of an Ir film, And the third diffusion barrier layer forms an IrOx film. The method of claim 7, wherein The TiN film is a capacitor forming method, characterized in that formed to a thickness of 50 to 1000Å. The method of claim 7, wherein And the Ir film is formed to a thickness of 100 to 2000 microns. The method of claim 7, wherein The method of forming a capacitor, wherein the IrOx film is formed to have a thickness of 50 to 2000 microns. The method of claim 3, wherein The etching method is a capacitor forming method characterized in that performed by the inclined etching. The method of claim 3, wherein The etching method is characterized in that the capacitor is formed using a separate hard mask. The method of claim 12, And a TiN film as said hard mask. The method of claim 2, The adhesive film is a capacitor forming method, characterized in that formed by Al ₂ O ₃ film. The method of claim 14, The Al ₂ O ₃ film is a capacitor forming method, characterized in that formed to a thickness of 50 to 500Å. The method of claim 2, And the first metal film is formed of one film selected from a film consisting of a Pt film, an Ir film, a Ru film, a RuOx film, and a combination thereof. The method of claim 16, And the first metal film is formed of a Pt film. The method of claim 2, The ferroelectric film is a capacitor forming method, characterized in that formed of one film selected from SBT film, SBTN film, PZT film and BLT film. The method of claim 2, And the second metal film is formed of a Pt film. The method of claim 2, And forming a predetermined heat treatment after forming the ferroelectric film and before forming the second metal film. The method of claim 20, The heat treatment is a capacitor formation method, characterized in that performed by the diffusion furnace or rapid heat treatment method. The method of claim 22, The heat treatment is a capacitor forming method characterized in that performed for 10 minutes to 5 hours in an O ₂ , N ₂ , Ar, O ₃ , He, Ne or Kr atmosphere at a temperature of 400 to 800 ℃. The method of claim 1, And the plug is formed of a conductive film such as a tungsten film, a TiN film, a TaN film, and a polysilicon film. The method of claim 1, And forming a silicide film between the plug and the junction region. The method of claim 24, The silicide layer is formed of a titanium silicide layer or a cobalt silicide layer.