KR20030032902A - Method and system for single-chip integration of 3D Y/C comb filter and interlace-to-progressive converter - Google Patents

Abstract

PURPOSE: A method for integrating a three-dimensional Y/C comb filter and an interlace/progressive converter into a single chip and a system thereof are provided to share the single frame buffer, and to cut down expenses by making the three-dimensional Y/C comb line filter and the interlace/progressive converter into the single-chip integrated configuration. CONSTITUTION: A single-chip integrated configuration includes an integrated chip for receiving and processing a video signal, and the integrated chip has a comb line filter(20), an interlace/progressive converter(IPC,25), and a plurality of data channels for communication between the video signal and a component for processing the signal. Furthermore, the single-chip integrated configuration is sometimes provided with a frame buffer(80) for storing one or more frames to be processed on the basis of the video signal, and the frame buffer is connected communicably to the integrated chip. The integrated chip is further provided with a memory controller(70) that adjusts a reading request and a writing request from the comb line filter to the frame buffer and a reading request and a writing request from the IPC to the frame buffer.

Description

Method and system for single-chip integration of 3D Y / C comb filter and interlace-to-progressive converter

The present invention relates generally to the field of display devices, and more particularly to methods and systems for integrating multiple video functions in a single integrated circuit chip. More specifically, the present invention relates to a method and system for single-chip integration of 3D Y / C comb filters and interlaced-sequential converters.

Conventional television monitors typically present video images in the form of a fast sequence of video fields, modified at high frequencies to create an illusion of motion. Television cameras and other sources of video generally do not produce full-frame images, but instead such video sources are typically, for example, each full (in interlaced systems). Generate a field consisting of about half of the lines of the frame image at 60 speeds per second. The alternating fields include alternating lines of video data. In other words, one field contains odd numbered lines, and the next field contains even numbered lines. Thus, each field of video can be identified as an "odd" field or an "even" field.

In a typical interlaced system, the sequence of video fields is thus alternating between odd fields and even fields. Conventional television monitors receiving a sequence of fields play each video field in sequence. Each field is displayed on the television screen on only half of the scan lines. For example, an odd field is first displayed using odd numbered scan lines, then an even field is displayed using even numbered scan lines, and so on. The television scans the raster across the screen from top left to top right while generating the first scan line and then returns the raster to the left edge of the screen to a position slightly below the original position. However, the position where the raster returns is not directly below the first scan line, but allows sufficient space to accommodate intervening scan lines on alternating fields. The raster then scans to the right edge of the screen to create a second scan line, and in this way continues to the bottom edge of the screen.

The distance between the scan lines is a function of the size of the monitor, but generally allows intervening scan lines (first scan lines in other fields) to be drawn after the end of the first field. The invisible return of the raster to the left edge of the screen after scanning each scan line is a fly-back or which occurs much faster than visible left-to-right lines. Horizontal refresh stage (fly-back or horizontal refresh stage). In this way, approximately 485 active scan lines can be generated (in the main US video format) to complete a single video frame, half of which is displayed in each field.

Once the lower edge of the screen is reached, the raster is invisibly returned to its original position in the upper left corner during the "vertical blanking interval" stage. Horizontal and vertical blanking interval stages are fast and invisible. For conventional television, this interlaced video scanning approach is a good compromise between refresh rate, vertical resolution and limited bandwidth.

However, methods of alternating odd and even frames used by conventional TV systems include line flicker, line crawl, dot crawl, limited horizontal resolution, flashing, and flashing. It is well known to have various disadvantages such as false color and large area flicker. To overcome these shortcomings of conventional TV signals, various techniques have been developed such as 3D comb filtering, interlaced-sequential conversion and field rate up-conversion to double field rate output. It became. However, 3D comb filters and interlaced-sequential converters ("IPC") require some fields of memory.

In a typical prior-art solution, the 3D comb filter and the IPC are separate, integrated circuit ("IC") chips. Thus, two separate memory chips (e.g. DRAM) are needed, respectively, for the 3D comb filter and the IPC. However, having separate memory chips for each of these components results in high system cost. In addition, as the number of individual components increases, so does the physical space required to house them. Thus, prior art systems have undesirable high manufacturing costs and large form factors associated with the systems.

Therefore, there is a need for a method and system architecture for integrating 3D Y / C comb filters and interlaced-sequential converters (or field rate up-converters) on a single IC chip, which can share a single frame buffer (memory). And, thus, reduce formation factors and manufacturing costs of the architecture.

A method for single-chip integration of interlaced-sequential converters and 3D Y / C comb filters, which on the one hand have small formation factors and reduced manufacturing costs and can provide the same or better performance than existing multi-chip solutions. And other needs for the system.

In accordance with the present invention, a 3D Y / C comb filter and substantially eliminates or reduces problems and disadvantages associated with prior art multi-chip methods and systems providing Y / C comb filtering and interlaced-sequential conversion. A method and system for single-chip integration of an interlaced-sequential converter is provided.

In particular, one embodiment of the present invention provides a single-chip integrated architecture, where the architecture includes an integrated chip that receives and processes a video signal, wherein the integrated chip comprises a comb filter, an interlaced-sequential converter and a video signal. And a plurality of data channels for communication of the processed components of the video signal. The architecture may further include a frame buffer that stores one or more frames processed from the video signal, where the frame buffer is communicatively connected to the integrated chip. The integrated chip may further include a comb filter and a memory controller that coordinates read and write requests from the IPC to the frame buffer. Alternatively, the memory controller may be a separate component separate from the integrated chip, which is communicatively connected to the integrated chip and the frame buffer. The plurality of data channels may further include pin-outs and connections for delivering signals to the integrated chip, both within the integrated chip and outside the integrated chip.

The technical advantage of the method and system architecture of integrating 3D Y / C comb filters and interlaced-sequential converters in a single IC chip is that they can share a single frame buffer, thus reducing both the architecture's formation factors and manufacturing costs. Let's do it.

Other technical advantages of the method and system for single-chip integration of 3D Y / C comb filters and interlaced-to-sequential converters are on the one hand the same as existing multi-chip solutions with small formation factors and reduced manufacturing costs. Or better performance.

A more complete understanding of the invention and its advantages can be obtained with reference to the following, in conjunction with the accompanying drawings, wherein like reference numerals designate like parts.

1 is a block diagram of a prior art multi-chip architecture providing comb filtering, interlaced-sequential conversion, and frame buffering.

2 is a simplified block diagram of an embodiment of a single-chip integrated system of the present invention.

* Description of the symbols for the main parts of the drawings *

20: 3D comb filter 25: interlaced-sequential converter

70: memory controller 80: frame buffer

Preferred embodiments of the invention are illustrated in the drawings, like numbers being used to refer to the same and corresponding parts of the various drawings.

The invention includes various embodiments of circuit architecture, 3D Y / C comb filter and interlaced-sequential converter (or alternatively field rate up-converter) integrated on a single chip, so that they will share a single frame buffer. Can be. Accordingly, embodiments of the present invention provide the advantages of a more compact shaping factor that takes up less space on the circuit board and provides reduced manufacturing costs without compromising performance over prior art methods and systems. can do. Unlike prior art solutions requiring multiple separate chip blocks, the present invention requires only a single frame buffer chip communicatively connected to a single chip integrating both a 3D Y / C comb filter and an IPC.

1 is a block diagram representation of a prior art multi-chip architecture 10 that includes two separate IC chips 60 and 65. IC chip 60 includes a memory controller 30 and a 3D comb filter 20 that performs Y / C separation. IC chip 65 includes an interlaced-to-sequential converter 25 and a second memory controller 30. Alternatively, interlaced-sequential converter 25 may instead include a field rate up-converter. The interlaced-sequential converter 25 provides, as an output signal, image information that is accumulated at the same time and is then output line by line or sequentially rather than in interlaced fashion. The result is an interlaced image with full vertical and horizontal resolution captured in a single rapid shutter event.

Architecture 10 may also include frame buffers 15. As shown in FIG. 1, the prior art architecture 10 requires one frame buffer 15 for each of the integrated circuit chips 60 and 65. Frame buffers 15 store video image frames for processing by the 3D comb filter 20 and the IPC 25. The memory controllers 30 (one for each frame buffer 15) are read / write requests between the 3D comb filter 20 and the frame buffer 15 and between the IPC 25 and the frame buffer 15. Adjust them. Frame buffers may be any suitable memory medium known to those skilled in the art, such as DRAM. Frame buffers 15 may also include frame buffers of different sizes, depending on the particular application. The frame buffers 15 may further comprise a plurality of memory chips to meet the memory requirements of a particular application.

The 3D comb filter 20 takes the composite video signal 50 as an input. The composite video signal 50 may be an NTSC signal, a PAL signal, or any other such signal known to those skilled in the art. NTSC stands for National Television Standards Committee, which defines a composite video signal at a refresh rate of 60 half-frames per second (interlaced). Each frame contains 525 lines and can contain 16 million different colors. Signal 50 may also be a signal for high definition-ready television, which may provide much better resolution than current television standards based on the NTSC standard. PAL stands for Phase Alternating Line, the dominant television standard in Europe. NTSC delivers 525 lines of resolution at 60 half-frames per second, while PAL delivers 625 lines at 50 half-frames per second. These specifications are well known in the art.

The 3D comb filter 20 receives the composite video signal 50 and separates the composite video signal 50 into component signals (discussed below) of the composite video signal. There are different types of comb filters, which vary widely in performance. For the purposes of this patent application, this description will focus on 3D comb filter technology.

The composite video signal 50 includes a luminance (brightness) signal and a chrominance (color) signal. In video technology, these are often referred to as Y and C signals, respectively. The C signal is a specially modulated combination of two other intermediate signals, such as the I and Q signals in the YIQ model and the Cb and Cr signals in the YCbCr model. These additional chroma signals are generated from, for example, the original red, green and blue (“RGB”) outputs of the video camera. Each of the color space models (eg, YIQ, YCbCr and YUV) uses a luminance value to represent basic black and white image information. Each model also uses two saturation (or chrominance) values to represent color information. Different color space models and their operation are well known to those skilled in the art. Video processing devices, such as television monitors, must utilize some form of Y / C separation to recover Y and C signal information from the composite video signal (eg, composite video signal 50).

Referring now to FIG. 1, the 3D comb filter 20 may be a 3D motion adaptive Y / C separation filter known in the art. Thus, the 3D comb filter 20 can process the same scan lines taken from successive video frames (inter-frame comb filtering) as opposed to intra-field comb filtering, which is within a single video field. Processing successive scan lines. The same scan lines from two consecutive frames are fed to the basic digital line comb filter in the 3D comb filter 20. If the image is static at the same location between frames (no color change or motion), the interframe comb filter can completely separate the Y and C information. If there is image motion or color changes between the frames, the corresponding lines in successive frames will have different Y / C content. In such a case, the interframe comb filter will generate faulty signal information. Therefore, the 3D Y / C separation filter should be motion adaptive and should select interframe comb filtering only in the absence of motion. Therefore, 3D motion adaptive Y / C separation comb filters can potentially make nearly perfect Y / C separation on static images.

The 3D comb filter 20 transmits the separated Y and C signals to the IPC 25 in the IC chip 65. Interlaced-to-sequential converter 25 takes interlaced Y and C signals and outputs them to a progressive (known as non-interlaced or sequential) signal 75, which is output to the display. Convert. Sequential signal 75 is associated with sequential scanning, which is a method of drawing image scan lines on a display in a manner similar to that of interlaced signals, but instead of splitting the video frame into two fields, one scan is an odd number The lines include the other and the even numbered scanned lines, and the complete frame is scanned from top to bottom in one process. Thus, IPC 25 converts the interlaced signal into an interlaced signal that can be output on a sequential display without artifacts. The sequential signal 75 output from the IPC 25 may be a signal in a suitable format for a display monitor such as NTSC or PAL.

2 is a block diagram representation of an embodiment of the method and system of the present invention for integrating a 3D Y / C comb filter and an IPC block on a single chip. The architecture 100 of FIG. 2 includes a single integrated chip 110 and a frame buffer 80. The integrated chip 110 may be a 3D comb filter 20, an IPC 25 and a shared memory controller 70 (which may be a motion adaptive Y / C isolated comb filter or other comb filters known to those skilled in the art). ). IPC 25 may be an operation and edge adaptive interlaced-sequential converter. Alternatively, IPC 25 may instead include a field rate-up converter.

The 3D comb filter 20 and the IPC 25 architecture 100 are both serviced by a shared memory controller 20. The shared memory controller 20 can steer read and write requests from the 3D Y / C comb filter 20 and the IPC, allowing the frame buffer 80 to be used by both. The shared memory controller 20 may be an integrated component of the integrated chip 110 or may be a separate component communicatively connected to the frame buffer 80 and the integrated chip 110. Frame buffer 80 may be any size frame buffer required for a particular use, and may include one or more DRAM chips or any other memory device known to those skilled in the art.

The single chip architecture 100 of FIG. 2 further provides pin-outs and connections between components on the single-integrated chip 110 and / or between external components in a manner known to those skilled in the art. May be included (not shown in FIG. 2). Pin-outs and connections can be configured as required for a particular use. The 3D comb filter 20 takes a composite video signal 50 as input as described in connection with FIG. Y and C signals transmitted to IPC 25 by 3D comb filter 20 are not shown in FIG. 2.

Embodiments of the invention may include the system shown in FIG. 2 and may also include a method of sharing a single frame buffer 80 between the comb filter 20 and the IPC 25. The method is characterized by the 3D comb filter 20, the IPC 25, and the processed components of the video signal and the video signal on the integrated chip 110 for receiving and processing a video signal such as the composite video signal 50. Communicatively connecting one or more data channels for communication. The method may further comprise communicatively connecting the frame buffer 80 to the integrated chip 110.

Embodiments of the method and system of the present invention provide the advantages of reduced formation factors and reduced manufacturing costs, while maintaining comparable or better performance than existing solutions. Reduced formation factor (reduced size) may allow for a reduction in size requirements of the device incorporating embodiments of the present invention. Similarly, embodiments of the present invention may provide savings in costs associated with prior art dual frame buffer requirements.

Embodiments of the method and system of the present invention include a memory buffer 80 comprising one or more available memory devices communicatively connected to the memory controller 70 for use of the 3D comb filter 20 and the IPC 25. It may include embodiments to. In such an embodiment, the memory controller 70 reads / writes from the 3D comb filter 20 and the IPC 25 to the frame buffer 80 to determine which memory device is accessed for a given read / write request. You can control (reconcile) requests. In a multi-memory device frame buffer 80 embodiment, the memory controller 70 may further control which memory device in the frame buffer 80 is accessed by the 3D comb filter 20 and the IPC 25. . In this way, the memory controller 70 can route requests from the 3D comb filter 70 and the IPC 25 to maximize speed and efficiency.

The frame buffer 80 may be any memory size required for the application, but typically for 3D motion adaptive Y / C separation, the frame buffer 80 is a video signal in the format used by the application implementing the present invention. It may be large enough to hold at least two video frames processed from 50. Frame buffer 80 is used to store video frames for average and motion detection purposes. For example, for the NTSC format, the frame is approximately 720 x 480 pixels. For a 720x480 pixel NTSC frame, the frame buffer 80 would have to contain four (1) four megabytes by 16 bit DRAM chips to store a 64 bit frame. Alternatively, two (1) 1 megabytes with 32 bit chips may be used. However, these memory requirements are well known in the art and can be implemented without undue testing. Thus, the size requirements for framebuffer 80 can be readily determined for a particular application.

Embodiments of the method and system of the present invention may be implemented with high definition (“HD”) or as part of a video processing system of progressive scan television. Indeed, embodiments of the method and system of the present invention may be implemented as part of a video signal processing system of any display system having both an IPC converter and a 3D comb filter.

Although the present invention has been described in detail herein with reference to exemplary embodiments, the description is to be understood only as illustrative and not in a limiting sense. Therefore, numerous changes in the details of the embodiments of the present invention and additional embodiments of the present invention will be apparent to and can be made by those skilled in the art relevant to the above description. Should be better understood. All such changes and additional embodiments are intended to be within the spirit and true scope of the invention as claimed below.

The method and system architecture for integrating 3D Y / C comb filters and interlaced-sequential converters (or field rate up-converters) in a single IC chip may share a single frame buffer (memory), thus forming and fabricating the architecture. Reduce costs.

Claims (34)

As a single-chip integrated architecture, An integrated chip for receiving and processing video signals, The integrated chip, Comb filter; Interlace-to-progressive converter ("IPC"); And And a plurality of data channels for communication of the video signal and the processed components of the video signal. The method of claim 1, Wherein the architecture further comprises a frame buffer for storing one or more frames processed from the video signal, the frame buffer communicatively connected to the integrated chip. The method of claim 2, The integrated chip further comprises a memory controller that coordinates read and write requests from the comb filter and the IPC to the frame buffer. The method of claim 2, The architecture further includes a memory controller that coordinates read and write requests from the comb filter and the IPC to the frame buffer, the memory controller being communicatively coupled to the integrated chip and the frame buffer. Chip integrated architecture. The method of claim 2, The frame buffer includes one or more memory devices. The method of claim 5, The memory devices are DRAM chips. The method of claim 2, The frame buffer size is large enough to store two or more frames. The method of claim 1, The comb filter is a 3D Y / C motion adaptive separation filter. The method of claim 1, Wherein the IPC is an operational and edge adaptive IPC. The method of claim 1, The plurality of data channels further comprise pin-outs and connections for delivering signals to the integrated chip, both within the integrated chip and outside the integrated chip. . The method of claim 1, Wherein the video signal is a composite video signal. The method of claim 11, Wherein the composite video signal is an interlaced video signal. As a single-chip integrated architecture, An integrated chip for receiving and processing video signals, The integrated chip, Comb filter; Field rate-up converter; And A one-chip integrated architecture comprising one or more data channels for communication of the video signal and the processed components of the video signal. The method of claim 13, Wherein the architecture further comprises a frame buffer for storing one or more frames processed from the video signal, the frame buffer communicatively connected to the integrated chip. The method of claim 14, Wherein the integrated chip further comprises a memory controller that coordinates read and write requests from the comb filter and the field rate-up converter to the frame buffer. The method of claim 14, The frame buffer includes one or more memory devices. The method of claim 16, The memory devices are DRAM chips. The method of claim 14, The frame buffer size is large enough to store two or more frames. A method of sharing a single frame buffer between a comb filter and an interlaced-to-sequential converter ("IPC"), To receive and process video signals, The comb filter; The IPC; And Communicatively connecting one or more data channels for communication of the video signal and the processed components of the video signal on one integrated chip; Communicatively connecting the frame buffer to the integrated chip. The method of claim 19, And the frame buffer stores one or more frames processed from the video signal. The method of claim 19, And communicatively connecting the comb filter and a memory controller that coordinates read and write requests from the IPC to the frame buffer on the integrated chip. The method of claim 19, And communicatively connecting a memory controller to the integrated chip and the frame buffer to coordinate read and write requests from the comb filter and the IPC to the frame buffer. The method of claim 19, And the frame buffer comprises one or more memory devices. The method of claim 19, And the memory devices are DRAM chips. The method of claim 19, And the frame buffer size is large enough to store two or more frames. The method of claim 19, And the comb filter is a 3D Y / C motion adaptive separation filter. The method of claim 19, And the IPC is an operational and edge adaptive IPC. The method of claim 19, The data channels further comprise pin-outs and connections for delivering signals to the integrated chip, both within the integrated chip and outside the integrated chip. As a dinyl-chip integrated architecture, An integrated chip for receiving and processing video signals, The integrated chip, 3D Y / C motion adaptive split comb filter; Interlaced-sequential converter ("IPC"); A memory controller that coordinates read and write requests from the comb filter and the IPC to a frame buffer, the frame buffer being communicatively connected to the integrated chip and capable of storing one or more frames processed from the video signal. A memory controller; And And a plurality of data channels for communication of the signal and the processed components of the signal. The method of claim 29, The frame buffer includes one or more memory devices. The method of claim 30, The memory devices are DRAM chips. The method of claim 29, The frame buffer size is large enough to store two or more frames. The method of claim 29, Wherein the IPC is an operational and edge adaptive IPC. The method of claim 29, The plurality of data channels further include pin-outs and connections for delivering signals to the integrated chip, both within the integrated chip and outside the integrated chip.