JP2003189262A - Method for integrating three-dimensional y/c comb line filter and interlace/progressive converter into single chip and system thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a three-dimensional Y/C comb line filter and an interlace/ progressive converter into a single-chip integrated configuration. <P>SOLUTION: This single-chip integrated configuration is provided with an integrated chip for receiving and processing a video signal, and the integrated chip has a comb line filter, the interlace/progressive converter (IPC), and a plurality of data channels for communication between the video signal and a component for processing the signal. Furthermore, the single-chip integrated configuration is sometimes provided with a frame buffer for storing one or more frames to be processed on the basis of the video signal, and the frame buffer is connected communicably to the integrated chip. The integrated chip is further provided with a memory controller that adjusts a reading request and a writing request from the comb line filter to the frame buffer and a reading request and a writing request from the IPC to the frame buffer. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates generally to the field of displays, and more particularly to a method and system for integrating multiple video functions on a single integrated circuit chip. More particularly, the present invention relates to a single-chip integration method and system for a three-dimensional (3D) Y / C comb filter and interlaced progressive converter.

[0002]

2. Description of the Prior Art Conventional television monitors typically present video images in the form of high speed, continuous video fields, with frequent changes to produce the illusion of motion. Television cameras and other video sources typically do not produce full-frame images, but instead, such video sources typically consist of about half the number of lines in a full-frame image. Generate fields (at an interlaced system) at a rate of 60 fields per second. Every other field contains every other line of video data. In other words, when one field contains odd-ordered lines, the next field contains even-ordered lines. Therefore, each field of the video can be identified as an "odd" field or an "even" field.

In a typical interlaced system, the sequence of video fields thus alternates between odd and even fields. A conventional television monitor that receives such a continuous field plays a series of video fields one at a time. When displayed on the television screen for each field, only half of the scan lines are displayed. For example, first, odd-numbered scan lines are used to display odd-numbered fields, then even-numbered field lines are used to display even-numbered fields, and so on. The television scans the raster across the screen from upper left to upper right while at the same time producing the first scan line, then back up the raster to the left edge of the screen, slightly below its original position. However, although the position where the raster has returned is not directly below the first scanning line, the intervening scanning lines for every other field can be accommodated in a sufficient space. Then
The raster is scanned across the right edge of the screen, producing a second scan line, and in this manner, the bottom edge of the screen.

The distance between scan lines is a function of monitor size, but in general the intervening scan line (the first scan line of another field) will be placed after the completion of the first field. Can be pulled. Invisible to the left edge of the screen after scanning each scan line, but returning the raster is called a flyback or horizontal refresh stage, which is more than a visible left-to-right line. Is happening much faster. In this manner, about 485 active scan lines are generated (in the predominant US video format) to complete one video frame, half of which is displayed in each field.

When the bottom edge of the screen is reached, the raster is invisibly returned to its original position in the upper left corner during the "vertical blanking period" stage. The horizontal blanking stage and the vertical blanking stage are fast and invisible. For conventional televisions, this interlaced video scanning approach is the result of a good compromise between vertical refresh rate, vertical resolution, and limited bandwidth.

However, the method of alternately switching between the odd frame and the even frame, which is adopted in the conventional TV system, is the flicker of the line, the slow sweep of the line, the slow sweep of the point, the limited horizontal resolution, and the intermittent pseudo color. It is also well known to have various defective states such as static insertion, large area flicker and the like. Three-dimensional comb filtering,
Various techniques such as interlaced progressive conversion, field rate doubling conversion to ascending field rate output, have been developed to overcome the above drawbacks of conventional TV signals. However, a three-dimensional comb filter and an interlaced progressive converter (hereinafter "IP
Both are called C ") and both require multiple fields of memory.

In a typical prior art solution, the three-dimensional comb filter and the IPC are separate integrated circuit (IC) chips. Therefore, two separate memory chips (eg DRAM), one for each 3D comb filter and IPC
is necessary. However, system costs are high as a result of such components providing their own separate memory chips. Moreover, as the number of discrete components increases, so does the physical space required to house them. Thus, prior art systems have undesirably high manufacturing costs and the large form factor associated with each system.

[0008]

Therefore, a method of integrating a three-dimensional Y / C comb filter and an interlaced progressive converter (or a field rate up converter) on a single IC chip and a system configuration thereof have been established. There is a need to allow these components to share one frame buffer (memory), thus reducing both system configuration form factor and manufacturing costs.

A three-dimensional Y / C comb filter capable of delivering performance equal to or better than existing multi-chip solutions, while achieving a small form factor and reduced manufacturing costs. What is also needed is a method and system for integrating an interlaced progressive converter with a single chip.

[0010]

According to the present invention, three-dimensional
A method and system for single-chip integration of a Y / C comb filter and an interlaced progressive converter is presented, which method and system provide a Y / C comb filtering and interlaced progressive conversion prior art multi-chip method. And substantially eliminates or reduces the disadvantages and problems associated with multi-chip systems.

In particular, one embodiment of the present invention provides a single chip integrated configuration, which includes an integrated chip for receiving and processing video signals, the integrated chip including a comb filter and an interlaced progressive conversion. A vessel,
A plurality of data channels for communication between the video signal and the components on which the video signal is processed. The arrangement further comprises a frame buffer for storing one or more frames processed based on the video signal, the frame buffer communicatively connected to the integrated chip. The integrated chip may further include a memory controller that coordinates read and write requests from the comb filter to the frame buffer and read and write requests from the IPC to the frame buffer. Alternatively, the memory controller may be a separate component from the integrated chip that is communicatively coupled to each of the integrated chip and the frame buffer. The plurality of data channels may further comprise pin outputs and connections within the integrated chip and external to the integrated chip for communicating with the integrated chip by signals.

The technical advantage of the method and system configuration of integrating a three-dimensional Y / C comb filter and an interlaced progressive converter on a single IC chip is that they can form a system configuration because they can share a frame buffer. • To reduce both factor and manufacturing costs.

Another technical advantage of the method and system for single-chip integration of a three-dimensional Y / C comb filter and an interlaced progressive converter is that they realize a small form factor and reduced manufacturing costs. That is, it can provide the same level of performance or better than existing multi-chip solutions.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A more complete understanding of the present invention and an advantage of the present invention can be understood if understood with reference to the following description in connection with the accompanying drawings. The reference numbers indicate the same functional parts.

The preferred embodiments of the present invention are illustrated in the drawings in which the same numbers are used to refer to the same and corresponding parts of the various figures.

The present invention integrates a three-dimensional Y / C comb filter and an interlaced progressive converter (or, as an alternative, a field rate up converter) on a single chip, and each component is a frame buffer. It includes various embodiments of circuit configurations that enable sharing of the same. Accordingly, embodiments of the present invention include
The advantages of a smaller form factor can be provided that occupy less space on the circuit board and reduce manufacturing costs without compromising performance compared to prior art methods and systems. Unlike prior art solutions that require a large number of separate chip blocks, the present invention allows one frame buffer chip to be communicated to a single chip that integrates both the 3D Y / C comb filter and the IPC. You just have to connect to.

FIG. 1 shows two separate IC chips 60,65.
1 is a block diagram of a prior art multi-chip configuration 10 having The IC chip 60 includes a three-dimensional comb filter 20 that performs Y / C separation and a memory controller 30. The IC chip 65 includes an interlace / progressive converter 25 and a second memory controller 30. Alternatively, the interlace progressive converter 25 may be composed of a field rate up converter. Interlaced
The progressive converter 25 provides the picture information as an output signal, which is accumulated at the same time and then output line by line, or continuously, rather than in interlaced fashion. The result is an interlaced image, with full vertical and horizontal resolution acquired in one quick shutter event.

The configuration 10 may also include a frame buffer 15. As illustrated in FIG. 1, the prior art arrangement 10 requires one frame buffer 15 for each integrated circuit chip 60, 65. The frame buffer 15 is a three-dimensional comb filter 20 and IP
Store the video image frame to be processed by C25.
The memory controller 30 (one for each of the frame buffers 15) coordinates read and write requests between the three-dimensional comb filter 20 and the frame buffers 15 as well as read and write requests between the IPC 25 and the frame buffers 15. Coordinate write requests. The frame buffer 15 may be any suitable memory medium known to those skilled in the art, for example DRAM.
In addition, the frame buffer 15 will depend on the particular application.
It may have a plurality of frame buffers of different sizes. The frame buffer 15 may further include multiple memory chips to meet the memory requirements of a particular application.

The three-dimensional filter 20 receives the composite video signal 50 as an input. The composite video signal 50 may be an NTSC signal, a PAL signal, or any other signal known to those skilled in the art. NT
SC is an abbreviation of National Television Standards Committee, which defines a composite video signal at a refresh rate of 60 half frames (interlaced type) per second. Each frame contains 525 lines and can contain 160,000 different colors. The signal 50 may also be a high definition television signal capable of providing much better resolution than current television standards based on the NTSC standard. PAL is Phase Alternating Line
Stands for and is the dominant television standard in Europe. NT
SC is 525 at a rate of 60 half frames per second
Carrying two separate scan lines, PAL carries 625 lines at a rate of 50 half frames per second. Such specifications are well known in the art.

The three-dimensional comb filter 20 receives the composite video signal 50 and outputs the composite video signal 50.
Is separated into its multiple component signals (as discussed later). There are different types of comb filters and their performance varies widely. For purposes of this patent application, the present description will focus on three-dimensional comb filter technology.

The composite video signal 50 is composed of a luminance (brightness) signal and a color (color) signal. In video technology, these component signals are often referred to as the Y and C signals, respectively. The C signal is a specially modulated combination of two different intermediate signals,
For example, I and Q signals of YIQ model and C of YCbCr model
It is a combination like b signal and Cr signal. Such an additional saturation signal is the primary color red of a video camera,
Created from each color output of green and blue (RGB). Color space models (eg YIQ, YCbCr, and YUV) are
Each uses a brightness value to indicate basic black image information and white image information. These models also use two chromatic values (i.e., color values) to draw color information, although the saturation values are defined differently. Different color space models and their respective behaviors are known to those skilled in the art. Video processing equipment, such as a television monitor, uses a composite video signal (eg, composite video signal 5
To recover the Y and C signal information from 0) some form of Y / C separation must be employed.

Returning now to FIG. 1, the three-dimensional comb filter 20 is a three-dimensional motion adaptive type as is known in the art.
It may be a Y / C separation filter. Thus, the three-dimensional comb filter 20 can process the same scan lines obtained from successive video frames, as opposed to intra-field comb filtering, which involves processing successive scan lines within one video field. (In-frame comb filtering). The same scan line from two consecutive frames is sent to the basic digital line comb filter inside the three-dimensional comb filter 20. If the image is stationary at the same position between frames (no movement or color change), the in-frame comb filter uses Y information and C
Information can be completely separated. Corresponding lines in successive frames are different if there is image motion or image color change between frames
Has Y / C content. In such a case, the intra-frame comb filter produces false signal information. Therefore, the 3D Y / C separation filter must be motion adaptive and the intraframe comb filtering should be selected only when there is no motion. Therefore, the 3D motion adaptive Y / C separation comb filter is almost perfect for still images.
Has the potential to perform Y / C separation.

The three-dimensional comb filter 20 transfers the separated Y signal and C signal to the IPC 25 inside the IC chip 65. The interlace / progressive converter 25 receives interlaced Y and C signals, converts these signals into progressive signals (also known as non-interlaced or continuous signals) 75, and displays the converted signals. Output to the device. The continuous signal 75 is associated with continuous scanning, which is a method of drawing an image scan line on a display device in a manner similar to that of interlaced signals, in which two video frames are used. It is divided into two fields, one containing odd numbered scan lines and the other containing even numbered scan lines, so that one complete frame is scanned from top to bottom in one pass operation. Therefore, the IPC 25 converts the interlaced signal into a non-interlaced signal that is output on continuous display without artifacts. The continuous signal 75 output from the IPC 25 is a format suitable for a display monitor, NTSC or
It may be a signal such as PAL.

FIG. 2 shows a three-dimensional Y / C comb filter and IPC.
FIG. 3 is a block diagram of an embodiment of the method and system of the present invention in which blocks and are integrated on a single chip. The configuration 100 of FIG. 2 comprises a single integrated chip 110 and a frame buffer 80. The integrated chip 110 includes a three-dimensional comb filter 20 (which may be a motion adaptive Y / C separation comb filter or other comb filters known to those skilled in the art), an IPC 25, and a shared memory. It is composed of a controller 70. IPC25
May be a motion and edge adaptive interlaced progressive converter. Alternatively, IPC 25 may be a field rate up converter.

Three-dimensional comb filter 20 and IPC 25
Both components of the configuration 100 are subordinately assisted by the shared memory controller 20. The shared memory controller 20 can coordinate read and write requests from the 3D Y / C comb filter 20 and from the IPC 25 so that the frame buffer 80 is used by both. Shared memory controller 20 may be an integrated component of integrated chip 110, or may be a separate component communicatively coupled to integrated chip 110 and frame buffer 80. The frame buffer 80 may be any size frame buffer as required by the particular application, may be composed of more than one DRAM chip, or may be of ordinary skill in the art. It may consist of any other memory device known in the art.

The single chip configuration of FIG. 2 is a single integrated chip 1
Pin outputs and connections are provided between components on 10 and / or external components in a manner known to those skilled in the art (although not illustrated in FIG. 2). The pin outputs and connections need only be configured to meet the requirements of a particular application. The three-dimensional comb filter 20 includes a composite video signal 50, as described in connection with FIG.
Can be received as input. The Y and C signals transferred to the IPC 25 by the 3D comb filter 20 are not illustrated in FIG.

Embodiments of the present invention may include a system such as that illustrated in FIG. 2, and one frame buffer 8 between the comb filter 20 and the IPC 25.
A method of sharing 0 may be provided. The method is for receiving and processing a video signal, such as the video signal 50, on the integrated chip 110, the three-dimensional filter 20, the IPC 25, the video signal and the components that process the video signal. And the step of communicatively connecting to each other one or more data channels for communication with. The method may further include communicatively connecting the frame buffer 80 to the integrated chip 110.

Embodiments of the method and system of the present invention maintain the same or better performance than existing solutions, while at the same time providing the advantages of lower form factor and lower manufacturing costs. The lower form factor (smaller size) allows for reduced dimensional requirements for equipment incorporating embodiments of the present invention. Similarly, embodiments of the present invention may provide cost savings associated with prior art dual frame buffer requirements.

In an embodiment of the method and system of the present invention, the frame buffer 80 is communicatively coupled to a memory controller 70 for use with the three-dimensional comb filter 20 and the IPC 25. The embodiment includes the following. In such an embodiment, memory controller 70 controls (optional) read and write requests from three-dimensional comb filter 20 and from IPC 25 to determine which memory device is accessed for a given read or write request. Can be determined. In an embodiment of frame buffer 80 having a multiple memory device configuration, memory controller 70 includes three-dimensional comb filter 20 and IPC2.
5, it is possible to further control which memory device of the frame buffer 80 has been accessed. In this way, the memory controller 70 can organize the procedural steps required by the three-dimensional comb filter 70 and the IPC 25 to maximize speed and efficiency.

The frame buffer 80 may have any memory size required for each application, but typically for three-dimensional motion adaptive Y / C separation,
The frame buffer 80 must be of sufficient size to hold at least two video frames processed on the basis of the video signal 50 in the format utilized by the application implementing the invention. The frame buffer 80 is used to store video frames for averaging and motion detection purposes. For example, for the NTSC format, the frame is approximately 720 x 480 pixels.
For NTSC frames of 720 x 480 pixels, the frame buffer 80 will store 4 64-bit frames.
It must consist of 1 megabyte x 16-bit DRAM chip. As an alternative, two 1 megabyte x 32 bit chips may be employed. However, such memory requirements are known in the art and can be achieved without undue experimentation. Therefore, the size requirements of the frame buffer 80 can be easily determined for each particular application.

Embodiments of the method and system of the present invention can be implemented as part of a video processing system for high definition (HD) or as a progressive scan television. In fact, embodiments of the method and system of the present invention, whether for any display system that includes both an IPC converter and a three-dimensional comb filter,
It can be implemented as part of the video signal processing system.

Although the present invention has been described in detail herein with reference to exemplary embodiments, it is understood that the description is merely illustrative and should not be construed in a limiting sense. Should be. Thus, numerous modifications of the embodiments of the invention and the details of further embodiments of the invention will be apparent to those of ordinary skill in the art in view of the present description, and such modifications will occur to those skilled in the art. It should be further understood that this can be done. All such modifications and alternative embodiments are considered to be within the spirit and true scope of the invention as defined by the appended claims.

[Brief description of drawings]

FIG. 1 is a block diagram of a prior art multi-chip configuration that provides comb filtering, interlaced progressive conversion, and frame buffer operation.

FIG. 2 is a schematic block diagram of an embodiment of a single chip integrated system of the present invention.

[Explanation of symbols]

10 chip configuration 15 frame buffer 20 3D comb filter 25 interlaced progressive converter 30 memory controller 50 composite video signal 60 IC chip 65 IC chip 75 progressive signal 80 frame buffer 100 configurations 110 integrated chips

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[Procedure amendment]

[Submission date] December 6, 2002 (2002.12.
6)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

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Claims (34)

[Claims] 1. A single-chip integrated structure, comprising an integrated chip for receiving and processing a video signal, the integrated chip comprising a comb filter, an interlaced progressive converter (IPC), and the video signal. A single chip integrated arrangement having a plurality of data channels for communication between and a component whose signal is processed. 2. The single-chip integrated structure further comprises a frame buffer for storing one or more frames processed based on the video signal, the frame buffer being communicatively connected to the integrated chip. The single chip integrated configuration of claim 1, wherein: 3. The integrated chip further comprises a memory controller for coordinating read and write requests from the comb filter to the frame buffer and read and write requests from the IPC to the frame buffer. The single-chip integrated structure according to claim 2. 4. The single chip integrated configuration further comprises a memory controller for coordinating read and write requests from the comb filter to the frame buffer and read and write requests from the IPC to the frame buffer. The single-chip integrated configuration according to claim 2, wherein the memory controller is communicatively connected to the integrated chip and also communicatively connected to the frame buffer. 5. The single chip integrated arrangement of claim 2, wherein the frame buffer comprises one or more memory devices. 6. The single chip integrated structure of claim 5, wherein the memory device is a DRAM chip. 7. The single chip integrated structure according to claim 2, wherein the size of the frame buffer is large enough to store two or more frames. 8. The single-chip integrated structure according to claim 1, wherein the comb filter is a three-dimensional Y / C motion adaptive separation filter. 9. The single-chip integrated configuration of claim 1, wherein the IPC is a motion and edge adaptive IPC. 10. The plurality of data channels further comprises pin outputs and connections for communicating signals with the integrated chip, both within the integrated chip and external to the integrated chip. 1. A single-chip integrated structure described in 1. 11. The single-chip integrated structure of claim 1, wherein the video signal is a composite video signal. 12. The single chip integrated arrangement of claim 11, wherein the composite video signal is an interlaced video signal. 13. A single-chip integrated structure, comprising an integrated chip for receiving and processing a video signal, the integrated chip comprising a comb filter, a field rate up converter, a video signal and the processed signal. A single-chip integrated structure having one or more data channels for communication with components. 14. The single chip integrated configuration further comprises a frame buffer for storing one or more frames processed based on the video signal, the frame buffer being communicatively coupled to the integrated chip. ing,
A single chip integrated configuration according to claim 13. 15. The integrated chip further comprises a memory controller for coordinating read and write requests from the comb filter to the frame buffer and read and write requests from the IPC to the frame buffer. The single chip integrated structure according to claim 14. 16. The single chip integrated arrangement of claim 14, wherein the frame buffer comprises one or more memory devices. 17. The memory device is a DRAM chip,
The single chip integrated structure according to claim 16. 18. The single chip integrated structure according to claim 14, wherein the size of the frame buffer is large enough to store two or more frames. 19. A method of sharing a frame buffer between a comb filter and an interlaced progressive converter (IPC), which comprises receiving and processing a video signal on a single integrated chip. For the purpose, the comb filter and the IPC
And one or more data channels for communication between the video signal and the component on which the video signal is processed,
A method comprising: communicatively connecting to each other; communicatively connecting the frame buffer to an integrated chip. 20. The method of claim 19, wherein the frame buffer stores one or more frames processed based on the video signal. 21. A memory controller communicatively connected to the integrated chip for coordinating read and write requests from the comb filter to the frame buffer and read and write requests from the IPC to the frame buffer. The method according to claim 1, further comprising:
9. The method according to 9. 22. A memory controller is provided with the integrated chip for the purpose of coordinating a read request and a write request from the comb filter to the frame buffer and a read request and a write request from the IPC to the frame buffer. 20. The method of claim 19, further comprising communicatively connecting to each of the frame buffers. 23. The method of claim 19, wherein the frame buffer comprises one or more memory devices. 24. The memory device is a DRAM chip,
The method according to claim 19. 25. The method of claim 19, wherein the size of the frame buffer is large enough to store more than one of the frames. 26. The method of claim 19, wherein the comb filter is a three-dimensional Y / C motion adaptive separation filter. 27. The IPC is a motion and edge adaptive IPC.
20. The method of claim 19, wherein 28. The plurality of data channels further comprises pin outputs and connections for communicating signals with the integrated chip, both within the integrated chip and external to the integrated chip. The method according to 19. 29. A single-chip integrated structure, comprising an integrated chip for receiving and processing a video signal, the integrated chip comprising a three-dimensional Y / C motion adaptive separation comb filter, and an interlaced progressive. A converter (IPC); and a memory controller for coordinating read and write requests from the comb filter to the frame buffer and read and write requests from the IPC to the frame buffer. It is communicatively connected to an integrated chip and is capable of storing one or more frames processed based on a video signal, said integrated chip comprising a video signal and a component on which the signal is processed. A single-chip integrated configuration further comprising multiple data channels for communication to and from. 30. The single chip integrated arrangement of claim 29, wherein the frame buffer comprises one or more memory devices. 31. The memory device is a DRAM chip,
A single chip integrated arrangement according to claim 30. 32. The single chip integrated configuration according to claim 29, wherein the size of the frame buffer is large enough to store two or more frames. 33. The IPC is a motion and edge adaptive IPC.
30. The single chip integrated configuration of claim 29, wherein: 34. The plurality of data channels further comprises pin outputs and connections for communicating signals with the integrated chip, both within the integrated chip and external to the integrated chip. Item 31. A single-chip integrated structure according to Item 29.