KR20030028974A - Thin film transistor liquid crystal display - Google Patents

Thin film transistor liquid crystal display Download PDF

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KR20030028974A
KR20030028974A KR1020010061431A KR20010061431A KR20030028974A KR 20030028974 A KR20030028974 A KR 20030028974A KR 1020010061431 A KR1020010061431 A KR 1020010061431A KR 20010061431 A KR20010061431 A KR 20010061431A KR 20030028974 A KR20030028974 A KR 20030028974A
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liquid crystal
gate lines
thin film
common electrode
pixel
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KR1020010061431A
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Korean (ko)
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배석
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비오이 하이디스 테크놀로지 주식회사
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1335Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509Filters, e.g. light shielding masks
    • G02F1/133512Light shielding layers, e.g. black matrix
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1335Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509Filters, e.g. light shielding masks
    • G02F1/133514Colour filters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE: A thin film transistor liquid crystal display device is provided to restrain signal delay in gate lines by parasitic capacity between the gate lines and common electrodes, thereby improving the quality of a TFT-LCD. CONSTITUTION: A plurality of gate lines(2) and data lines cross each other on a first glass substrate. An array substrate includes thin film transistors at cross parts, and pixel electrodes at pixel areas. Black matrix is arranged on a second glass substrate corresponding to the gate lines and the data lines. Color filters are arranged on a color filter substrate corresponding to the pixel electrodes. A plate type common electrode(12) is formed on the black matrix and the pixel electrodes. The array substrates and the color filter substrates are bonded by interposing a liquid crystal layer including a plurality of liquid crystal particles. The common electrode includes dot type slits(S) corresponding to the gate lines.

Description

박막 트랜지스터 액정표시장치{THIN FILM TRANSISTOR LIQUID CRYSTAL DISPLAY}Thin Film Transistor Liquid Crystal Display {THIN FILM TRANSISTOR LIQUID CRYSTAL DISPLAY}

본 발명은 박막 트랜지스터 액정표시장치에 관한 것으로, 보다 자세하게는, 상부기판과 하부기판 사이에서 형성되는 원치않은 기생 용량에 의한 신호 지연을억제시킬 수 있는 박막 트랜지스터 액정표시장치에 관한 것이다.The present invention relates to a thin film transistor liquid crystal display device, and more particularly, to a thin film transistor liquid crystal display device capable of suppressing signal delay due to unwanted parasitic capacitance formed between an upper substrate and a lower substrate.

박막 트랜지스터 액정표시장치(이하, TFT-LCD)는 경량, 박형 및 저소비 전력 등의 특성을 갖기 때문에 CRT를 대신하여 각종 정보 기기의 단말기 또는 비디오 기기 등에 사용되고 있다.Thin film transistor liquid crystal display devices (hereinafter TFT-LCDs) have characteristics such as light weight, thinness, and low power consumption, and thus are used in terminals or video devices of various information devices instead of CRTs.

이러한 TFT-LCD는 어레이 기판(array substrate)과 컬러필터 기판(color filter substrate) 사이에 액정층이 개재된 구조로 이루어져 있으며, 각 화소에 구비된 박막 트랜지스터에 의해서 상기 각 화소가 개별적으로 구동되는 것에 의해서 소정의 화상을 표시하게 된다.The TFT-LCD has a structure in which a liquid crystal layer is interposed between an array substrate and a color filter substrate, and each pixel is individually driven by a thin film transistor provided in each pixel. By this, a predetermined image is displayed.

보다 자세하게, 상기 TFT-LCD는 제1유리기판 상에 단위 화소 영역들을 한정하도록 수 개의 게이트 라인 및 데이터 라인이 교차 배열되고, 각 교차부에는 박막 트랜지스터가 구비되며, 각 화소 영역 내에는 화소전극이 배열된 구조의 어레이 기판과, 제2유리기판 상에 게이트 라인 및 데이터 라인에 대응해서 블랙 매트릭스(Black Matrix)가 구비되고, 상기 화소와 대응해서 컬러필터가 배열되며, 상기 블랙 매트릭스와 화소전극 상에 ITO로 이루어진 플레이트 형상의 공통전극이 형성된 구조의 컬러필터 기판이 수 개의 액정분자들을 포함한 액정층의 개재하에 합착되어 이루어진 구조이다.In more detail, the TFT-LCD includes several gate lines and data lines intersecting to define unit pixel regions on a first glass substrate, and thin film transistors are provided at each crossing portion, and pixel electrodes are included in each pixel region. A black matrix is provided on the array substrate of the arranged structure and the second glass substrate in correspondence with the gate line and the data line, and color filters are arranged in correspondence with the pixel, and on the black matrix and the pixel electrode. A color filter substrate having a structure in which a plate-shaped common electrode made of ITO is formed is bonded to each other under interposition of a liquid crystal layer including several liquid crystal molecules.

그러나, 전술한 종래의 TFT-LCD는 액정층을 사이에 두고 어레이 기판과 컬러필터 기판 사이에서 원치않은 기생용량이 발생되는 바, 이러한 기생용량으로 인해 신호 전달에 어려움을 갖게 되고, 그래서, 화면 품위가 저하되는 문제점이 있다.However, in the conventional TFT-LCD described above, unwanted parasitic capacitance is generated between the array substrate and the color filter substrate with the liquid crystal layer interposed therebetween, which causes difficulty in signal transmission. There is a problem that is lowered.

예컨데, 도 1 및 도 2에 도시된 바와 같이, 액정층(30)을 사이에 두고 어레이 기판(10)의 게이트 라인(2)과 컬러필터 기판(20)의 공통전극(11) 사이에서 원치않는 기생용량(Cgc)이 발생되며, 이러한 기생용량(Cgc)에 의해서 게이트 라인(2)에 실려지는 어드레스신호의 신호지연이 야기되고, 이 결과로, 크로스토크(crosstalk) 및 플리커(flicker) 등의 현상이 발생되어, 결국, TFT-LCD의 화면 품위가 야기된다. 도 1 및 도 2에서, 미설명된 도면부호 1,11은 유리기판, 3은 게이트 절연막을 나타낸다.For example, as shown in FIG. 1 and FIG. 2, an undesired gap between the gate line 2 of the array substrate 10 and the common electrode 11 of the color filter substrate 20 with the liquid crystal layer 30 interposed therebetween. The parasitic capacitance Cgc is generated, and the signal delay of the address signal carried on the gate line 2 is caused by the parasitic capacitance Cgc. As a result, crosstalk, flicker, and the like are caused. The phenomenon occurs, and eventually, the screen quality of the TFT-LCD is caused. 1 and 2, reference numerals 1 and 11, which are not described, denote glass substrates, and 3 denote gate insulating films.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 게이트 라인과 공통전극 사이에서 발생되는 기생용량에 의한 화면 품위 저하를 억제시킬 수 있는 TFT-LCD를 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a TFT-LCD capable of suppressing deterioration of screen quality due to parasitic capacitance generated between a gate line and a common electrode.

도 1은 종래의 박막 트랜지스터 액정표시장치를 개략적으로 도시한 평면도.1 is a plan view schematically showing a conventional thin film transistor liquid crystal display device.

도 2는 도 1의 A-A′선을 따라 절단하여 나타낸 단면도.FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1. FIG.

도 3은 본 발명의 실시예에 따른 박막 트랜지스터 액정표시장치를 개략적으로 도시한 평면도.3 is a plan view schematically illustrating a thin film transistor liquid crystal display device according to an exemplary embodiment of the present invention.

도 4는 도 3의 B-B′선을 따라 절단하여 도시한 단면도.4 is a cross-sectional view taken along the line BB ′ of FIG. 3.

- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-

1,11 : 유리기판 2 : 게이트 라인1,11 glass substrate 2: gate line

3 : 게이트 절연막 10 : 어레이 기판3: gate insulating film 10: array substrate

12 : 공통전극 20 : 컬러필터 기판12 common electrode 20 color filter substrate

30 : 액정층 S : 슬릿30: liquid crystal layer S: slit

상기와 같은 목적을 달성하기 위한 본 발명의 TFT-LCD는, 단위 화소 영역들을 한정하도록 수 개의 게이트 라인 및 데이터 라인이 교차 배열되고, 각 교차부에는 박막 트랜지스터가 구비되며, 각 화소 영역 내에는 화소전극이 구비된 어레이 기판과, 상기 게이트 라인 및 데이터 라인에 대응해서 블랙 매트릭스가 구비되고, 상기 화소전극과 대응해서 컬러필터가 배열되며, 상기 블랙 매트릭스와 화소전극 상에는 플레이트 형상의 공통전극이 형성된 컬러필터 기판이 액정층의 개재하에 합착되어 이루어진 TFT-LCD에 있어서, 상기 각 게이트 라인과 대응하는 공통전극에 부분에 적어도 하나 이상의 도트형 슬릿(slit)이 구비된 것을 특징으로 한다.In the TFT-LCD of the present invention for achieving the above object, several gate lines and data lines are intersected to define unit pixel regions, thin film transistors are provided at each intersection portion, and pixels are included in each pixel region. An array substrate having electrodes, a black matrix corresponding to the gate line and the data line, a color filter arranged to correspond to the pixel electrode, and a color having a plate-shaped common electrode formed on the black matrix and the pixel electrode. A TFT-LCD in which a filter substrate is bonded to each other under an intervening liquid crystal layer is characterized in that at least one dot-shaped slit is provided at a portion of the common electrode corresponding to each of the gate lines.

본 발명에 따르면, 게이트 라인과 대응하는 공통전극에 수 개의 슬릿을 구비시키기 때문에 기생용량을 최소화시킬 수 있으며, 그래서, 신호 지연에 의한 화면 품위의 저하를 억제시킬 수 있다.According to the present invention, since several slits are provided in the common electrode corresponding to the gate line, the parasitic capacitance can be minimized, so that the degradation of the screen quality due to the signal delay can be suppressed.

(실시예)(Example)

이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명의 실시예에 따른 TFT-LCD에서의 게이트 라인 및 공통전극을 도시한 평면도이고, 도 4는 도 3의 B-B′선을 따라 절단하여 나타낸 단면도이다. 여기서, 도 1 및 도 2와 동일한 부분은 동일한 도면부호로 나타낸다.3 is a plan view illustrating a gate line and a common electrode in a TFT-LCD according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along the line BB ′ of FIG. 3. 1 and 2 are denoted by the same reference numerals.

도 3 및 도 4를 참조하면, 본 발명의 TFT-LCD는 제1유리기판(1) 상에 단위 화소 영역들을 한정하도록 수 개의 게이트 라인(2) 및 데이터 라인(도시안됨)이 교차 배열되고, 각 교차부에는 박막 트랜지스터(도시안됨)가 구비되며, 각 화소 영역 에는 화소전극(도시안됨)이 구비된 어레이 기판(10)과, 제2유리기판(11) 상에 상기 게이트 라인(2) 및 데이터 라인에 대응해서 블랙 매트릭스(도시안됨)가 구비되고, 상기 화소전극과 대응해서 컬러필터(도시안됨)가 배열되며, 상기 블랙 매트릭스와 화소전극 상에는 플레이트 형상의 공통전극(12)이 형성된 컬러필터 기판(20)이 수 개의 액정분자들을 포함하는 액정층(30)의 개재하에 합착되어 이루어진 구조이며, 특히, ITO 재질로 이루어지는 플레이트 형상의 공통전극(12)은 게이트 라인(2)과 대응하는 부분에 적어도 하나 이상의 도트형 슬릿(slit : S)이 구비된 구조를 갖는다. 여기서, 상기 도트형의 슬릿(S)은 바람직하게 일자, 또는, 십자 형상으로 구비된다.3 and 4, in the TFT-LCD of the present invention, several gate lines 2 and data lines (not shown) are alternately arranged to define unit pixel areas on the first glass substrate 1, Each intersection is provided with a thin film transistor (not shown), and each pixel region is provided with an array substrate 10 having a pixel electrode (not shown), and the gate line 2 and the second glass substrate 11. A black matrix (not shown) is provided corresponding to the data line, a color filter (not shown) is arranged corresponding to the pixel electrode, and a color filter having a plate-shaped common electrode 12 formed on the black matrix and the pixel electrode. The substrate 20 is bonded to each other under the interposition of the liquid crystal layer 30 including several liquid crystal molecules. In particular, the plate-shaped common electrode 12 made of ITO material corresponds to the gate line 2. At least one The dot-shaped slit: a (slit S) has a structure provided. Here, the dot-shaped slit S is preferably provided in a straight or cross shape.

이와 같은 TFT-LCD 구조에 있어서, 게이트 라인(2)과 공통전극(12) 사이에서의 원치않는 기생용량의 발생은 최소화되며, 이에 따라, 상기 기생용량에 의한 신호지연 현상의 발생이 억제되고, 결국, TFT-LCD의 화면 품위 저하가 방지된다.In such a TFT-LCD structure, the generation of unwanted parasitic capacitance between the gate line 2 and the common electrode 12 is minimized, thereby suppressing the occurrence of signal delay due to the parasitic capacitance, As a result, the deterioration of the screen quality of the TFT-LCD is prevented.

보다 자세하게, 기존의 TFT-LCD에 있어서는 액정층(30)을 사이에 두고 어레이 기판(10)의 게이트 라인(2)과 컬러필터 기판(20)의 공통전극(12)이 배치되는 것으로 인해 이들간에 기생용량이 발생되며, 그래서, 신호지연에 의한 화면 품위의 저하가 발생된다. 반면, 본 발명의 TFT-LCD에 있어서는, 도 4에 도시된 바와 같이, 어레이 기판(10)의 게이트 라인(2)에 대응하는 컬러필터 기판(20)의 공통전극 부분에 슬릿(S)이 구비된 것으로 인해 상기 공통전극(12)과 게이트 라인(2) 사이에서의 기생용량의 발생은 제거되거나, 또는, 최소화된다.In more detail, in the conventional TFT-LCD, the gate line 2 of the array substrate 10 and the common electrode 12 of the color filter substrate 20 are disposed with the liquid crystal layer 30 interposed therebetween. Parasitic capacitance is generated, and therefore, deterioration of screen quality is caused by signal delay. On the other hand, in the TFT-LCD of the present invention, as shown in FIG. 4, the slit S is provided in the common electrode portion of the color filter substrate 20 corresponding to the gate line 2 of the array substrate 10. As a result, the generation of parasitic capacitance between the common electrode 12 and the gate line 2 is eliminated or minimized.

따라서, 기생용량에 의한 게이트 라인(2)에 실려지는 어드레스신호의 신호지연은 억제되는 바, 크로스토크 및 플리커 등의 발생이 억제되고, 그래서, TFT-LCD의 화면 품위 저하가 억제된다.Therefore, the signal delay of the address signal carried on the gate line 2 due to the parasitic capacitance is suppressed, so that the occurrence of crosstalk, flicker, and the like is suppressed, so that the deterioration of the screen quality of the TFT-LCD is suppressed.

이상에서와 같이, 본 발명은 게이트 라인과 대응하는 공통전극 부분에 도트형의 슬릿들을 구비시킴으로써, 상기 게이트 라인과 공통전극간의 기생용량에 의한 상기 게이트 라인에서의 신호지연 현상을 억제시킬 수 있으며, 그래서, TFT-LCD의 화면 품위를 향상시킬 수 있다.As described above, the present invention can suppress the signal delay phenomenon in the gate line due to the parasitic capacitance between the gate line and the common electrode by providing the slit of the dot in the common electrode portion corresponding to the gate line, Thus, the screen quality of the TFT-LCD can be improved.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (2)

단위 화소 영역들을 한정하도록 수 개의 게이트 라인 및 데이터 라인이 교차 배열되고, 각 교차부에는 박막 트랜지스터가 구비되며, 각 화소 영역 내에는 화소전극이 구비된 어레이 기판과, 상기 게이트 라인 및 데이터 라인에 대응해서 블랙 매트릭스가 구비되고 상기 화소전극과 대응해서 컬러필터가 배열되며, 상기 블랙 매트릭스와 화소전극 상에는 플레이트 형상의 공통전극이 형성된 컬러필터 기판이 액정층의 개재하에 합착되어 이루어진 박막 트랜지스터 액정표시장치에 있어서,Several gate lines and data lines are alternately arranged to define unit pixel regions, and thin film transistors are provided at each crossing portion, and an array substrate having pixel electrodes in each pixel region corresponds to the gate lines and data lines. And a color filter arranged in correspondence with the pixel electrode, and a color filter substrate having a plate-shaped common electrode formed on the black matrix and the pixel electrode bonded to each other under a liquid crystal layer. In 상기 각 게이트 라인과 대응하는 공통전극에 부분에 적어도 하나 이상의 도트형 슬릿(slit)이 구비된 것을 특징으로 하는 박막 트랜지스터 액정표시장치.And at least one dot-shaped slit in a portion of the common electrode corresponding to each of the gate lines. 제 1 항에 있어서, 상기 슬릿은The method of claim 1, wherein the slit 일자, 또는, 십자 형상으로 구비되는 것을 특징으로 하는 박막 트랜지스터 액정표시장치.A thin film transistor liquid crystal display, characterized in that provided in a date, or cross shape.
KR1020010061431A 2001-10-05 2001-10-05 Thin film transistor liquid crystal display KR20030028974A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10204564B2 (en) 2015-12-30 2019-02-12 Samsung Display Co., Ltd. Display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10204564B2 (en) 2015-12-30 2019-02-12 Samsung Display Co., Ltd. Display device

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