KR20030018668A - Gate driving circuit and liquid crystal display device having the same - Google Patents

Abstract

PURPOSE: A gate driving circuit and a liquid crystal display using the same are provided, which controls a driving direction of a plurality of gate lines arranged horizontally and connected to a display cell array circuit. CONSTITUTION: According to a shift register where a plurality of stages(SRC0-SRCn+1) are connected and selects a plurality of gate lines selectively by an output signal of each stage, each stage includes a gate line driving unit including an input port and an output port(OUT) and a control port and a gate line driving port connected to the corresponding gate line. Each stage also includes the first switching unit where the first and the second switch signal are provided, and the first and the second input port(IN1,IN2) are connected to output ports of a previous stage and a next stage, and the first switching unit applies one of the output signals of the previous stage and the next stage to the input port. And the second switching unit, where the first and the second switching signal are provided and the third and the fourth input port(IN3,IN4) are connected to the output ports of the previous stage and the next stage, applies one of the output signals to the control port.

Description

Gate driving circuit and liquid crystal display device using the same {GATE DRIVING CIRCUIT AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driving circuit and a liquid crystal display device using the same, and more particularly, to a gate driving circuit capable of adjusting a driving direction of a plurality of gate lines arranged to extend in a horizontal direction.

Recently, with the rapid development of the information processing apparatus, the development of the display apparatus for displaying the information processed by the information processing apparatus so that a human can recognize is growing rapidly.

Until now, 'CRT-type display device' among display devices has been widely used because of its excellent image quality and low price. However, as the necessity of a light and small display device that emphasizes portability is gradually increasing, 'liquid crystal display device' ) 'S share is also growing day by day.

The liquid crystal display is largely divided into twisted nematic (TN) and super-twisted nematic (STN) methods, and due to the difference in driving method, an active matrix display method using a switching element and TN liquid crystal and a passive matrix using STN liquid crystal (passive matrix) display method. The active matrix display method uses a TFT as a switch to drive an LCD.

TFT-LCD is divided into a-Si TFT LCD and poly-Si TFT LCD. Poly-Si TFT LCD has low power consumption and low price, but has a disadvantage of complicated TFT manufacturing process compared to a-Si TFT. Thus, poly-Si TFT LCDs are mainly applied to small display devices such as those of IMT-2000 phones. On the other hand, a-Si TFT LCD has large area and high yield, and is mainly applied to large screen display devices such as notebook PCs, LCD monitors, and HDTVs.

In a poly-si TFT LCD, a display cell array circuit is formed on a substrate by a TFT process, and the display cell array circuit extends in a column direction connected to a TFT, a transparent pixel electrode connected to a drain electrode of the TFT, and a data electrode of a TFT. A plurality of data lines and a plurality of gate lines connected to the gate electrode of the TFT and extending in the row direction are included.

The plurality of data lines and the gate lines are connected to the data driving circuit and the gate driving circuit, respectively, and drive the plurality of data lines and the gate lines according to signals from the outside. The gate driving circuit includes a shift register having a plurality of stages, and drives a gate line corresponding to each stage by an output signal of the shift register.

Each stage is cascaded and has an input terminal, a control terminal, a clock signal input terminal and an output terminal. That is, the output terminal of each stage is connected to the input terminal of the next stage, and the output terminal of each stage is connected to the control terminal of the previous stage. Therefore, when the clock signal is provided to the shift register, the plurality of stages sequentially provide the output signal from the output terminal to the corresponding gate line. That is, the plurality of gate lines are sequentially driven from top to bottom by the shift register.

However, the shift register advances the gate lines only in one direction. That is, the direction in which the gate lines are driven is fixed from the top to the bottom.

Accordingly, a first object of the present invention is to provide a gate driving circuit capable of adjusting a driving direction of a plurality of gate lines arranged in a horizontal direction.

A second object of the present invention is to provide a liquid crystal display device capable of adjusting a driving direction of a plurality of gate lines connected to a display cell array circuit.

1 is a schematic exploded perspective view of a poly-si TFT liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 2 is a schematic diagram showing the configuration of the TFT substrate shown in FIG.

3 is a block diagram of a shift register of the gate driving circuit shown in FIG. 2.

4 is a configuration diagram of each stage of the shift register shown in FIG. 3.

5 and 6 are block diagrams illustrating an operating state of the shift register illustrated in FIG. 4.

7 and 8 are specific circuit diagrams of the first and second switching means shown in FIG.

9 and 10 are output waveform diagrams of the first and second switching means shown in FIGS. 7 and 8.

11 and 12 are output waveform diagrams of the shift register shown in FIG. 4.

A gate driving circuit according to the present invention for achieving the above-described first object is composed of shift registers in which a plurality of stages are cascaded and sequentially select the plurality of gate lines by an output signal of each stage.

Each stage of the shift register includes gate line driving means including an input terminal, an output terminal, a control terminal, and a gate line driving terminal connected to the corresponding gate line. In addition, each stage is provided with first and second switching signals, and the first and second input terminals are respectively coupled with the output terminals of the previous stage and the next stage, so that the input terminals of the output signals of the previous stage and the next stage are provided. First switching means and first and second switching signals for applying either one are provided, and the third and fourth input terminals are coupled with the output terminals of the next stage and the previous stage, respectively, so that the next stage and Second switching means for applying any one of the output signals of the previous stage.

The shift register is a first dummy stage for providing the output signal of the previous stage to the fifth input terminal of the second stage, and the last stage is for providing the output signal of the next stage to the fourth input terminal of the previous stage. Second dummy stage.

In the present invention, the first input terminal and the second input terminal of the first switching means of the first dummy stage are provided with a floating signal and an output signal of the next stage, respectively, and the third input terminal and the fourth input terminal of the second switching means. Input terminals are provided with output signals and floating signals of the next stage, respectively.

In addition, the first input terminal and the second input terminal of the first switching means of the second dummy stage are provided with the output signal and the floating signal of the previous stage, respectively, and the third input terminal and the fourth input terminal of the second switching means. Are provided with the floating signal and the output signal of the previous stage, respectively.

In the present invention, the start signal is provided to the first input terminal of the first switching means of the first stage and the second input terminal of the first switching means of the last stage, respectively.

In the present invention, the first switching means has a gate electrode connected to the first switching signal, a drain electrode connected to an output terminal of a previous stage, a source electrode connected to the input terminal, a first transistor and a gate electrode connected to a second A second transistor connected to the output terminal of the previous stage, a source electrode connected to the input terminal, a gate electrode connected to the second switching signal, and a drain electrode connected to the output terminal of the next stage. A third transistor connected with a source electrode connected to the input terminal, a gate electrode connected with a first switching signal, a drain electrode connected with an output terminal of a next stage, and a source electrode connected with the fourth transistor connected with the input terminal. It is composed.

In the present invention, the second switching means includes a fifth transistor in which a gate electrode is connected with a first switching signal, a drain electrode is connected with an output terminal of a next stage, and a source electrode is connected with the control terminal, and a gate electrode is second A sixth transistor connected to a switching signal, a drain electrode connected to an output terminal of a next stage, a source electrode connected to the control terminal, a gate electrode connected to a second switching signal, and a drain electrode connected to an output terminal of a previous stage. A seventh transistor connected to a source electrode connected to the control terminal, a gate electrode connected to a first switching signal, a drain electrode connected to an output terminal of a next stage, and a source electrode connected to the eighth transistor connected to the control terminal. It is composed.

In the present invention, the transistors of the first and second switching means are preferably composed of any one of PMOS and NMOS.

In the liquid crystal display according to the present invention for achieving the above-described second object, a display cell array circuit formed on a transparent substrate includes a plurality of data lines and a plurality of gate lines, and each display cell circuit includes corresponding data and Is connected to the gate line pair.

The liquid crystal display includes a shift register in which a plurality of stages are cascaded and sequentially select the plurality of gate lines by an output signal of each stage.

Each stage of the shift register includes a gate line driving means including an input terminal, an output terminal, a control terminal, and a gate line driving terminal connected to the corresponding gate line. In addition, first and second switching signals are provided, and the first and second input terminals are respectively coupled to the output terminals of the previous stage and the next stage to apply any one of the output signals of the previous stage and the next stage to the input terminal. A first switching means and first and second switching signals are provided, and the third and fourth input terminals are coupled with output terminals of the previous stage and the next stage, respectively, to output the previous stage and the next stage to the control terminal. Second switching means for applying any one of the signals.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a schematic exploded perspective view of a poly-si TFT liquid crystal display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display device 100 includes a liquid crystal display panel assembly 110, a backlight assembly 120, a chassis 130, and a cover 140.

The liquid crystal display panel 112 of the liquid crystal display panel assembly 110 includes a TFT substrate 112a and a color filter substrate 112b. The TFT substrate 112a includes a display cell array circuit 111 (shown in FIG. 4), a data drive circuit 113 (shown in FIG. 4), and a gate drive circuit 114 (see FIG. 4) by a poly-si TFT process. Shown) are formed. RGB pixels and transparent common electrodes are formed on the color filter substrate 112b. The TFT substrate 112a and the color filter substrate 112b are opposed to each other and liquid crystal is injected therebetween and then encapsulated.

The backlight assembly 120 includes a lamp assembly 122, a light guide plate 124, optical sheets 126, a reflector plate 128, and a mold frame 129.

2 is a schematic view showing the configuration of a TFT substrate of a poly-TFT LCD.

Referring to FIG. 2, the poly-Si TFT LCD 100 forms a data driving circuit 113 and a gate driving circuit 114 on a glass substrate 112a on which a display cell array is formed, and is integrated with the terminal portion 116. The printed circuit board 119 is connected to the film cable 118.

The display cell array circuit 111 extends in a column direction connected to a TFT formed by a poly-si TFT process on the glass substrate 112a, a transparent pixel electrode connected to a drain electrode of the TFT, and a data electrode of the TFT. A plurality of data lines and a plurality of gate lines connected to the gate electrode of the TFT and extending in a row direction.

The data driving circuit 113 and the gate driving circuit 114 are connected to the plurality of data lines and the gate lines to drive the plurality of data lines and the gate lines according to signals from the outside. In this case, the gate driving circuit 114 includes a shift register having a plurality of stages to drive the gate line by an output signal of the shift register.

3 is a block diagram of a shift register of the gate driving circuit shown in FIG. 2.

Referring to FIG. 3, the shift register 114a is configured such that a plurality of stages SRC0 to SRCn + 1 are cascaded, and the plurality of stages SRC0 to SRCn + 1 are N gate lines GL1 to GLn. N stages SRC1 to SRCn and two dummy stages SRC0 and SRCn + 1. Each stage includes first to fourth input terminals IN1 to IN4, clock signal input terminals CK and CKB, switching signal input terminals S and SB, an output terminal OUT, and a gate line driving terminal G. Have

Gate line driving terminals G1 to Gn of each stage are connected to corresponding gate lines GL1 to GLN. At this time, the first and second clock signals CK and CKB are respectively provided to the clock signal input terminals CK and CKB of each stage. The first and second clock signals CK and CKB have inverted phases. The first and second input terminals IN1 and IN2 of the stages are provided with output signals OUTn-1 and OUTn + 1 of the previous stage and the next stage, respectively. In addition, the third and fourth input terminals IN3 and IN4 are provided with output signals OUTn-1 and OUTn + 1 of the next stage and the previous stage, respectively. First and second switching signals S and SB are input to the switching signal input terminals S and SB of the stages. In this case, the first and second switching signals S and SB have inverted phases.

The start signal ST is provided to the first input terminal IN1 of the second stage SRC1 instead of the output signal OUT0 of the previous stage, and the next stage is provided to the second input terminal IN2 of the Nth stage SRCn. The start signal ST is provided instead of the output signal OUTn + 1.

A floating signal is provided to the first input terminal IN1 of the first stage SRC0, which is a dummy stage, and an output signal OUTn + 1 of the next stage is provided to the second input terminal IN2. In addition, the third input terminal IN3 is provided with the output signal OUTn + 1 of the next stage, and the floating signal is provided with the fourth input terminal IN4. In this case, a corresponding gate line does not exist in the gate line driving terminal G0 of the dummy stage SRC0.

The output signal OUTn-1 of the previous stage is provided to the first input terminal IN1 of the last stage SRCn + 1 which is the dummy stage, and the floating signal is provided to IN2 of the second input terminal. In addition, the floating signal is provided to the third input terminal IN3 and the output signal OUTn-1 of the stage before the fourth input terminal IN4 is provided.

4 is a configuration diagram of each stage of the shift register shown in FIG. 3. However, in FIG. 4, an I-th stage SRCi, which is one of the 1st to Nth stages SRC1 to SRCn, and an I + 1th stage SRCi + 1 will be described as an example. 'I' is an even number.

Referring to FIG. 4, each stage SRCi and SRCi + 1 is connected to the gate lines GLi and GLi + 1 and gate line driving means for applying driving signals Gi and Gi + 1 to the gate lines. A first switching means (Si1, for selecting an input provided to the gate line driving means (Di, Di + 1) connected to (Di, Di + 1) and the gate line driving means (Di, Di + 1); Si + 11) and second switching means (Si2, Si + 12). The first switching means Si1 and Si + 11 are coupled to the input terminal IN of the gate line driving means Di and Di + 1 of the stages SRCi and SRCi + 1, and the second switching is performed. The means D is coupled to the control terminal CT of the gate line driving means Di and Di + 1.

The first switching means Si1 is connected to the first and second input terminals IN1 and IN2 provided with output signals OUTi-1 and OUTi + 1 of the previous stage and the next stage, and the second switching. The means Si2 are connected to the third and fourth input terminals IN3 and IN4 provided with output signals OUTi + 1 and OUTi + 1 of the next and previous stages.

The first switching means Si1 selects one of the signals from the first and second input terminals and provides it to the input terminal IN of the gate line driving means Di, and the second switching means Si2. ) Selects one of the signals from the third and fourth input terminals and provides it to the control terminal CT of the gate line driving means Di.

The gate line driving means Di of the I-th stage SRCi is a first inverter INV1 and the first inverter inverting an input signal provided to the input terminal IN in response to the first clock signal CK. And a second inverter INV2 for inverting the output signal output from the inverter INV1. And a third inverter INV3 that inverts the output signal of the second inverter INV2 in response to the first clock signal CK and feeds it back to the input signal of the second inverter INV2. In addition, a fourth inverter for inverting the output signal of the NAND gate (NAND1) and the NAND gate (NAND1) for NAND operation of the output signal of the second inverter (INV2) and the control signal provided to the control terminal (CT) ( INV4).

Therefore, when a low signal is provided to the input terminal IN and the first clock signal CK reaches a high level, a low signal is output to the gate line driving terminal G. In this case, even when the first clock signal CK becomes a low level section, the gate line driving terminal G is always kept low by the third inverter INV3. In this case, when a high signal is provided to the input terminal IN, and the first clock signal CK becomes a high level section, a high signal is output to the gate line driving terminal G to correspond to the corresponding gate line GLi. Drive.

The gate line driving means Di + 1 of the I + 1th stage SRCi + 1 may include a fifth inverter for inverting an input signal provided to the input terminal IN in response to the second clock signal CKB. INV5) and a sixth inverter INV6 for inverting the output signal output from the fifth inverter INV5. And a seventh inverter INV7 that inverts the output signal of the sixth inverter INV6 in response to the second clock signal CKB and feeds back the input signal of the sixth inverter INV6. In addition, an NAND gate NAND2 for NAND calculating the output signal of the sixth inverter INV6 and the control signal provided to the control terminal CT, and an eighth inverter for inverting the output signal of the NAND gate NAND2 ( INV8).

Therefore, when a low signal is provided to the input terminal IN and the second clock signal CKB becomes a high level section, a low signal is output to the gate line driving terminal G. In this case, even when the second clock signal CKB is at the low level, the gate line driving terminal G is always kept low by the seventh inverter INV7. In this case, a high signal is provided to the input terminal IN, and a high signal is output to the gate line driving terminal G in the high level section of the second clock signal CKB so that a corresponding gate line GLi + 1 is provided. ).

5 and 6 are block diagrams illustrating an operating state of the shift register illustrated in FIG. 4. 5 shows a connection state of the first and second switching means when the plurality of gate lines are sequentially driven from top to bottom, and FIG. 6 shows that the plurality of gate lines are sequentially driven from bottom to top. It shows the connection state of the first and second switching means at the time.

5 and 6, the shift register 114a includes the first switching means Sn1 and the next stage connected to the output signal OUTn-1 of the previous stage and the output signal OUTn + 1 of the next stage. Second switching means Sn2 are connected to the output signal OUTn + 1 and the output signal OUTn-1 of the previous stage, respectively. The output signal of the first switching means Sn1 is connected to the input terminal IN of the gate line driving means D, and the output signal of the second switching means Sn2 is the gate line driving means D. It is connected to control terminal (CT) of.

The first switching means Sn1 is provided with first and second switching signals S and SB, and output signals OUTn of the previous stage and the next stage according to the first and second switching signals S and SB. -1, OUTn + 1). In addition, the second switching means Sn2 are provided with first and second switching signals S and SB, and according to the first and second switching signals S and SB, One of the output signals OUTn + 1 and OUTn-1 is selected. In this case, the first and second switching signals S and SB have inverted phases.

As shown in FIG. 5, when the gate lines 1 to N are driven from the top to the bottom, the first switching means Sn1 outputs the output signal OUTn-1 of the previous stage to the gate line driving means D. Provided to input terminal (IN). In addition, the second switching means Sn2 provides the output terminal OUTn + 1 of the next stage to the control terminal CT of the gate line driving means D.

As shown in FIG. 6, when driving the gate lines N to 1 from the bottom, the first switching means Sn1 drives the output signal OUTn + 1 of the next stage to the gate line driving means D. FIG. To the input terminal (IN) of. In addition, the second switching means Sn2 provides the output terminal OUTn-1 of the previous stage to the control terminal CT of the gate line driving means D.

7 and 8 are detailed circuit diagrams of the first and second switching means, and FIGS. 9 and 10 are output waveform diagrams of the first and second switching means shown in FIGS. 7 and 8.

Referring to FIG. 7, the first switching means Si1 is composed of four transistors NT1, NT2, NT3, NT4. The drain electrode of the first transistor NT1 is connected to the first input terminal IN1 provided with the output signal OUTn-1 of the previous stage, the gate electrode is connected to the second switching signal SB, and the source electrode. Is coupled to the input terminal (IN) of the gate line driving means (D). The drain electrode of the second transistor NT2 is connected to the first input terminal IN1, the gate electrode is connected to the first switching signal S, and the source electrode is coupled to the input terminal IN. The drain electrode of the third transistor NT3 is connected to the second input terminal IN2 provided with the output signal OUTn + 1 of the next stage, the gate electrode is connected to the first switching signal S, and the source electrode. Is coupled to the input terminal IN. The drain electrode of the fourth transistor NT4 is connected to the second input terminal IN2, the gate electrode is connected to the second switching signal SB, and the source electrode is coupled to the input terminal IN.

Referring to FIG. 8, the second switching means Si2 is composed of four transistors NT5, NT6, NT7, NT8. The drain electrode of the fifth transistor NT5 is connected to the third input terminal IN3 provided with the output signal OUTn + 1 of the next stage, the gate electrode is connected to the first switching signal S, and the source electrode. Is coupled to the control terminal CT of the gate line driving means D. The drain electrode of the sixth transistor NT6 is connected to the third input terminal IN3, the gate electrode is connected to the second switching signal SB, and the source electrode is coupled to the control terminal CT. The drain electrode of the seventh transistor NT7 is connected to the fourth input terminal IN4 provided with the output signal OUTn-1 of the previous stage, the gate electrode is connected to the second switching signal SB, and the source electrode. Is combined with the control terminal CT. The drain electrode of the eighth transistor NT8 is connected with the fourth input terminal IN4, the gate electrode is connected with the first switching signal S, and the source electrode is coupled with the control terminal CT.

7 and 9, a high signal is applied to the first switching signal S of the first switching means Si1 and a low signal is applied to the second switching signal SB. When the first transistor NT1 is turned on by the second switching signal SB, the second transistor NT2 is turned on by the first switching signal S to input the first input signal. The output signal OUTi-1 of the previous stage provided to the terminal IN1 is provided to the input terminal IN of the gate line driving means D. In addition, the third transistor NT3 is turned off by the first switching signal S, and the fourth transistor NT4 is turned off by the second switching signal SB to be turned off. The output signal OUTi + 1 of the next stage provided to the second input terminal IN2 is not provided to the input terminal IN.

7 and 10, when the high signal is applied to the first switching signal S of the second switching means Si2 and the low signal is applied to the second switching signal SB, the fifth transistor is applied. The output of the next stage NT5 is turned on by the first switching signal S and the sixth transistor NT6 is turned on by the second switching signal SB to be provided to the third input terminal IN3. The signal OUTi + 1 is provided to the control terminal CT of the gate line driving means D. In addition, the seventh transistor NT7 is turned off by the second switching signal SB, and the eighth transistor NT8 is turned off by the first switching signal S, so that the fourth input terminal The output signal OUTi-1 of the previous stage provided to IN4) is not provided to the control terminal CT.

8 and 9, when the low signal is applied to the first switching signal S of the first switching means Si1 and the high signal is applied to the second switching signal SB, the first transistor is applied. The previous stage NT1 is turned off by the second switching signal SB and the second transistor NT2 is turned off by the first switching signal S to be provided to the first input terminal IN1. The output signal OUTi-1 is not provided to the input terminal IN of the gate line driving means D. In addition, the third transistor NT3 is turned on by the first switching signal S and the fourth transistor NT4 is turned on by the second switching signal SB to the second input terminal IN2. The output signal OUTi + 1 of the next stage provided is provided to the input terminal IN.

8 and 10, when the low signal is applied to the first switching signal S of the second switching means Si2 and the high signal is applied to the second switching signal SB, the fifth transistor is applied. The next stage NT5 is turned off by the first switching signal S and the sixth transistor NT6 is turned off by the second switching signal SB to be provided to the third input terminal IN3. The output signal of OUTi + 1 is not provided to the control terminal CT of the gate line driving means D. In addition, the seventh transistor NT7 is turned on by the second switching signal SB and the eighth transistor NT8 is turned on by the first switching signal S to the fourth input terminal IN4. The output signal OUTi-1 of the previous stage provided is provided to the control terminal CT.

11 and 12 are output waveform diagrams of the shift register shown in FIG. 4. 11 is an output waveform diagram of the shift register when the gate line is driven from top to bottom, and FIG. 12 is an output waveform diagram of the shift register when the gate line is driven from top to bottom.

Referring to FIG. 11, in the second stage SRC1 of the shift register 114a, the high level section of the first clock signal CK is an output signal of the output terminal OUT in response to the leading end of the start signal ST. Occurs with (OUT1). In addition, in the third stage SRC2, a high level section of the second clock signal CKB is generated as an output signal OUT2 at the output terminal OUT in response to the leading end of the output signal OUT1 of the previous stage. In addition, in the fourth stage SRC3, the high level section of the first clock signal CK is generated as the output signal OUT3 of the output terminal OUT in response to the leading end of the output signal OUT2 of the previous stage.

In the second and third stages SRC1 and SRC2, gate line driving signals G1 and G2 are generated in response to the leading ends of the output signals OUT2 and OUT3 of the next stage. Therefore, as the shift register 114a is driven, the N gate lines GL1 to GLn corresponding to the gate line driving terminals G1 to Gn of the stages SRC1 to SRCn are sequentially driven from top to bottom. .

Referring to FIG. 12, when the start signal ST is provided to the Nth stage of the shift register 114a, the second clock signal CKB in response to the front end of the start signal ST in the Nth stage SRCn. A high level section is generated as an output signal OUTn of the output terminal OUT. In the N-1 th stage SRCn-1, the high level section of the first clock signal CK is output to the output terminal OUTn in response to the leading end of the output signal OUTn of the next stage. Occurs. In the N-2th stage SRCn-2, the high level section of the second clock signal CKB is output to the output terminal OUT in response to the leading end of the output signal OUTn-1 of the next stage. Occurs).

In the Nth and N-1th stages SRCn to SRCn-1, gate line driving signals Gn to Gn-1 are generated in response to the leading ends of the output signals OUTn-1 to OUTn-2 of the previous stage. . Therefore, as the shift register 114a is driven, the N gate lines GLn to GL1 corresponding to the gate line driving terminals Gn to G1 of the stages SRCn to SRC1 are sequentially driven from bottom to top. .

As described above, the gate driving circuit of the present invention includes a shift register in which a plurality of stages are cascaded and sequentially select a plurality of gate lines by an output signal of each stage. Each stage includes gate line driving means having an input terminal, an output terminal, a control terminal and a gate line driving terminal connected to the corresponding gate line. The input terminal is coupled with an output terminal of the first switching means for applying any one of the output signals of the previous stage and the next stage according to the switching signal, and the control terminal is an output signal of the next stage and the previous stage according to the switching signal. It is coupled to the output terminal of the second switching means for applying either one.

Accordingly, the plurality of gate lines arranged to extend in the horizontal direction by the first and second switching means may be sequentially driven from the top to the bottom or from the bottom to the top.

Although described with reference to the examples, those skilled in the art can understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention described in the claims below. There will be.

In other words, in the above-described embodiment, the gate driving circuit of the present invention is adopted as an example in the poly-si TFT LCD. However, it will be very easy for a person skilled in the art to implement the gate driving circuit of the present invention even in an a-si TFT LCD.

Claims (9)

A shift register in which a plurality of stages are cascade-connected and sequentially selects the plurality of gate lines by an output signal of each stage, Each stage Gate line driving means including an input terminal, an output terminal, a control terminal, and a gate line driving terminal connected to the corresponding gate line; First and second switching signals are provided, and the first and second input terminals are coupled with output terminals of the previous stage and the next stage, respectively, to apply one of the output signals of the previous stage and the next stage to the input terminal. First switching means for; And First and second switching signals are provided, and the third and fourth input terminals are coupled with output terminals of the next stage and the previous stage, respectively, to apply one of the output signals of the next stage and the previous stage to the control terminal. And a second switching means for the gate driving circuit. The first stage is a first dummy stage for providing an output signal of the previous stage to the fifth input terminal of the second stage, and the last stage is an output signal of the next stage to the fourth input terminal of the previous stage. And a second dummy stage for providing. The first and second input terminals of the first switching means of the first dummy stage are provided with a floating signal and an output signal of the next stage, respectively, and the third and fourth input terminals of the second switching means. And the output signal and the floating signal of the next stage are respectively provided. The first input terminal and the second input terminal of the first switching means of the second dummy stage are respectively provided with the output signal and the floating signal of the previous stage, and the third input terminal of the second switching means; And the fourth input terminal is provided with a floating signal and an output signal of a previous stage, respectively. The gate driving circuit according to claim 1, wherein a start signal is provided to each of the first input terminal of the first switching means of the first stage and the second input terminal of the first switching means of the last stage. The display device of claim 1, wherein the first switching means comprises: a first transistor having a gate electrode connected to a first switching signal, a drain electrode connected to an output terminal of a previous stage, and a source electrode connected to the input terminal; A second transistor having a gate electrode connected to a second switching signal, a drain electrode connected to an output terminal of a previous stage, and a source electrode connected to the input terminal; A third transistor having a gate electrode connected to the second switching signal, a drain electrode connected to an output terminal of a next stage, and a source electrode connected to the input terminal; And And a fourth transistor having a gate electrode connected to the first switching signal, a drain electrode connected to the output terminal of the next stage, and a source electrode connected to the input terminal. The semiconductor device of claim 1, further comprising: a fifth transistor connected to the second switching means gate electrode, a first switching signal, a drain electrode connected to an output terminal of a next stage, and a source electrode connected to the control terminal; A sixth transistor having a gate electrode connected to the second switching signal, a drain electrode connected to an output terminal of a next stage, and a source electrode connected to the control terminal; A seventh transistor connected to the gate electrode by the second switching signal, the drain electrode by the output terminal of the previous stage, and the source electrode by the control terminal; And And a gate transistor connected to a first switching signal, a drain electrode connected to an output terminal of a next stage, and a source electrode connected to the control terminal. 8. The gate driving circuit according to claim 6 or 7, wherein the transistors of the first and second switching means comprise one of a PMOS and an NMOS. A display cell array circuit formed on a substrate includes a plurality of data lines and a plurality of gate lines, wherein each display cell circuit is connected to a corresponding data and gate line pair. A plurality of stages are cascaded, and configured as a shift register for sequentially selecting the plurality of gate lines by the output signal of each stage, Each stage Gate line driving means including an input terminal, an output terminal, a control terminal, and a gate line driving terminal connected to the corresponding gate line; First and second switching signals are provided, and the first and second input terminals are coupled with output terminals of the previous stage and the next stage, respectively, to apply one of the output signals of the previous stage and the next stage to the input terminal. First switching means for; And First and second switching signals are provided, and the third and fourth input terminals are coupled with output terminals of the previous stage and the next stage, respectively, to apply one of the output signals of the previous stage and the next stage to the control terminal. And a second switching means for the liquid crystal display.