KR100956341B1 - Thin film transistor array panel - Google Patents

Abstract

In a thin film transistor array panel according to an exemplary embodiment of the present invention, a display cell array circuit including a plurality of gate lines, a plurality of data lines, a thin film transistor, and a pixel electrode formed on an insulating substrate, and data transferred to a plurality of data lines. A data driver circuit for transmitting a signal, a gate driver circuit for transmitting a scan or gate signal to a plurality of gate lines, and a gate driver circuit for forming a power supply voltage or a timing signal to the gate driver circuit from outside. It includes a plurality of signal lines to transmit. At this time, the signal line exposes the first wiring, the second wiring, the first wiring, and the second wiring formed of different layers, and contacts the first wiring and the second wiring through the contact hole of the insulating film having the boundary line of petal shape or uneven structure. It includes a connecting member for connecting the first and second wiring.

Liquid crystal, shift register, contact, gate driving circuit, signal line

Description

Thin film transistor array panel

1 is an exploded perspective view illustrating a structure of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a diagram illustrating a configuration of a thin film transistor array panel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a shift register of the data driving circuit of FIG. 2.

4 is a block diagram for describing a shift register employed in the gate driving circuit of FIG. 2.

FIG. 5 is a layout view illustrating a structure of a signal line for transmitting a driving signal to the shift register of FIG. 4.

FIG. 6 is a cross-sectional view taken along the line VI-VI 'of FIG. 5.

<Description of the symbols for the main parts of the drawings>

100 thin film transistor display panel 200 color filter display panel

300: liquid crystal panel assembly 340: backlight assembly

320: chassis 320: cover

170, 164: shift register

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel, and more particularly, to a thin film transistor array panel used as a substrate of a display device.

Recently, information processing devices have been rapidly developed to have various forms, various functions, and faster information processing speed. Information processed in such an information processing device has an electrical signal form. In order for the user to visually check the information processed by the information processing apparatus, a display apparatus that serves as an interface is required.

Recently, a liquid crystal display device has a light weight, a small size, high resolution, low power, and an environment-friendly advantage compared to a typical CRT display device, and is capable of full color and is emerging as a next generation display device.

A liquid crystal display device applies a voltage to a specific molecular array of a liquid crystal to convert it into another molecular array, and visually changes the optical properties such as birefringence, photoreactivity, dichroism, and light scattering characteristics of the liquid crystal cell that emit light by the molecular array. It is a display using the modulation of the light by a liquid crystal cell by converting into.

The liquid crystal display is largely divided into twisted nematic (TN) and super-twisted nematic (STN) methods, and the difference between the driving methods is an active matrix display method using a switching element and a TN liquid crystal and a passive matrix using an STN liquid crystal. There is a passive matrix display method.                         

The main difference between the two methods is that the active matrix display method uses a thin film transistor array panel, which uses a thin film transistor to drive each pixel, and the passive matrix display method does not use a transistor, which is a complicated method. No circuit needed

Thin film transistor liquid crystal display devices are classified according to whether the semiconductor layer uses amorphous silicon or polycrystalline silicon. Although the polycrystalline silicon thin film transistor liquid crystal display device has a small power consumption and a low price, the manufacturing process of the thin film transistor is complicated compared to the amorphous silicon thin film transistor liquid crystal display device. Thus, the polycrystalline silicon thin film transistor liquid crystal display device is mainly applied to a small display device such as a display of an IMT-2000 portable telephone.

The amorphous silicon thin film transistor liquid crystal display device has a large area and a high yield, and is mainly applied to a large screen display device such as a notebook PC, an LCD monitor, and an HDTV.

However, in an amorphous silicon liquid crystal display device, a data driving chip is mounted on a flexible printed circuit board by a chip on film (COF) method, compared to a polycrystalline silicon thin film transistor liquid crystal display device, and the data printed circuit board and Connect the data line terminal portion of the pixel array. In addition, a gate driving chip is formed on the flexible printed circuit board by a COF method, and the gate printed circuit board and the gate line terminal portion of the pixel array are connected through the flexible printed circuit board. That is, the amorphous silicon thin film transistor liquid crystal display device has a disadvantage in terms of cost and slim structure compared with the polycrystalline silicon thin film transistor liquid crystal display device, despite the high productivity, which is an advantage of the process using amorphous silicon. have.

On the other hand, when manufacturing the thin film transistor array panel when connecting the wiring of the different layers through the contact hole of the insulating film to use as a signal line, it is preferable to design the contact portion so that the signal line is not corroded or disconnected at the contact portion in order to transfer the signal transmitted normally. .

Accordingly, the present invention has been made in an effort to solve such a conventional problem, and an object of the present invention is to provide an amorphous silicon thin film transistor array panel capable of adopting a slim structure.

In addition, another object of the present invention is to provide a thin film transistor array panel that can ensure the reliability of the contact portion.

According to an exemplary embodiment of the present invention, a thin film transistor array panel includes a display cell array circuit including a plurality of gate lines, a plurality of data lines, a thin film transistor, and a pixel electrode formed on an insulating substrate. A data driving circuit for transmitting a data signal transmitted to a data line, and is formed on the substrate, a gate driving circuit for transmitting a scan or gate signal to a plurality of gate lines, formed on the substrate, the gate driving circuit from the outside It includes a plurality of signal lines for carrying a power supply voltage or a timing signal. At this time, the signal line exposes the first wiring, the second wiring, the first wiring, and the second wiring formed of different layers, and contacts the first and second wiring through the contact hole of the insulating film having the boundary line of petal shape or uneven structure. And a connection member connecting the first and second wires.

The boundary line of the first or second wiring line may be exposed in the contact hole, and the boundary line of the first or second wire line exposed through the contact hole may include a petal shape or an uneven structure.

Preferably, the first or second wiring comprises a first conductive film containing aluminum or an aluminum alloy or silver or silver alloy and a second conductive film containing chromium or molybdenum or titanium or tantalum, and is exposed through contact holes. It is preferable that the second insulating film be exposed on the first or second wiring.

The first or second wiring may be formed of the same layer as the gate line or the data line, and the connection member may be formed of the same layer as the pixel electrode.

The gate driving circuit is composed of shift registers in which a plurality of stages are cascade-connected, a first signal is coupled to an input terminal, and a shift register sequentially outputs output signals of the respective stages. A first clock and a first control signal for removing the output of the first clock are provided, the even stages have a second clock phase-inverted to the first clock and a second control for removing the output of the second clock. A signal is provided.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily practice the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a structure of a thin film transistor array panel for an amorphous silicon liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.

1 is an exploded perspective view of an a-Si TFT liquid crystal display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel assembly 300, a backlight assembly 340, a chassis 3200, and covers 310 and 320.

The liquid crystal display panel assembly 300 includes a liquid crystal display panel, a flexible printed circuit board 510, an integrated control and data driving chip 540. The liquid crystal display panel includes a thin film transistor array panel 100 and a color filter display panel 200. In the thin film transistor array panel 100, a pixel electrode, a thin film transistor, a data driving circuit, a gate driving circuit, an external connection terminal, and the like formed by a manufacturing process of a thin film transistor using amorphous silicon are formed. The color filter display panel 200 includes red, green, and blue color filters arranged sequentially in each pixel, and a common electrode through which a signal for driving liquid crystal molecules is transmitted, together with the pixel electrode. The thin film transistor array panel 100 and the color filter panel 200 are aligned to face each other, and a liquid crystal is formed between them 100 and 200 and then encapsulated.

Circuits formed in the integrated control and data driving chip 540 and the thin film transistor array panel 100 installed in the flexible printed circuit board 210 are electrically connected by the flexible printed circuit board 510. The flexible printed circuit board 510 provides data signals, data timing signals, gate timing signals, and gate driving voltages to the data driving circuit and the gate driving circuit of the thin film transistor array panel 100.

The backlight assembly 340 includes a lamp assembly 342, a light guide plate 344, optical sheets 346, a reflector plate 128, and a mold frame 349.

2 is a layout view illustrating a configuration of an amorphous silicon thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

2, the display cell array circuit 150, the data driving circuit 160, the gate driving circuit 170, and the data driving circuit external connection terminal 162 are disposed on the thin film transistor array panel 100 according to the exemplary embodiment of the present invention. 163 and a gate driving circuit external connection terminal portion 169 are formed. These are formed together in the thin film transistor manufacturing process using amorphous silicon as a semiconductor layer.

The display cell array circuit 150 includes m data lines DL1 to DLm extending in the row direction and n gate lines GL1 to GLn extending in the column direction.

In the exemplary embodiment of the present invention, the number of data lines and gate lines in the 2-inch liquid crystal display panel has a resolution of 528 (ie, 176 × 3) × 192.

The switching transistor STi is formed at each intersection of the data lines and the gate lines. The source electrode of the switching transistor STi is connected to the data line DLi, and the gate electrode is connected to the gate line GLi. The drain electrode of the switching transistor STi is connected to the transparent pixel electrode PE. The liquid crystal LC is positioned between the transparent pixel electrode PE and the transparent common electrode CE formed on the color filter display panel 200.

Therefore, the liquid crystal array is controlled by the voltage applied between the transparent pixel electrode PE and the transparent common electrode CE, so that the amount of light passing through is adjusted, and gray scale display of each pixel is performed.

The data driving circuit 160 includes a shift register 164 and 528 switching transistors SWT. The 528 switching transistors SWT form eight data line blocks BL1 to BL8 for 66 units.

Each data line block BLi has 66 input terminals commonly connected to an external input terminal 163 composed of 66 data input terminals, and 66 output terminals are connected to corresponding 66 data lines. In addition, a block select terminal is connected to a corresponding one of the eight output terminals of the shift register 164.

Each of the 528 switching transistors SWT has a drain electrode connected to a corresponding data line, a source electrode connected to a corresponding input terminal among 66 data input terminals, and an amorphous silicon thin film connected to a block selection terminal at a gate electrode. It consists of a transistor.

Thus, the 528 data lines are divided into eight blocks of 66 pieces, and each block is sequentially selected by the eight block selection signals of the shift register 164.

The shift register 164 receives a first clock CKH, a second clock CKHB, and a block selection start signal STH through an external connection terminal 162 of three terminals. The output terminals of the shift register 164 are each connected to the block select terminals of the corresponding line blocks.

3 is a block diagram of a shift register of the data driving circuit of FIG. 2.

Referring to FIG. 3, the shift register 164 according to the present invention has nine stages SRH1 to SRH9 connected thereto. That is, the output terminal OUT of each stage is connected to the input terminal IN of the next stage. The number of stages is composed of eight stages SRH1 to SRH8 and one dummy stage SRH9 corresponding to the data line blocks. Each stage has an input terminal IN, an output terminal OUT, a control terminal CT, a clock input terminal CK, a first power supply voltage terminal VSS, and a second power supply voltage terminal VDD. The eight stages SRH1 to SRH8 provide the block select start signals DE1 to DE8 to the block select terminals of the respective data line blocks BL1 to BL8, respectively. The block selection start signal is an enable signal of each line block.

The first clock CKH is provided to the odd-numbered stages SRH1, SRH3, SRH5, SRH7, and SRH9, and the second clock CKHB is provided to the even-numbered stages SRC2, SRC4, SRH6, and SRH8. The first clock CKH and the second clock CKHB have phases opposite to each other. The duty periods of the clocks CKH and CKHB are 1/66 ms or less.

The output signal of the next stage is input to the control terminal CT as a control signal to each control terminal CT of each stage. That is, the control signal input to the control terminal CT becomes a signal delayed by the duty period of its output signal.

Accordingly, since output signals of each stage are sequentially generated with an active period (that is, a high state), corresponding data line blocks are selected and enabled in the active period of each output signal.

The dummy stage SRH9 is for providing a control signal to the control terminal CT of the previous stage SRH8.

4 is a block diagram for describing a shift register employed in the gate driving circuit of FIG. 2.

Referring to FIG. 4, the gate driving circuit 170 of FIG. 2 includes one shift register, and the shift register is connected to a plurality of stages SRC1 to SRC193. That is, the output terminal OUT of each stage is connected to the input terminal IN of the next stage. The stages are composed of 192 stages SRC1 to SRC192 and one dummy stage SRC193 corresponding to the gate lines. Each stage has an input terminal IN, an output terminal OUT, a control terminal CT, a clock input terminal CK, a first power supply voltage terminal VSS, and a second power supply voltage terminal VDD.

The scan start signal STV is input to the input terminal IN of the first stage SRC1. The scan start signal STV is a pulse synchronized with the vertical synchronization signal Vsync.

The output signals GOUT1 to GOUT192 of each stage are connected to the corresponding gate lines. The odd clock stages SRC1, SRC3,... Are provided with a first clock CKV, and the even stages SRC2, SRC4, ... are provided with a second clock CKVB. Here, the first clock CKV and the second clock CKVB have phases opposite to each other. In addition, the duty period of the first clock CKV and the second clock CKVB may be a period of 16.6 / 192 ms.

In each control terminal CT of each stage SRC1, SRC2, SRC3, ..., the output signal GOUT2, GOUT3, GOUT4 of the next stage SRC2, SRC3, SRC4, ... is a control terminal as a control terminal. It is input to (CT). That is, the control signal input to the control terminal CT becomes a signal delayed by the duty period of its output signal.

Therefore, since the output signals of each stage are sequentially generated with an active period (high state), the corresponding horizontal line is selected in the active period of each output signal.

In this embodiment of the present invention, as shown in FIGS. 1 and 4, the gate driving circuit external connection terminal unit 169 is connected to transfer the first clock CKV and the second clock CKVB or the first power supply voltage terminal. A signal line connecting the VSS and the second power supply voltage terminal VDD is formed on the thin film transistor array panel together with the stages SRC1, SRC2, SRC3, .... By the way, the signal line includes at least a wiring formed in different layers and a connecting member connecting the wirings to each other, and the connecting members are formed in layers with each other through contact holes of insulating films formed between the different wirings. The wiring is in place. This will be described in detail with reference to the drawings.

5 is a layout view illustrating a structure of a signal line for transmitting a driving signal to the shift register of FIG. 4, and FIG. 6 is a cross-sectional view taken along the line VI-VI ′ of FIG. 5.

5 and 6, in the thin film transistor array panel 100 according to the exemplary embodiment of the present invention, the thin film transistor array panel 100 may be formed of a material such as chromium or molybdenum or tantalum or titanium or an alloy containing the same. A first conductive film 201 made of a conductive material having contact characteristics and a first wiring 120S made of a second conductive film made of a conductive material having low resistance, such as aluminum or silver, or an alloy containing the same, are formed. .

In addition, the first conductive film 701 made of silicon nitride or silicon oxide, the first conductive film 701 made of a conductive material having good contact characteristics with other materials, and a low resistance on the first insulating film 140 covering the first wiring 120S. The second wiring 170S including the second conductive film 702 made of a conductive material having a structure is formed.

An upper portion of the first insulating layer 140 is formed of an inorganic insulating material such as silicon nitride or an organic insulating material having a low dielectric constant, and a second insulating layer 180 covering the second wiring 170S is formed. The second insulating layer 180 has contact holes 182S and 187S exposing the first and second wirings 120S and 170S. At this time, as shown in FIG. 5, the second conductive layers 202 and 702 are removed from the contact holes 182S and 187S to expose the lower layers 201 and 701 of the first and second wirings 120S and 170S. The side walls of the contact holes 182S and 187S have a tapered structure having a gentle inclination angle. Through this, a profile of another conductive layer formed on the second insulating layer 180 can be satisfactorily induced. In this case, the contact holes 182S and 187S exposing the first and second wires 120S and 170S take a boundary line having a petal shape or an uneven structure, and the contact holes 182S exposing the first wire 120S are made of a first line. The boundary line of the first wiring 120S is exposed, and the boundary line of the first wiring 120S exposed through the contact hole 182S has a petal shape or an uneven structure. The boundary lines of the contact holes 182S and 187S and the first wiring 120S are formed in the shape of petals or irregularities, so that the first and second wires 120S and 170S exposed through the contact holes 182S and 187S are exposed. The area of the lower layers 201 and 701 may be widened or long. Here, a portion of the lower layers 201 and 701 of the first and second wirings 120S and 170S exposed through the contact holes 182S and 187S may be in contact with another conductive layer formed on the second insulating layer 180. Becomes Of course, the contact hole 187S may be designed in the same manner as the contact hole 182S exposing the first wire 120S so that the boundary line of the second wire 170S is exposed.

The upper portion of the second insulating layer 180 is made of a conductive material and is connected to the first and second wires 120S and 170S through the contact holes 182S and 187S to electrically connect the 120S and 170S to each other. The member 190S is formed.

In the thin film transistor array panel according to the exemplary embodiment of the present invention, the connection member 190S electrically connecting the first and second wirings 120S and 170S and the 120S and 170S to each other may include a gate driving circuit external connection terminal portion ( 169 and a power supply voltage application signal connecting the first power supply voltage terminal VSS. At this time, the current flowing through the first and second wirings 120S and 170S is about 10 times higher than the current flowing through the display cell array circuit 150 (see FIG. 2). Thus, in the exemplary embodiment of the present invention, the boundary lines of the contact holes 182S and 187S and the first or second wiring 120S are designed in the shape of petals or uneven structures to expose the first and the second through the contact holes 182S and 187S. By securing a wide area of the lower layers 201 and 701 of the second wirings 120S and 170S, contact resistance between the first and second wirings 120S and 170 and the connecting member 190S connecting them can be minimized. By securing a long boundary line between the lower layers 201 and 701, a disconnection may be prevented from occurring at the contact portion between the first and second wirings 120S and 170 and the connecting member 190S connecting the same even when a high current flows. can do. In addition, by designing the contact holes 182S and 187S to expose the boundary lines of the first or second wirings 120S and 170S, the upper layers 202 and 702 of the first and second wirings 120S and 170S during the manufacturing process. The first layer exposed through the contact holes 182S and 187S may be removed even when the upper layer 202S and 702S have an etch door undercut structure to the lower portions of the first and second insulating layers 140 and 180. Alternatively, the undercut structure does not occur at the boundary between the second wirings 120S and 170S. Through this, the profile of the connection member 190S connected to the first or second wires 120S and 170S can be satisfactorily induced, the contact structure can be stably secured, and the reliability of the contact can be improved.

In the above embodiment, the signal line for transmitting the power supply voltage has been described, but as shown in FIG. 5, the first and second clocks CKV and CKVB are transferred by being connected to the gate driving circuit external connection terminal unit 169. Through the first and second wirings 120V, 170V, 120B, 170B constituting the signal line, and the contact holes 182V, 187V, 182B, 187B exposing them, and the contact holes 182V, 187V, 182B, 187B. The connection members 190V and 190B, which electrically connect the 120V, 170V, 120B, and 170B to each other, also have the same structure as the signal lines that connect the power supply voltages, so that the effects described above can be similarly obtained.

In this case, the first and second wirings 120S, 102V, 120B, 170S, 170V, and 170B are made of the same layer as the gate line and the data line of the display cell array circuit 150 (refer to FIG. 2), respectively, and the connection member 190S. , 190V and 190B are formed of the same layer as the pixel electrode of the display cell array circuit 150 (refer to FIG. 2), and have a low conductivity having a transparent conductive material or reflectivity such as indium tin oxide (ITO) and indium zinc oxide (IZO). It may be made of a conductive material. In addition, when one of the first and second wirings 120S, 102V, 120B, 170S, 170V, and 170B is formed of a gate line or a data line, the connection members 190S, 190V and 190B are formed of a data line or a gate line. Can be.

Meanwhile, an amorphous silicon layer may be left under the first or second wirings 120S, 102V, 120B, 170S, 170V, and 170B, depending on the manufacturing method or the need.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

As described above, according to the present invention, by designing a gate driving circuit including a shift register in a thin film transistor array panel of an amorphous silicon thin film transistor liquid crystal display device, a manufacturing cost can be reduced and a slim structure can be taken. . In addition, by designing a contact or wire boundary of the wire in the contact portion in the shape of a petal or uneven structure, and by designing the contact hole to expose the wire boundary, the contact resistance of the contact can be minimized, and the connecting member connecting the wire The profile of can be derived well, and the reliability of the contact portion can be improved.

Claims (10)

A display cell array circuit including a plurality of gate lines, a plurality of data lines, a thin film transistor, and a pixel electrode formed on an insulating substrate; A gate driving circuit formed on the substrate and transferring a scan or gate signal to a plurality of the gate lines; A plurality of signal lines formed on the substrate and transferring a power supply voltage or a timing signal to the gate driving circuit from the outside; In the thin film transistor array panel comprising: The signal line exposes the first wiring, the second wiring, and the first and second wirings, which are formed of different layers, and contacts the first and second wirings through contact holes of an insulating layer having a boundary line of petal shape or uneven structure. A connection member connecting the first and second wires to each other; The boundary line of the first or second wire is exposed at the contact hole, The boundary line of the contact hole of the first or second wiring exposed through the contact hole includes a petal shape or an uneven structure. delete delete In claim 1, The first or second wiring line includes a first conductive film including aluminum or an aluminum alloy or silver or a silver alloy and a second conductive film including chromium or molybdenum or titanium or tantalum. In claim 4, The thin film transistor array panel on which the second conductive layer is exposed on the first or second wire exposed through the contact hole. In claim 1, The thin film transistor array panel of claim 1, wherein the first or second wiring is formed of the same layer as the gate line or the data line. In claim 1, And the connection member is formed of the same layer as the pixel electrode. In claim 1, And the connection member is formed on the same layer as the gate line or the data line. In claim 1, The gate driving circuit includes a shift register in which a plurality of stages are cascade-connected, a first signal is coupled to an input terminal, and a shift register sequentially outputs output signals of the stages, and an odd-numbered stage of the shift register. Are provided with a first clock, a first control signal for removing the output of the first clock, and even-numbered stages with a second clock phase-inverted to the first clock and an output of the second clock. A thin film transistor array panel provided with a second control signal for removal. In claim 1, A thin film transistor array panel including a data driving circuit configured to transfer data signals transmitted to a plurality of data lines.

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