KR101352114B1 - Flat Panel Display Device - Google Patents

Abstract

The present invention provides a flat panel display having a plurality of pixel cells and a switching element for driving the pixel cells.

In the case where the switching element is composed of a PMOS transistor, a gate driving circuit used to drive an NMOS transistor, which is widely used in the past, is controlled by controlling only a control signal without developing a separate gate driving circuit for driving the PMOS thin film transistor. It is an object of the present invention to provide a flat panel display device which can reduce production costs by reducing circuit development costs.

In order to achieve the above object, the flat panel display device according to the present invention,

A display panel having a plurality of pixel cells formed for each of the regions defined by the plurality of gate lines and the plurality of data lines, a switching element for driving the pixel cells, and a data driver for supplying image signals to the data lines. And a gate driving circuit for supplying a gate on voltage to each gate line, wherein the gate driving circuit generates the gate on voltage using a start signal, a clock signal, and a gate output signal, and supplies the gate on voltage to the gate line. And a plurality of second stages connected between the plurality of first stages and the plurality of first stages to supply the output signal of the previous stage to the next stage.

Gate driving circuit, PMOS thin film transistor, NMOS thin film transistor, gate output signal

Description

Technical Field [0001] The present invention relates to a flat panel display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display, and more particularly, to a flat panel display which can reduce production costs by using the same gate driving circuit for driving a conventional NMOS transistor.

In a flat panel display having a plurality of pixel cells and a switching element for driving the pixel cells, the switching element is not constituted by an N-channel metal oxide semiconductor thin film transistor (NMOS transistor), which is widely used in the prior art, and is a PMOS. In the case of a transistor (P-channel Metal Oxide Semiconductor Thin Film Transistor),

Without developing a gate driving circuit (P type gate driving circuit) for driving a separate PMOS transistor, the gate driving circuit (hereinafter referred to as N type gate driving circuit) for driving a conventional NMOS transistor is controlled as it is by controlling only a control signal. Provided is a flat panel display device capable of driving a PMOS transistor.

With the development of the information society, liquid crystal display devices (LCDs) and organic light emitting diodes (OLEDs) and organic light emitting diodes (OLEDs) that improve disadvantages such as heavy weight and large volume of conventional CRT (Cathode Ray Tube) ), Various flat panel display devices such as Plasma Panel Display Device (PDP) and Surface-conduction Electron-emitter Display Device (SED) are attracting attention.

Such flat panel display devices include a plurality of pixel cells and a switching element for driving the pixel cells. In FIG. 1, a liquid crystal display device, which is one of the representative flat panel display devices, is illustrated.

In the conventional liquid crystal display, as shown in FIG. 1, m × n pixel cells PXL are arranged in a matrix type, and m data lines DL1 to DLm and n gate lines GL1 to GLn cross each other. To define the pixel region 15, and to supply an image signal to the data lines of the display panel 10 and the display panel 10 having an NMOS transistor connected to the switching element 13 at an intersection thereof. And a gate driving circuit 12 for supplying a gate-on voltage to the gate lines.

The display panel 10 includes a liquid crystal layer interposed between two transparent substrates, and implements an image by adjusting the transmittance of the liquid crystal layer according to a gate-on voltage and an image signal input from the outside.

The data driver 11 converts the input digital video data into an analog voltage using a gamma voltage to supply an image signal to the data lines DL1 to DLm.

The gate driving circuit 12 sequentially supplies a gate-on voltage to the gate lines GL1 to GLn to drive the NMOS transistor so that the image signal is supplied to the pixel cells PXL.

2A shows a detailed configuration of the gate driving circuit 12. As shown in FIG.

As shown in FIG. 2A, the gate driving circuit 12 includes n stages ST1 to STn, an inverter 20 that receives the gate output signal GOE, inverts the output, and outputs signals from each stage and the inverter. And an AND operation unit 24a to 24n for performing an AND operation and outputting the logical AND operation.

Each stage sequentially shifts the start pulse GSP according to the clock signal GSC and outputs the shifted start pulse GSP.

Although not shown, a gate driving circuit is connected to each of the AND products 24a to 24n to convert a voltage level of an output signal output from the AND product, and an output signal output from the level shifter. The apparatus may further include a buffer configured to buffer the output to the liquid crystal panel.

2B is a timing chart of control signals for driving the gate driving circuit.

Referring to FIGS. 2A and 2B, first, stage 1 ST1 receives the start signal GSP first, and then, when the first clock signal GSC is input, high until the next clock signal is input. The stage1 output signal Stage Output 1 in a state is output to the first AND product 24a.

The first AND operation unit 24a receives the stage1 output signal and the gate output signal GOE inverted by the inverter 20, performs an AND operation, and outputs the result to the first gate line GL1. do.

At this time, the gate output signal GOE is input to the inverter as a pulse signal in synchronization with the clock signal GSC.

Therefore, when the gate output signal GOE is input high, the gate output signal GOE is inverted to be low by the inverter 20 and is outputted so that the first logical product operator 24a outputs the low output signal. Output

When the gate output signal GOE is input low, the gate output signal GOE is inverted and output by the inverter 20 so that the first logical product operation unit 24a outputs the gate output signal of the next high state. The output signal of the high state is output to the first gate line GL1 until is input.

In addition, the stage 1 output signal Stage Output 1 is output to the second stage of the next stage, that is, stage 2 (ST2) to activate the stage 2.

The activated stage 2 (ST2) receives the second clock signal and outputs a high stage 2 output signal (Stage Output 2) to the second logical product operator 24b until the next clock signal is input.

In addition, the stage 2 output signal (Stage Output 2) is input to the stage of the next stage to activate the stage of the next stage.

The second AND operation unit 24b receives the gate output signal GOE inverted by the stage 2 output signal and the inverter and performs an AND operation, and similarly performs a gate output signal GOE. ) Is low, and outputs the high output signal to the second gate line GL2 until the next high gate output signal is input.

By repeatedly performing such a process, n stages sequentially output output signals during one frame to implement an image.

In addition to the above-described liquid crystal display device, such an operation method may be operated in a similar manner to other flat panel display devices including a plurality of pixel cells.

However, the conventional flat panel display including a plurality of pixel cells, including a liquid crystal display, is an NMOS transistor whose semiconductor layer of switching elements for driving each pixel cell is mainly made of amorphous silicon doped with an n-type material.

In recent years, PMOS transistors having higher mobility have been widely used to cope with high resolution.

In particular, in the case of an organic light emitting diode (OLED), which is attracting attention as a next-generation flat panel display, a PMOS transistor is widely used as a switching element for driving a pixel cell.

However, in order to drive such a PMOS transistor, when a gate driving circuit used in a conventional NMOS transistor is used, in fact, due to signal delay due to resistance and capacitance, as shown in FIG. There was a problem that the overlapping section (A) occurs,

Accordingly, there is a problem in that a separate gate driving circuit must be developed for driving a PMOS transistor.

As such, when a gate driving circuit for driving a separate PMOS transistor is separately developed in addition to a gate driving circuit for driving a widely used NMOS transistor, an initial development cost increases and this leads to an increase in production cost.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. Instead of developing a gate driving circuit for driving a separate PMOS transistor, a flat panel display device using a gate driving circuit for driving a conventional NMOS transistor by adjusting a control signal is used. It is technical problem to provide.

In order to achieve the above technical problem, the driving circuit in the flat panel display device according to the embodiment of the present invention,

The gate driving circuit is connected between a plurality of first stages for generating the gate-on voltage and supplying the gate-on voltage to the gate line by using a start signal, a clock signal, and a gate output signal, and is connected to the previous stage. A plurality of second stages for supplying an output signal of

The gate on voltage output from the adjacent first stage and the output signal of the second stage have a period in which phases overlap, and the phase is non-overlapping between the gate on voltages output from the adjacent first stage. .

The flat panel display device according to the present invention,

Instead of developing a separate gate driving circuit for driving a PMOS transistor, it is possible to use the same gate driving circuit for driving a widely used NMOS transistor by controlling only a control signal, thereby reducing the production cost. Have

Next, a flat panel display device according to an exemplary embodiment of the present invention will be described in detail.

A flat panel display device according to an embodiment of the present invention,

A display panel including a plurality of pixel cells formed for each of the regions defined by the plurality of gate lines and the plurality of data lines, a switching element for driving the pixel cells, and data for supplying an image signal to the data lines. A driver and a gate driver circuit for supplying a gate-on voltage to each gate line,

The gate driving circuit is connected between a plurality of first stages for generating the gate-on voltage and supplying the gate-on voltage to the gate line by using a start signal, a clock signal, and a gate output signal, and is connected to the previous stage. It characterized in that it comprises a plurality of second stages for supplying the output signal of the next stage.

In addition, in the flat panel display according to the exemplary embodiment of the present invention, the gate-on voltage output from the adjacent first stage and the output signal of the second stage have a period in which phases overlap, and are output from the adjacent first stage. The phase is non-overlapping between the gate-on voltage.

In addition, the switching element may be configured of an NMOS or PMOS transistor connected to the gate line and the data line, and in particular, configured of a PMOS transistor to drive each pixel cell to implement an image.

Such a flat panel display device according to an embodiment of the present invention,

The display panel may be driven by sequentially supplying gate-on voltages for driving the gate lines so that phases do not overlap each other.

In addition, even when a switching device for driving a plurality of pixel cells included in the display panel is configured as a PMOS transistor, the conventional flat panel display device may be used as a switching device without developing a separate gate driving circuit for driving the PMOS transistor. It is possible to use a gate driving circuit for driving a widely used NMOS transistor as it is.

Next, a flat panel display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram illustrating a configuration of a gate driving circuit in a flat panel display device according to an exemplary embodiment of the present invention.

As shown in FIG. 4, in the flat panel display device according to the exemplary embodiment of the present invention, the gate driving circuit includes:

A plurality of first stages S1 to Sn for generating the gate-on voltage and supplying the gate-on voltage to the gate line by using a start signal GSP, a clock signal CLK, and a gate output signal GOE; It comprises a plurality of second stages S'1 to S'n which are connected between stages and supply the output signal of the previous stage to the next stage.

The first stages S1 to Sn may be configured of a plurality of stages, and preferably, the first stages S1 to Sn may have the same number as the gate lines GL1 to GLn provided in the display panel.

In addition, it is preferable that the second stages S'1 to S'n connected between the first stages also have the same number as the gate lines.

The first stage and the second stage may be configured as flip-flops.

In FIG. 4, n gate lines are provided, and the first and second stages are each provided with n gate lines.

The second stages S′1 to S′n receive a gate-on voltage output from the first stages S1 to Sn located at the front end and shift the gate-on voltage according to a clock signal to shift the output signal to a first stage located at a next stage. Will output

In addition, the signal output from the second stage is not input to the display panel because the output terminal of the second stage is floating or pulled down.

The first stages S1 to Sn shift the signal received from the second stage located at the front end according to the clock signal and output the shifted signal to the second stage of the next stage.

In addition, the gate driving circuit inputs an inverter 200 that receives a gate output signal GOE, and inverts and outputs the gate output signal that is inverted from the inverter 200 and a stage output signal output from the first stage. And a plurality of logical product operation units 210a to 210n for performing the logical AND operation.

The result of the AND operation performed by the AND operation unit is sequentially output to the gate line provided in the display panel.

Although not shown, the gate driving circuit may be connected to each of the AND products to convert a voltage level of an output signal output from the AND product, and a buffer of an output signal output from the level shifter to a liquid crystal panel. It may further include a buffer unit for outputting.

In addition, although the switching element for driving each of the pixel cells included in the display panel is preferably composed of a PMOS transistor, it may be possible in the case of an NMOS transistor.

5 is a timing chart of control signals for driving a gate driving circuit when a switching element is formed of a PMOS transistor in a flat panel display according to an exemplary embodiment of the present invention.

The driving of the flat panel display device according to the exemplary embodiment of the present invention will be described with reference to FIGS. 4 and 5.

First, when the first first stage S1 receives the start signal GSP and then receives the first clock signal GSC, the output signal of the first first stage is polled from the high state to the low state. Falling In this way, the polled first stage output signal is output until the second clock signal GSC is input.

In this case, the first gate output signal GOE is inverted by the inverter and is input to the first logical product operation unit 210a together with the first first stage output signal.

The first AND operation unit 210a performs an AND operation on the first gate output signal GOE and the first first stage output signal, and performs a low gate in synchronization with a timing at which the first gate output signal is input. The on voltage is output to the first gate line GL1.

At this time, since the AND operation performs an AND operation, the gate-on voltage supplied to the first gate line GL1 becomes low until the second gate output signal GOE in the form of a pulse is completed. .

Next, when the second clock signal is input, the first first stage S1 output signal rises to a high state again, and the first second stage S′1 is low in a high state. output a first second stage output signal that has fallen to a low state.

In this case, although the rising of the first first stage output signal and the polling of the first second stage output signal are simultaneously performed in FIG. 5, as described above, the signals overlap due to the signal delay caused by the resistance and the capacitance. It is output to have a section.

The output signal of the first second stage S ′ 1 is kept low until the next clock signal is input.

Next, when the third clock signal is input, the first second stage output signal rises again to a high state, and the second first stage output signal is polled from a high state to a low state. falling).

In this way, the output signal output from the second first stage S2 and the gate output signal GOE inverted by the inverter 200 are input to the second AND product 210b, and the second AND product ( 210b performs an AND operation on the input signals and outputs a gate-on voltage to the second gate line GL2 as shown in FIG. 5.

As described above, the gate-on voltage is sequentially input from the first gate line GL1 to the n-th gate line GLn.

On the other hand, when the logical AND operation unit is connected to the first second stage S'1, as shown by the dotted line,

Although it is output to have a section A 'overlapping with the gate-on voltage input to the first gate line GL1 and a section C' overlapping with the gate-on voltage input to the second gate line GL2,

In reality, the output terminal of the first second stage S'1 is connected to be floated or pulled down so that the output signal is not input to the display panel.

In addition, the gate output signal GOE has a first section for outputting a gate-on voltage and a second section for suppressing the output of the gate-on voltage, and the phase of the second section in the gate output signal GOE. And a section overlapping the phase of the rising section in each clock signal.

Therefore, the gate-on voltage input to the first gate line GL1 and the gate-on input to the second gate line GL2 are adjusted by adjusting the duty ratio of the gate output signal GOE in consideration of signal delay due to resistance and capacitance. It is possible to adjust the width of the section B 'that does not overlap between voltages.

That is, in the flat panel display according to the present invention, the gate-on voltage output from the k-th first stage is output so that the phase overlaps with the output signal output from the adjacent second stage, that is, the k-th and k-1th second stages. However, the phases are output so that the phases do not overlap with the gate-on voltages output from the neighboring first stages, that is, the k-1 th and k + 1 th first stages.

Thus, in the flat panel display device which concerns on this invention,

By using a gate driving circuit for driving a conventional NMOS transistor as it is, connecting to a display panel such that only a signal output from, for example, odd or even stages can be input to the display panel,

The gate-on voltages output from the first stages adjacent to each other, that is, the stages connected to the display panel, do not overlap their phases,

By changing the control signal so that the output signal between the first stage and the second stage adjacent to each other overlapping phase,

It is possible to drive a flat panel display in which switching elements are formed with a PMOS transistor without developing a separate gate driving circuit for driving the PMOS transistor.

In addition, the frequency of the clock signal GSC may be driven at a frequency according to the VESA standard for each resolution. That is, since only signals of even or odd stages of the output stage are supplied to the display panel, it is preferable to double the frequency of the clock signal GSC.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

1 is a configuration diagram showing a configuration of a conventional liquid crystal display device.

Fig. 2A is a block diagram showing the configuration of a gate driving circuit in the conventional liquid crystal display device.

FIG. 2B is a timing chart of signals in the gate driving circuit of FIG. 2A. FIG.

3 is a timing chart of signals when driving a PMOS thin film transistor using a conventional N-type driving circuit.

4 is a block diagram showing the configuration of a gate driving circuit in the flat panel display device according to the present invention;

5 is a timing chart of signals in a gate driving circuit in the flat panel display according to the present invention;

 Description of the Related Art

GL1 to GLn: gate lines DL1 to DLm: data lines

PXL: pixel cell 11: data driver

12 gate driving circuit 13 NMOS thin film transistor

10: display panel 15: pixel area

20,200: inverter ST1 to STn: stage

24a to 24n: logical product operation unit 210a to 210n: logical product operation unit

S1 to Sn: first stage S'1 to S'n: second stage

GOE: Gate output signal GSP: Start pulse

GSC: Clock Signal

Claims (6)

A display panel having a plurality of pixel cells formed for each region defined by a plurality of gate lines and a plurality of data lines; A data driver for supplying an image signal to the data line; A gate driving circuit for supplying a gate-on voltage to each of the gate lines, The gate driving circuit A plurality of first stages for generating the gate-on voltage and supplying the gate-on voltage to the gate line by using a start signal, a clock signal, and a gate output signal; A plurality of second stages connected between the plurality of first stages to supply an output signal of a previous stage to a next stage; And a gate on voltage output from the adjacent first stage and an output signal of the second stage have a period in which phases overlap each other, and a gate on voltage output from the adjacent first stage is non-overlapping. . delete The method of claim 1, And each pixel cell includes a PMOS transistor connected to the gate line and the data line. The method of claim 1, The gate driving circuit includes an inverter for inverting a logic state of a gate output signal, and a plurality of AND products for generating the gate-on voltage by performing an AND operation on the output signal of each stage and the gate output signal inverted by the inverter. Flat panel display further comprises an output unit having a. 5. The method of claim 4, The gate output signal has a first section for outputting the gate-on voltage and a second section for suppressing the output of the gate-on voltage, and the second section overlaps the rising section of each clock signal. Flat panel display. The method of claim 1, The display panel includes N gate lines (where N is a natural number), and the first and second stages each include N stages.

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