KR20030010287A - Apparatus and Method of Driving Liquid Crystal Display - Google Patents

Abstract

PURPOSE: A driving apparatus of a liquid crystal display device and a method for driving the same are provided to rapidly charge a pixel voltage up to a data voltage by forming a data modulation voltage created through a data modulation block, thereby applying to a high resolution liquid crystal display device with decreasing a gate pulse width thereof. CONSTITUTION: A driving apparatus of a liquid crystal display device includes a digital video card(31) for converting a signal into a digital video data, a data driver(33) for supplying the video data to the data lines of the liquid crystal display panel(36), a gate driver(34) for sequentially driving the gatelines of the liquid crystal display panel(36), a control block(32) for controlling the data driver(33) and the gate driver(34) and a data modulation block(35) connected between the data driver(33) and the control block(32), wherein the data driver(33) supplies the modulation data supplied during an initial supply period of the scanning signal and the input data supplied during the remaining period of the scanning signal.

Description

Apparatus and Method of Driving Liquid Crystal Display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a driving device for a liquid crystal display device and a driving method thereof capable of improving a filling rate.

In general, a liquid crystal display (“LCD”) displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. Among the liquid crystal display devices, an active matrix type in which switching elements are provided for each liquid crystal cell is suitable for displaying a moving image. In an active matrix type LCD, a thin film transistor (hereinafter, referred to as TFT) is mainly used as a switching element.

As shown in FIG. 1, the driving device of the liquid crystal display device includes a digital video card 1 for converting analog data into digital video data and a data driver for supplying video data to data lines DL of the liquid crystal panel 6. (3), the gate driver 4 for sequentially driving the gate lines GL of the liquid crystal panel 6, and the control unit 2 for controlling the data driver 3 and the gate driver 4 Equipped.

Liquid crystal is injected between the two glass substrates, and the liquid crystal panel 6 is formed such that the gate lines GL and the data lines DL are orthogonal to each other on the lower glass substrate. A TFT for selectively supplying an image input from the data lines DL to the liquid crystal cell Clc is formed at the intersection of the gate lines GL and the data lines DL. For this purpose, the gate terminal of the TFT is connected to the gate line GL, and the source terminal of the TFT is connected to the data line DL. The drain terminal of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

The digital video card 1 converts an analog input video signal into digital video data suitable for the liquid crystal panel 6 and detects a synchronization signal included in the video signal.

The control unit 2 supplies the digital video data of red (R), green (G) and blue (B) from the digital video card 1 to the data driver 3. In addition, the controller 2 generates the dot clock Dclk and the gate start pulse GSP using the horizontal / vertical synchronization signals H and V input from the digital video card 1 to generate the data driver 3 and the data driver 3. The timing of the gate driver 4 is controlled. The dot clock Dclk is supplied to the data driver 3, and the gate start pulse GSP is supplied to the gate driver 4.

The gate driver 4 has a shift register (not shown) that sequentially generates scan pulses in response to a gate start pulse GSP input from the controller 2, and a level suitable for driving the voltage of the scan pulses to drive the liquid crystal cell. And a level shifter (not shown) for shifting to a low level. In response to the scan pulse input from the gate driver 4, video data on the data line DL is supplied to the pixel electrode of the liquid crystal cell Clc by the TFT.

A dot clock Dclk is input to the data driver 3 together with video data of red (R), green (G), and blue (B) from the control unit 2. The data driver 3 latches the red (R), green (G), and blue (B) digital video data in synchronization with the dot clock Dclk, and then corrects the latched data according to the gamma voltage Vγ. Done. The data driver 3 converts the data corrected by the gamma voltage Vγ into analog data and supplies the data lines DL by one line.

As shown in FIG. 2, the data driver 3 includes a latch 12 into which red, green, and blue data are input, and a digital-to-analog converter connected between the latch 12 and the data lines DL. 13, a multiplexer 14 and an output buffer 15, and a shift register 11 for designating an address of the latch 12. The " DAC "

The latch 12 temporarily stores digital data of red (R), green (G), and blue (B) input from the control unit 2, and at a position indicated by the address information from the shift register 11. The data is stored and the stored one line of data is supplied to the DAC 13.

The DAC 13 decodes the digital data input from the latch 12 and converts the digital data into analog data.

The multiplexer 14 selects one of a plurality of analog data voltages and supplies the same to the output buffer 15.

The output buffer 15 buffers the data from the multiplexer 14 and supplies the data to the data lines DL. In the output buffer 15 and the latch 12, the control unit 2 inverts the polarity of the data according to an inversion driving method, for example, a dot inversion, a line (column) inversion and a frame inversion driving method. The polarity inversion signal is input from the.

The shift register 11 generates address information for data stored in the latch 12.

As shown in FIG. 3, the data voltage charging characteristic of the liquid crystal display device charges the data voltage from the rising edge of the gate pulse GP to the period of maintaining the high level. For example, the gate high voltage applied to the TFT is turned on to 20V to form a channel for 21.7 kV. After the gate voltage is turned on, the data voltage is turned on and applied to the data line DL. Then, the time taken for the pixel voltage Vp to charge up to the data voltage takes about 14 ms after the gate voltage is turned on. In this case, the XGA class having a gate pulse width of 21.7 mA or the SXGA class having a gate pulse width of 16.3 ms can sufficiently charge the pixel voltage to the data voltage.

However, as the liquid crystal display device becomes higher resolution, the gate pulse width becomes narrower. For example, in the UXGA class, since the gate pulse width is 13.9 ㎲, the pixel voltage does not reach the data voltage and is discharged. As a result, there is a problem that a change in image quality occurs in addition to a decrease in the charging rate.

Accordingly, it is an object of the present invention to provide a driving apparatus for a liquid crystal display device and a driving method thereof capable of improving a filling rate.

1 is a block diagram showing a conventional liquid crystal display device.

FIG. 2 is a block diagram illustrating a data driver of the liquid crystal display shown in FIG. 1.

3 is a waveform diagram illustrating a data pulse and a gate pulse supplied to the liquid crystal display shown in FIG. 1.

4 is a block diagram illustrating a liquid crystal display according to a first embodiment of the present invention.

FIG. 5 is a block diagram illustrating a data modulator of the LCD shown in FIG. 4. FIG.

FIG. 6 is a block diagram illustrating a data driver of the liquid crystal display shown in FIG. 4.

FIG. 7 is a circuit diagram illustrating a multiplexer of the data driver shown in FIG.

8 is a block diagram illustrating a liquid crystal display according to a second exemplary embodiment of the present invention.

9 is a waveform diagram illustrating a method of driving the liquid crystal display device illustrated in FIGS. 4 and 8.

10A and 10B are waveform diagrams illustrating pixel voltages charged corresponding to the data pulses shown in FIG. 9.

Fig. 11 is a waveform diagram showing channel current for pixel voltage charging with respect to data voltage.

<Description of Symbols for Main Parts of Drawings>

1,31: Digital video card 2,32: control unit

3,33: Data driver 4,34: Gate driver

6,36: liquid crystal panel 11,41: shift resist

12,42: Latch 13,43: Digital-to-Analog Converter

14,44: Multiplexer 15,45: Output Buffer

46: lookup table 47: moving modulation unit

In order to achieve the above object, the driving apparatus of the liquid crystal display according to the embodiment of the present invention is a data modulator for adjusting the size of the input data, a scan driver for generating a scanning signal, and during the initial supply period of the scanning signal. A control signal generation section positioned to indicate a data modulation period having a width smaller than the width of the scanning signal, modulation data supplied in the initial supply period of the scanning signal, input data supplied in the remaining period of the scanning signal, and modulation data; And a data driver for supplying input data, respectively.

The data modulator includes a lookup table that modulates input data to generate modulated data.

The control signal generator generates a modulation period control signal for indicating a data modulation period.

The data driver includes a shift register for addressing data and modulation data, a latch for storing data and modulation data, temporarily storing data stored for one line, and outputting stored data every horizontal period, A digital-analog converter that selects a gamma voltage corresponding to the data and decodes the data, a multiplexer that outputs data from the digital-analog converter in response to a modulation period control signal, and a data line by buffering data from the multiplexer It further comprises an output buffer for supplying the field.

The multiplexer includes a first switch to which a data voltage is applied in response to the modulation period control signal, and a second switch to which a modulation data voltage is applied in response to the modulation period control signal.

A lookup table and a control signal generator are integrated in the data driver.

In order to achieve the above object, a method of driving a liquid crystal display device according to the present invention includes adjusting the size of input data in a data modulator, generating a scanning signal in a scan driver, and positioning the initial signal in the initial supply period. Instructing the data modulation period having a width smaller than the width of the scanning signal by the control signal generator; and modulating data supplied in the initial supply period of the scanning signal and input data supplied in the remaining period of the scanning signal. Each supplying step.

The data modulator includes a lookup table that modulates input data to generate modulated data.

The control signal generator generates a modulation period control signal for indicating a data modulation period.

The data driver includes a shift register for addressing data and modulation data, a latch for storing data and modulation data, temporarily storing data stored for one line, and outputting stored data every horizontal period, A digital-analog converter that selects a gamma voltage corresponding to the data and decodes the data, a multiplexer that outputs data from the digital-analog converter in response to the modulation period control signal, and buffers the data from the multiplexer It further includes an output buffer for supplying the lines.

The multiplexer includes a first switch to which a data voltage is applied in response to the modulation period control signal, and a second switch to which a modulation data voltage is applied in response to the modulation period control signal.

A lookup table and a control signal generator are integrated in the data driver.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 11.

Referring to FIG. 4, a driving device of a liquid crystal display device includes a digital video card 31 for converting into digital video data, and a data driver for supplying video data to data lines DL of the liquid crystal panel 36. 33, a gate driver 34 for sequentially driving the gate lines GL of the liquid crystal panel 36, a controller 32 for controlling the data driver 33 and the gate driver 34, And a data modulator 35 connected between the data driver 33 and the controller 32.

In the liquid crystal panel 36, liquid crystal is injected between two glass substrates, and the gate lines GL and the data lines DL are orthogonal to each other on the lower glass substrate. A TFT for selectively supplying an image input from the data lines DL to the liquid crystal cell Clc is formed at the intersection of the gate lines GL and the data lines DL. For this purpose, the gate terminal of the TFT is connected to the gate line GL, and the source terminal of the TFT is connected to the data line DL. The drain terminal of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

The digital video card 31 converts an analog input video signal into a digital video signal suitable for the liquid crystal panel 36 and detects a synchronization signal included in the video signal.

The control unit 32 supplies the red (R), green (G) and blue (B) digital video data from the digital video card 31 to the data driver 33. In addition, the controller 2 generates a control signal including a dot clock Dclk and a gate start pulse GSP using the horizontal and vertical synchronization signals H and V input from the digital video card 31. The data driver 33 and the gate driver 34 are controlled for timing. The dot clock Dclk is supplied to the data driver 33, and the gate start pulse GSP is supplied to the gate driver 34.

The gate driver 34 includes a shift register (not shown) that sequentially generates scan pulses in response to the gate start pulse GSP input from the controller 32, and a level suitable for driving the voltage of the scan pulses to drive the liquid crystal cell. And a level shifter (not shown) for shifting to a low level. In response to the scan pulse input from the gate driver 34, video data on the data line DL is supplied to the pixel electrode of the liquid crystal cell Clc by the TFT.

As illustrated in FIG. 5, the data modulator 35 includes a lookup table 46 for modulating data of red (R), green (G), and blue (B), and a timing modulator for modulating a control signal. The part 47 is provided.

The lookup table 46 modulates data of red (R), green (G), and blue (B) input from the controller 32 to generate modulated data (Mdata). The modulated data Mdata is modulated larger or smaller than the data according to the control signal.

The timing modulator 47 generates a timing modulated signal Cφ by adjusting the duty ratio based on at least one of the control signals Dclk and GSP.

The data driver 33 is supplied with modulated data Mdata of red (R), green (G), and blue (B) modulated by the data modulator 35, and from the control unit 32, red (R), Green (G) and blue (B) data are input. In addition, the data driver 33 is supplied with the timing modulation signal Cφ by the data modulator 35, and the dot clock Dclk is input from the controller 32. The data driver 33 latches the data (data) and the modulation data (Mdata) of red (R), green (G), and blue (B) in synchronization with the dot clock Dclk, and then gamma latches the latched data. Correction is made according to the voltage Vγ. The data driver 33 converts the data corrected by the gamma voltage Vγ into analog data. Then, the modulation data voltage VMdata and the data voltage Vdata, which are selectively turned on by the timing modulation signal C, are supplied to the data line DL.

As illustrated in FIG. 6, the data driver 33 includes a shift register 41 into which data (data) and modulation data (Mdata) of red (R), green (G), and blue (B) are input, and a shift register. A latch 42, a DAC 43, a multiplexer 44, and an output buffer 45 connected between the latch 41 and the data lines DL are provided.

The shift register 41 includes red (R), green (G) and blue (B) data input from the control unit 32 and red (R), green (G) and blue input from the data modulator 35. Address information of the modulation data Mdata of (B) is generated.

The latch 42 stores data data and modulation data Mdata at a position indicated by address information from the shift register 41, and stores one line of data data and modulation data Mdata in a DAC ( 43).

The DAC 43 decodes data and modulated data Mdata input from the latch 42 to generate a data voltage Vdata and a modulated data voltage VMdata.

As shown in FIG. 7, the multiplexer 44 includes a first switch Q1 to which a data voltage Vdata is applied and a second switch Q2 to which a modulation data voltage VMdata is applied. The multiplexer 44 selectively supplies the data voltage Vdata and the modulated data voltage VMdata to the output buffer 45 in response to the timing modulated signal Cφ output from the timing modulator 47.

That is, the modulation data voltage VMdata is supplied to the output buffer 45 when the timing modulation signal Cφ is input, and the data voltage Vdata is supplied to the output buffer 56 when the timing modulation signal Cφ is not input. do.

The output buffer 45 buffers the data voltage Vdata and the modulation data voltage VMdata from the multiplexer 44 to supply the data lines DL to the data lines DL. In the output buffer 45 and the latch 42, the control unit 32 inverts the polarity of the data voltage according to an inversion driving method, for example, a dot inversion, a line (column) inversion and a frame inversion driving method. ), The polarity inversion signal POL is input.

The shift register 41 generates address information for data stored in the latch 42 to control the latch 42.

8 is a block diagram illustrating a data driver of a liquid crystal display according to a second exemplary embodiment of the present invention.

Referring to FIG. 8, the data driver 33 includes a lookup table 46 to which data of red (R), green (G), and blue (B) are input, a lookup table 46, and a data line ( A shift register 41, a latch 42, a DAC 43, a multiplexer 44 and an output buffer 45 connected between the DLs, and a timing modulator 47 for controlling the multiplexer 44 are provided. do.

The lookup table 46 modulates data of red (R), green (G) and blue (B) input from the control unit 32 to control the red (R), green (G) and blue (B) colors. Generate modulation data (Mdata). The modulation data Mdata generated by this lookup table 46 is formed larger or smaller in accordance with the polarity inversion signal POL.

The latch 42 stores data data and modulation data Mdata at a position indicated by address information from the shift register 41, and stores one line of data data and modulation data Mdata in a DAC ( 43).

The DAC 43 decodes data and modulated data Mdata input from the latch 42 to generate a data voltage Vdata and a modulated data voltage VMdata.

The timing modulator 47 modulates at least one of the control signals (GSP, Dclk, etc.) of the digital video card 31 and the controller 32 to generate a timing modulated signal Cφ. This timing modulation signal Cφ controls the multiplexer 44.

As shown in FIG. 7, the multiplexer 44 includes a first switch Q1 to which a data voltage Vdata is applied and a second switch Q2 to which a modulation data voltage VMdata is applied. The multiplexer 44 selectively supplies the data voltage Vdata and the modulated data voltage VMdata to the output buffer 45 in response to the timing modulated signal Cφ generated by the timing modulator 47.

That is, the modulation data voltage VMdata is supplied to the output buffer 45 when the timing modulation signal Cφ is input, and the data voltage Vdata is supplied to the output buffer 56 when the timing modulation signal Cφ is not input. do.

The output buffer 45 buffers the data voltage Vdata and the modulation data voltage VMdata from the multiplexer 44 to supply the data lines DL to the data lines DL. In the output buffer 45 and the latch 42, the control unit 32 inverts the polarity of the data voltage according to an inversion driving method, for example, a dot inversion, a line (column) inversion and a frame inversion driving method. ), The polarity inversion signal POL is input.

The shift register 41 generates address information for data stored in the latch 42 to control the latch 42.

9, in the driving method of the liquid crystal display according to the first and second embodiments of the present invention, a gate pulse GP is generated between data chargers. At the same time, in response to the timing control signal Cφ of the timing modulator 47, the modulated data voltage VMdata maintains a high voltage level, and when the voltage level of the modulated data is at the reference potential state, the data voltage Vdata. Maintains the high voltage level. As a result, the data pulse DP is input with the modulation data voltage VMdata when the timing control signal Cφ is high, and the data voltage Vdata is input with the rest of the period. Corresponding to such a stepped data pulse, the charging time of the pixel voltage is reduced as shown in FIG. 10A.

In addition, when a negative voltage is applied to the data line DL based on the common voltage, that is, when the polarity inversion signal POL is input, the gate pulse GP is generated between the data chargers. At the same time, the modulation data voltage VMdata maintains the low voltage level in response to the timing modulation signal Cφ of the timing modulator 47. The data voltage Vdata maintains the voltage level of the reference potential. . As a result, the modulation pulse voltage VMdata is input to the data pulse DP when the timing modulation signal Cφ is in a high state, and the data voltage Vdata is input in other periods. In response to the stepped data pulse GP, as shown in FIG. 10B, the charging time of the pixel voltage is reduced.

Referring to FIG. 11, it is a view showing a channel current for charging a pixel voltage with respect to a data voltage. It can be seen that the larger the data voltage at the same gate voltage, the greater the amount of current. That is, since the modulation data voltage VMdata is applied to the data voltage Vdata of the liquid crystal display according to the first and second embodiments of the present invention, the pixel voltage Vp is quickly charged to the data voltage Vdata. Able to know. Accordingly, as the resolution becomes higher, the gate pulse width may be applied to an LCD that is getting shorter.

As described above, the driving apparatus and driving method thereof of the liquid crystal display according to the exemplary embodiment of the present invention form a data modulation voltage generated through the data modulator so that the pixel voltage can be quickly charged to the data voltage. Accordingly, the present invention can be applied to a high resolution liquid crystal display device having a small gate pulse width.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (12)

A driving apparatus of a liquid crystal display device having a plurality of data lines supplied with data and a plurality of gate lines supplied with a scanning signal and orthogonal to the data lines, A data modulator for adjusting the size of the input data; A scan driver generating the scanning signal; A control signal generator positioned in an initial supply period of the scanning signal and indicating a data modulation period having a width smaller than the width of the scanning signal; Modulation data supplied in an initial supply period of the scanning signal; Input data supplied to the rest of the scanning signal; And a data driver for supplying the modulated data and the input data, respectively. The method of claim 1, And the data modulator comprises a lookup table that modulates the input data to generate the modulated data. The method of claim 1, And the control signal generator generates a modulation period control signal for indicating the data modulation period. The method of claim 1, The data driver A shift register specifying an address of said input data and modulation data; A latch for storing the input data and the modulation data, temporarily storing the stored data for one line, and outputting the stored data every horizontal period; A digital-to-analog converter that selects a gamma voltage corresponding to the data input from the latch and decodes the data; A multiplexer for outputting data from the digital-analog converter in response to the modulation period control signal; And an output buffer for buffering the data from the multiplexer and supplying the data to the data lines. The method of claim 4, wherein The multiplexer A first switch in response to the modulation period control signal and to which the data voltage is applied; And a second switch to which the modulation data voltage is applied in response to the modulation period control signal. The method of claim 1, And the lookup table and the control signal generator are integrated in the data driver. A driving method of a liquid crystal display device comprising a plurality of data lines supplied with data and a plurality of gate lines supplied with a scanning signal and orthogonal to the data lines, Adjusting the size of the input data by the data modulator; Generating the scanning signal by a scan driver; Indicating a data modulation period having a width smaller than the width of the scanning signal by a control signal generator located in the initial supply period of the scanning signal; And supplying modulation data supplied in the initial supply period of the scanning signal and input data supplied in the remaining period of the scanning signal to a data driver. The method of claim 7, wherein And the data modulator comprises a lookup table configured to generate the modulated data by modulating the input data. The method of claim 7, wherein And the control signal generator generates a modulation period control signal for indicating the data modulation period. The method of claim 7, wherein The data driver A shift register specifying an address of said data and modulation data; A latch for storing the data and the modulation data, temporarily storing the stored data for one line, and outputting the stored data every horizontal period; A digital-to-analog converter that selects a gamma voltage corresponding to the data input from the latch and decodes the data; A multiplexer for outputting data from the digital-analog converter in response to the modulation period control signal; And an output buffer for buffering the data from the multiplexer and supplying the data to the data lines. The method of claim 10, The multiplexer A first switch in response to the modulation period control signal and to which the data voltage is applied; And a second switch to which the modulation data voltage is applied in response to the modulation period control signal. The method of claim 7, wherein And the lookup table and the control signal generator are integrated in the data driver.