KR20030004584A - Method of forming storage electrode of semiconductor memory device - Google Patents

Abstract

PURPOSE: A method for forming a storage electrode in a semiconductor memory device is provided to prevent collapse and to improve capacitance of a capacitor by directly contacting the storage electrode to a contact pad. CONSTITUTION: The first interlayer dielectric(32a) is formed on a substrate(30) having a contact pad(44). A plurality of bit lines having a capping layer(38) and a spacer(42) are formed on the first interlayer dielectric. The second interlayer dielectric(40a) and a TEOS(Tetra Ethyl Ortho Silicate) oxide layer(48a) are sequentially formed on the bit lines. The contact pad(44) is exposed by selectively etching the TEOS oxide layer(48a), the second and first interlayer dielectric(40a,32a). A conductive layer(50) is then formed on the resultant structure.

Description

METHODS OF FORMING STORAGE ELECTRODE OF SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a method of forming a storage electrode of a semiconductor device, and more particularly, to a method of forming a storage electrode of a semiconductor memory device which prevents the storage electrode from falling down and increases a capacitor capacity.

In recent years, as the degree of integration of semiconductor devices increases, the size of patterns becomes smaller. Among such high-density semiconductor devices, semiconductor memory devices such as DRAMs (DRAMs) require a method for improving memory cell characteristics by decreasing the area occupied by memory cells. In the DRAM device, the characteristics of the memory cell are directly related to the capacitance for securing a certain amount of charge required for the operation of the memory device of the capacitor constituting the memory cell. That is, as the capacitance of the cell increases, the characteristics of the memory cell, such as low voltage characteristics and soft error characteristics due to alpha particles, are improved.

As a method of forming a cell capacitor suitable for a highly integrated DRAM device, first, a storage electrode is formed to have a three-dimensional structure to increase the surface area of the storage electrode, and second, a dielectric film having a high dielectric constant is used. And third, there is a method of forming a thin film thickness of the dielectric film. Here, the method of making the thickness of the dielectric film thin has a problem of degrading the characteristics of the capacitor due to the leakage current flowing through the dielectric film. And a method of forming a capacitor using a material having a high dielectric constant has not been put to practical use until now. Therefore, the method of increasing the surface area of the storage electrode is the most widely used situation.

In order to increase the surface area of the storage electrode of the capacitor, a planer structure, a stack structure, a trench structure, and various structures and methods in which they are modified are used.

Recently, in order to maximize the effective capacitance area, a box-type, cylinder-type, etc. structure having a three-dimensional stack structure is adopted. In addition, a hemispherical silicon film (HSG: Hemi-Spherical Grain, HSG) is called. ) To effectively increase the area of the storage electrode.

In this method of forming a box-type HSG structure capacitor, after forming a storage electrode contact, silicon doped with impurities is deposited for the storage electrode, and HSG is formed in a stacked structure in which the storage electrode is separated. However, due to the strict design rule of the device, it is difficult to secure the charge capacity necessary for the operation of the device, and the gap between the electrode and the electrode is narrowed, and the electrode and the electrode by the HSG are formed when HSG is formed after separation of the electrode. There is a problem in that a twin bit fail occurs due to a bridge between them.

In addition, the cylindrical HSG structure capacitors form HSG only inside the cylinder to avoid the bridge, so the area increase of the actual storage electrode is only about 40 to 45% even when the size of the HSG is increased to show an area increase of 100%. . In addition, the manufacturing process is more complicated than the box-type capacitor structure.

In the conventional storage electrode forming method, after forming the storage electrode contact, a dielectric film and a plate electrode are sequentially formed in the storage electrode to form a capacitor. In this case, in order to increase the capacity of the capacitor, a method of increasing the height of the storage electrode is used.

Referring to FIG. 1A, a method of forming a storage electrode of a semiconductor memory device according to the related art includes applying a storage electrode contact pad 14 to a semiconductor substrate 2 on which a substructure (eg, a MOS transistor) is formed. Form. That is, the storage electrode contact pads 14 are formed on the semiconductor substrate 2 on which the plurality of gate lines are formed. Usually, at this time, a bit line pad (not shown) is also formed. The first interlayer insulating film 4 is stacked on the semiconductor substrate 2 on which the gate line is formed, and the space 14 is formed on the sidewalls and the capping film 10 formed of an insulating film having an etch selectivity with the first interlayer insulating film 4. To form a plurality of bit lines. Although not shown in the drawing, a bit line contact hole is formed through patterning after the first interlayer insulating layer is stacked. At this time, the bit line is formed by sequentially stacking and patterning the oxide film 6, the conductive film 8, and the insulating film 10, and then forming a spacer 12 on the sidewall of the obtained pattern. Subsequently, a second interlayer insulating layer 16 that fills the space between the bit lines is stacked so that the bit lines are covered and planarized by a chemical mechanical polishing (CMP) process.

Referring to FIG. 1B, the semiconductor substrate 2 having the planarized second interlayer insulating film is patterned 4a and 16a to the first interlayer insulating film 4 to form contact holes. The conductive plug is stacked inside the contact hole to form the contact plug 18. Subsequently, as shown in FIG. 1C, an etch stop layer 20 is formed on the semiconductor substrate 2 on which the contact plugs 18 are formed, and a mold oxide layer for storage electrodes having an etch selectivity with the etch stop layer 20 ( TEOS: Tetra Ethly Ortho Silicate (22) was laminated.

Referring to FIG. 1D, an etching mask pattern is formed on the mold oxide film 22, and an etching process is performed to partially remove the mold oxide film 22 and the etch stop layer 20. At this time, an etching process is performed so that the contact plug 18 is exposed.

Subsequently, as shown in FIG. 1E, a chemical vapor deposition (CVD) process is performed to deposit a conductive film 24 such as silicon on the entire surface of the semiconductor substrate. The planar etching process removes the conductive material on the upper surface of the mold insulating layer to electrically separate the storage electrode. The HSG is formed, and a dielectric film and a plate electrode are sequentially formed inside the storage electrode to form a capacitor of the semiconductor memory device.

However, the above-described storage forming method is difficult to apply to a highly integrated semiconductor memory device because the process is complicated and the limitation of etching margin is revealed. In addition, the contact area between the storage electrode and the storage electrode contact is narrow, which causes the capacitor to collapse or disappear in a subsequent process.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problem, and to implement a method of forming a storage electrode of a semiconductor memory device for increasing a capacitor capacity of the semiconductor memory device.

In addition, the present invention provides a method of forming a storage electrode of a semiconductor memory device to increase the capacity of a capacitor without expanding the height of the storage electrode.

1 is a cross-sectional view showing a storage electrode structure for manufacturing a capacitor of a semiconductor device according to the prior art; And

2 is a cross-sectional view illustrating a storage electrode structure for manufacturing a capacitor of a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

30 semiconductor substrate 32 first interlayer insulating film

38 capping film 40 second interlayer insulating film

42: spacer 44: contact pad

46: etching stop film 48: template oxide film

50: conductive film (HSG)

According to the present invention for achieving the above object, a method of forming a storage electrode of a semiconductor memory device comprising the steps of: forming a first interlayer insulating film on a semiconductor substrate formed with a lower structure including a storage electrode contact pad; Forming a capping layer pattern having an etch selectivity with the first interlayer insulating layer, and a plurality of bit lines having spacers on sidewalls; Forming a second interlayer dielectric over said bit line; Forming a mold oxide film over said second interlayer insulating film; Forming an etching mask pattern on the mold oxide film; Performing etching using the etching cask pattern to expose the storage electrode contact pads while partially removing the template oxide film, the second interlayer insulating film, and the first interlayer insulating film; Conformally stacking a conductive film for a storage electrode on the semiconductor substrate to which the storage electrode contact pad is exposed; And removing the conductive layer on an upper surface of the mold oxide layer to separate the storage electrode.

The present invention preferably further comprises planarizing the second interlayer insulating film after forming the second interlayer insulating film. In this case, the method may further include forming an etch stop layer on the planarized second interlayer insulating layer. The template oxide layer has an etching selectivity with the etch stop layer. The etch stop layer is partially removed in the step of exposing the storage electrode contact pads.

The conductive film is made of doped amorphous silicon or polysilicon, and the conductive film is deposited by CVD. In particular, when the conductive film is an amorphous silicon, after separating the storage electrode, and further comprising the step of depositing an HSG on the storage electrode.

According to the present invention for achieving the above object, a storage electrode forming method of a semiconductor memory device comprising the steps of: forming a first interlayer insulating film on a semiconductor substrate formed with a lower structure including a storage electrode contact pad; Forming a capping layer pattern having an etch selectivity with the first interlayer insulating layer, and a plurality of bit lines having spacers on sidewalls; Forming a second interlayer dielectric over said bit line; Planarizing the second interlayer insulating film; Forming an etch stop layer over the second interlayer insulating layer; Forming a mold oxide film having an etch selectivity with an etch stop layer; Forming an etching mask pattern on the mold oxide film; Performing etching using the etch cask pattern to partially remove the mold oxide film, the etch stop film, the second interlayer insulating film, and the first interlayer insulating film, exposing the storage electrode contact pads; Conformally stacking a conductive film for a storage electrode on the semiconductor substrate to which the storage electrode contact pad is exposed; And electrically separating the storage electrode by removing the conductive layer on an upper surface of the mold oxide layer.

The conductive film is made of doped amorphous silicon or polysilicon, and the conductive film is deposited by CVD. And if the conductive film is amorphous silicon, after separating the storage electrode, and further comprising the step of depositing an HSG on the storage electrode.

Therefore, according to the present invention, the storage electrode and the contact pad are directly connected to increase the surface of the storage electrode.

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2D are cross-sectional views of a semiconductor substrate in a process sequence illustrating a method of forming a capacitor storage electrode of a semiconductor memory device according to an exemplary embodiment of the present invention.

According to the method of forming the storage electrode of the semiconductor memory device according to the present invention, although the semiconductor memory device is not shown in the figure, a gate oxide film is formed on the entire surface of the semiconductor substrate on the semiconductor substrate 30, and then the gate electrode and the cap A capping layer is deposited in turn. The gate electrode is formed of a polysilicon or metal silicide film, and the capping film is formed of a nitride film. The gate line is usually formed by a photolithography process and an etching process. Low concentration impurities are implanted into the semiconductor substrate to form source and drain regions, and spacers are formed on the sidewalls of the gate lines as nitride films. Subsequently, high-conductivity impurities are ion-implanted into the semiconductor substrate to complete a metal oxide semiconductor (MOS) transistor having a lightly doped drain (LDD) structure.

Referring to FIG. 2A, a landing plug contact pad 44 electrically connected to the source and drain regions of the MOS transistor is formed on the semiconductor substrate 30 having the underlying structure. A first interlayer insulating film 32 for insulating the MOS transistor is formed on the semiconductor substrate 30 on which the landing contact pads 44 are formed of an oxide film, for example, or a BOSG (BoroPhospho Silicate Glass) film.

Subsequently, a plurality of bit lines are formed on the semiconductor substrate 30 on which the first interlayer insulating layer 32 is formed, the capping layer 38 having an etch selectivity with the first interlayer insulating layer 32, and a space 42 on the sidewall. Form. At this time, the bit lines sequentially stack the oxide film 34, the conductive film 36, and the nitride film 38, and form spacers 42 on the sidewalls. Subsequently, a second interlayer insulating film 40 filling the space between the bit lines is stacked so that the bit lines are covered and planarized by the CMP process.

In FIG. 2B, an etch stop layer 46 is formed on a semiconductor substrate 30 having a planarized second interlayer insulating layer 40, and a mold oxide layer TEOS for storage electrodes having an etch selectivity with an etch stop layer 46. : Tetra Ethly Ortho Silicate (48) was laminated.

Referring to FIG. 2C, an etching mask pattern is formed on a semiconductor substrate on which the mold oxide film 48 is formed, and an etching process is performed to expose the contact pads 44, thereby forming the mold oxide film 48 and the etch stop layer 46. And the second interlayer insulating film 40 and the first interlayer insulating film 32 are partially removed. At this time, the contact pads 44 are sufficiently etched to expose the contact pads 44. This is possible because the damage of the bit line is prevented by the hard mask nitride film, that is, the capping film 38, on the bit line.

Next, referring to FIG. 2D, a CVD process is performed to deposit a conductive film 50, such as amorphous silicon or polysilicon, which is doped on the entire surface of the semiconductor substrate. The storage electrode is electrically separated by removing the conductive material remaining on the upper surface of the mold insulating film 48a through the planarization etching process. The CMP process is mainly used. However, since the depth and width of the storage electrode are deep and narrow, the full-side etching method may be used.

Although not shown in the drawings, a Hemi-Spherical Grain (HSG) such as MSG (Metastable Poly Si) or Surface Area Enhanced Si (SAES), which extends the surface of the storage electrode through a subsequent process, is formed, and the storage electrode is formed. The dielectric film and the plate electrode are sequentially formed to complete the capacitor of the semiconductor memory device.

As described above, according to the present invention, since the inside of the storage electrode contact plug can be used as a capacitor, the capacity of the capacitor is increased at the same height of the storage electrode.

In addition, the storage electrode and the contact pad directly contact each other, thereby preventing the capacitor from falling down. In addition, processes for forming the storage electrode contact plugs, such as photolithography, etching, deposition, and various cleaning processes for forming the story electrode contact plugs, are simplified.

Claims (5)

Forming a first interlayer insulating film on a semiconductor substrate having a lower structure including a storage electrode contact pad; Forming a capping layer pattern having an etch selectivity with the first interlayer insulating layer, and a plurality of bit lines having spacers on sidewalls; Forming a second interlayer dielectric over said bit line; Forming a mold oxide film over said second interlayer insulating film; Forming an etching mask pattern on the mold oxide film; Performing etching using the etching mask pattern to expose the storage electrode contact pads while partially removing the mold oxide film, the second interlayer insulating film, and the first interlayer insulating film; Conformally stacking a conductive film for a storage electrode on the semiconductor substrate to which the storage electrode contact pad is exposed; And removing the conductive layer from the upper surface of the mold oxide layer to separate the storage electrode. The method of claim 1, And forming the second interlayer insulating film, and then planarizing the second interlayer insulating film. The method according to claim 1 or 2, Forming an etch stop layer on the second interlayer insulating layer; Exposing the storage electrode contact pads, partially removing the etch stop layer. The method of claim 3, wherein And the template oxide layer has an etch selectivity with respect to the etch stop layer. Forming a first interlayer insulating film on a semiconductor substrate having a lower structure including a storage electrode contact pad; Forming a capping layer pattern having an etch selectivity with the first interlayer insulating layer, and a plurality of bit lines having spacers on sidewalls; Forming a second interlayer dielectric over said bit line; Planarizing the second interlayer insulating film; Forming an etch stop layer over the second interlayer insulating layer; Forming a mold oxide film having an etch selectivity with an etch stop layer; Forming an etching mask pattern on the mold oxide film; Performing etching using the etching mask pattern to partially remove the mold oxide layer, the etch stop layer, the second interlayer insulating layer and the first interlayer insulating layer, exposing the storage electrode contact pads; Conformally stacking a conductive film for a storage electrode on the semiconductor substrate to which the storage electrode contact pad is exposed; And electrically separating the storage electrode by removing the conductive layer on an upper surface of the mold oxide layer.