KR20030002741A - Method of forming a isolation layer in a semiconductor device - Google Patents

Abstract

PURPOSE: An isolation layer formation method of semiconductor devices is provided to prevent etching of upper edges of an isolation layer when cleaning by forming an oxy-nitrification layer on the surface of the isolation layer. CONSTITUTION: A pad oxide, a polysilicon layer and a pad nitride are sequentially formed on a semiconductor substrate(31). A trench is then formed. An oxide layer(36) is formed at sidewalls of the polysilicon layer and the bottom and inner walls of the trench. An oxy-nitrification layer(37) is formed at interface between the substrate(31) and the oxide layer(36) and polysilicon layer. An isolation layer(39) is then formed by entirely filling an insulating material into the trench. The pad nitride, the polysilicon layer and the pad oxide are removed.

Description

Method of forming a isolation layer in a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation layer of a semiconductor device, and more particularly, to forming a shallow trench isolation (STI) by forming an insulating material in a trench after forming a trench in a semiconductor substrate. It relates to a forming method.

Recently, an element isolation film having a shallow junction is formed as an element isolation film for electrical isolation between semiconductor devices.

1A to 1E are cross-sectional views of devices for describing a method of forming a device isolation film of a semiconductor device according to the prior art.

Referring to FIG. 1A, a pad oxide film 12 and a pad nitride film 13 are sequentially formed on a semiconductor substrate 11, and then the pad nitride film 13 and the pad oxide film 12 of a predetermined region are formed by a photolithography / etch process. The trench 14 is removed by etching the semiconductor substrate 11 to a predetermined depth.

In the above, the pad oxide film 12 is formed to relieve stress of the pad nitride film 13.

Referring to FIG. 1B, an oxide film 15 is grown on sidewalls and bottom surfaces of the trenches 14 in an oxygen atmosphere in order to remove plasma damage generated during an etching process for forming trenches.

Referring to FIG. 1C, the insulating material layer 16 is formed on the entire upper portion of the trench 14 so as to sufficiently fill the trench 14, and then the insulating material layer 16 on the pad nitride layer 13 is removed by a planarization process.

Referring to FIG. 1D, the pad nitride film 13 formed for the planarization process is removed. As a result, the STI process is completed to form the device isolation layer 17 having the shallow junction.

Subsequently, although not shown in the drawings, a masking operation is performed to separate NMOS and PMOS transistors as a subsequent process, followed by an ion implantation process for well and threshold voltage adjustment, and a photoresist removal and cleaning process.

Referring to FIG. 1E, the pad oxide film 12 formed to relieve stress of the pad nitride film 13 is removed by a cleaning process.

Thereafter, a polysilicon film to be used as a gate oxide film and a gate electrode is deposited through a conventional process, and a transistor is formed by performing a masking and etching process for forming a transistor, forming a side wall space, and a source / drain forming process.

The above-described method for forming a device isolation layer of a semiconductor device according to the related art has a problem in that the upper edge A of the device isolation layer 17 is etched and lost during the cleaning process to remove the pad oxide film. This exposes the upper sidewall of the trench 14.

When the upper sidewall of the trench 14 is exposed, an electric field is concentrated in this portion, causing a change in the threshold voltage of the transistor, generation of leakage current, occurrence of bending in the transistor's current-voltage graph, and the like.

In addition, referring to FIG. 2A, the gate oxide film 18 is thinly grown 18a in a subsequent process by thinning the gate oxide film 18 at a corner of the exposed trench 14 due to the etching of the upper edge of the device isolation layer 17. Decreases the reliability. For example, a phenomenon may occur in which the gate oxide film breaks down under the operating voltage.

Referring to FIG. 2B, while the device isolation layer 17 is etched into a puddle having a small edge A, the polysilicon 19a remains in the portion during the subsequent gate electrode (polysilicon) 19 patterning process. The electrical characteristics of the semiconductor device are lowered and defects are generated.

Referring to FIG. 2C, the gate oxide film 18, the polysilicon layer 19 for the gate electrode 19, the insulating film spacer 20, and the LDD structure are formed in the p-well 11a and the n-well 11b through a predetermined process. After forming the transistor made of the source / drain 21, a silicide layer 22 is formed on the gate silicon polysilicon layer 19 and the source / drain 21 through a salicide forming process. At this time, metallic particles such as titanium (Ti) remain in the trench upper sidewall portion in which the isolation layer 17 is formed during the salicide formation process of the gate electrode, and then the upper portion of the isolation layer 17 is deposited when the silicon nitride layer 23 is deposited. This causes a problem that the silicon nitride film 23 is abnormally deposited 23a.

Accordingly, in order to solve the above problems, the present invention forms a buffer polysilicon film between the pad oxide film and the pad nitride film, forms a trench by etching a predetermined region, and then oxidizes the buffer polysilicon film by an oxidation process, and annealing nitrogen gas atmosphere. By forming a nitrided oxide layer having a small amount of etching on the surface of the device isolation layer through nitriding through the process, the upper edge of the device isolation layer is prevented from being etched during the cleaning process, thereby improving process reliability and device electrical characteristics. It is an object of the present invention to provide a method for forming a separator.

1A to 1E are cross-sectional views of a device for explaining a device isolation film forming method of a semiconductor device according to the prior art.

2A to 2C are cross-sectional views of devices for explaining the problems of the prior art.

3A to 3E are cross-sectional views of a device for explaining a device isolation film forming method of a semiconductor device according to the present invention.

4A to 4C are cross-sectional views of devices for explaining the device isolation film of the present invention, which solves the problems of the prior art.

<Explanation of symbols for the main parts of the drawings>

11, 31: semiconductor substrate 11a, 31a: p-well

11b, 31b: n-well 12, 32: pad oxide film

13, 34: pad nitride film 14, 35: trench

15, 36: oxide film 16, 38: insulating material layer

17, 39: device isolation film 18, 40: gate oxide film

18a: thinly formed gate oxide film 19, 41: polysilicon layer

19a: polysilicon residue 20, 42: insulating film spacer

21, 43: source / drain 22, 44: silicide layer

23, 45: silicon nitride film

23a: Deformed silicon nitride film

33 buffer polysilicon film 37 nitrided oxide film

45 silicon nitride film on the device isolation film

A, B: top edge of device separator

In the method of forming a device isolation film of a semiconductor device according to the present invention, the step of sequentially forming a pad oxide film, a polysilicon layer and a pad nitride film on a semiconductor substrate, removing the pad nitride film, the polysilicon layer and the pad oxide film in a predetermined region, Etching to form a trench, forming an oxide film on the sidewalls of the polysilicon layer and the bottom and sidewalls of the trench, forming a nitride oxide film on the interface between the oxide film and the polysilicon layer and the semiconductor substrate, and insulating material on the trench. And embedding the device isolation film and removing the pad nitride film, the polysilicon layer, and the pad oxide film.

After the trench is formed, a cleaning process is performed to remove the etch residue. The oxide film is formed by a thermal oxidation process in an oxygen atmosphere.

The polysilicon layer is formed by low pressure chemical vapor deposition at a temperature of 600 to 650 ℃.

The nitride oxide film is formed by annealing in a nitrogen oxide atmosphere.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

3A to 3E are cross-sectional views of devices for describing a method of forming a device isolation film of a semiconductor device according to the present invention.

Referring to FIG. 3A, the pad oxide film 32 is formed on the semiconductor substrate 31 to sequentially form the pad oxide film 32, and then the buffer polysilicon film 33 and the pad nitride film 34 are sequentially formed. . Thereafter, the pad nitride layer 34, the buffer polysilicon layer 33, and the pad oxide layer 32 are removed by a photolithography / etch process, and the trench 35 is etched by etching the semiconductor substrate 31 to a predetermined depth. Form. When the trench 35 is formed, a predetermined cleaning process is performed to remove the etch residue generated during the etching process for forming the trench 35.

As the trench 35 is formed, sidewalls of the pad nitride film 34, the buffer polysilicon film 33, and the pad oxide film 32 are exposed. At this time, the buffer polysilicon film 33 is formed by low pressure chemical vapor deposition at a temperature of 600 to 650 ℃.

Referring to FIG. 3B, the sidewalls and the bottom of the oxygen atmosphere gauge trench 35 are removed to remove plasma damage generated during the etching process for forming the trench 35 and to round the sidewalls and the bottom of the trench 35. An oxide film 36 is formed in the film. At this time, the side wall of the buffer polysilicon layer 33 is partially oxidized. Thereafter, the nitride oxide film 37 is formed at the interface between the buffer polysilicon film 33 and the oxide film 36 by annealing in a nitrogen oxide (NO gas) atmosphere.

When annealing is carried out in a nitrogen oxide atmosphere, since nitrogen ions are bonded to silicon ions and present in a large amount between the oxide film and the silicon film, the nitride oxide film 37 only at the interface between the buffer polysilicon film 33 and the oxide film 36. Is formed.

In addition, since the nitride oxide film 37 has a property of preventing infiltration and external emission of other ions, it is possible to prevent the metal component from penetrating and remaining on the sidewall of the trench 35 when silicide is formed.

Referring to FIG. 3C, the insulating material layer 38 is formed on the entire upper portion of the trench 35 so as to sufficiently fill the trench 35, and then the insulating material layer 38 on the pad nitride layer 34 is removed by a planarization process. As a result, the insulating material layer 38 remains only in the trench 35.

Referring to FIG. 3D, the pad nitride layer 34 used for the planarization process is removed, and the buffer polysilicon layer 33 is removed to form a device isolation layer 39 having a new shallow junction. The pad oxide film 32 is not removed for use as the screen film of subsequent ion implantation processes.

Subsequently, although not shown in the drawings, a masking operation is performed to separate NMOS and PMOS transistors as a subsequent process, followed by an ion implantation process for well and threshold voltage adjustment, and a photoresist removal and cleaning process.

Referring to FIG. 3E, the pad oxide layer 32 formed on the semiconductor substrate 31 on which the gate oxide layer of the transistor is to be grown to reduce stress of the pad nitride layer is removed by a cleaning process.

At this time, the cleaning process is a hydrofluoric acid-based cleaning process, a very small amount of the nitride oxide film 37 etched in the hydrofluoric acid-based cleaning process at the interface between the oxide film 36 and the buffer polysilicon film 33 in Figure 3b. By forming, the device isolation film 39 is protected from the cleaning process by the nitride oxide film 37, so that no etching loss occurs at the upper edge B. FIG. Thus, the trench upper sidewalls are not exposed even after the cleaning process. For reference, in the hydrofluoric acid series cleaning process having a hydrofluoric acid and water mixing ratio of 1:99, the etching rate of the nitride oxide film is about 3 kW / minute, and the etching rate of the general thermal oxide film is 30 kW / minute.

Thereafter, although not shown in the drawings, a polysilicon film to be used as the gate oxide film and the gate electrode is deposited through a conventional process, and a masking and etching process for forming a transistor, a side wall space formation, a source / drain formation process, and the like are performed. To form a transistor

The method of forming an isolation layer of a semiconductor device according to the present invention prevents the upper edge B of the isolation layer 39 from being etched by protecting the isolation layer 39 with the nitride oxide film 37. Therefore, the oxide film on the upper edge of the device isolation film 39 is thick and nitrided, so that the upper portion of the trench sidewall is not exposed, thereby preventing stable threshold voltage, preventing leakage current, and preventing bumps in the current-voltage graph of the transistor. The reliability of the device can be improved.

In addition, referring to FIG. 4A, the uppermost edge of the device isolation layer 39 of the present invention is not exposed, thereby preventing the gate oxide layer 40 from being thinly formed due to the reduction of oxidative stress. That is, the uniformity of the gate oxide film can be improved.

Referring to FIG. 4B, while the edge of the device isolation layer is etched in the form of a small puddle, polysilicon remains in the portion during the subsequent gate electrode patterning process, thereby deteriorating electrical characteristics of the semiconductor device and causing defects. In the present invention, the upper edge of the device isolation layer 39 is prevented from being etched to solve the above problem.

Referring to FIG. 4C, the gate oxide film 40, the polysilicon layer 41 for the gate electrode 41, the insulating film spacer 42, and the LDD structure are formed in the p-well 31a and the n-well 31b through a predetermined process. After forming a transistor made of the source / drain 43, a polysilicon layer 41 for the gate electrode and a silicide layer 44 are formed on the source / drain 43 through a salicide forming process.

Thereafter, in the prior art, a problem arises in that the metal particles remain at the edges of the device isolation layer during the salicide formation process and thus are deformed at the time of deposition of the silicon nitride film. Particles can be prevented from remaining. As a result, when the silicon nitride film 45 is deposited, the silicon nitride film 45A on the device isolation layer 39 may be normally deposited.

As described above, the present invention prevents the upper edge of the device isolation layer from being etched during the cleaning process of removing the pad nitride layer after removing the pad nitride layer, thereby changing the threshold voltage of the transistor, generating leakage current, and abnormal deposition of the upper element. It is effective to improve the reliability of the process and the electrical characteristics of the device to prevent.

Claims (7)

Sequentially forming a pad oxide film, a polysilicon layer, and a pad nitride film on the semiconductor substrate; Removing the pad nitride layer, the polysilicon layer, and the pad oxide layer in a predetermined region, and etching a semiconductor substrate to form a trench; Forming an oxide film on sidewalls of the polysilicon layer and bottom and sidewalls of the trench; Forming a nitride oxide film at an interface between the oxide film, the polysilicon layer, and the semiconductor substrate; Embedding an insulating material in the trench to form an isolation layer; And removing the pad nitride film, the polysilicon layer, and the pad oxide film. The method of claim 1, And forming a trench to perform a cleaning process to remove an etch residue. The method of claim 1, And the oxide film is formed by a thermal oxidation process in an oxygen atmosphere. The method of claim 1, Wherein the polysilicon layer is formed by low pressure chemical vapor deposition at a temperature of 600 to 650 ° C. The method of claim 1, The method of forming a device isolation film of a semiconductor device, characterized in that the nitride oxide film is formed by annealing in a nitrogen oxide atmosphere. A nitride oxide film is formed at an interface between an insulating material embedded in a trench, a semiconductor substrate, and an upper element. The method of claim 6, The method of forming a device isolation film of a semiconductor device, characterized in that the nitride oxide film is formed by annealing in a nitrogen oxide atmosphere.