KR20080060424A - Method of forming a semiconductor device - Google Patents

Abstract

A method for forming a semiconductor device is provided to restrict void within a conductive layer when filling up the recesses and openings with the conductive layer by forming the upper portion of the recess whose width is same or smaller than the openings. A silicon layer and a nitride layer pattern having a first aperture exposing the silicon layer are formed on a substrate having a reclaimed oxide pattern. A silicon pattern having a second aperture(124) exposing the substrate is formed by etching the silicon layer using the nitride pattern as an etch mask. A third aperture is formed by performing the isotropic etching to the silicon pattern. A recess(130) is formed within the reclaimed oxide pattern by performing anisotropic etching. The recess is expanded by etching a part of the exposed oxide pattern. A gate insulation layer(134) is formed by performing oxidation to the substrate, a side surface of the silicon pattern, and an inner side of the recess. A gate conductor layer filling up the recess is formed.

Description

Method of forming a semiconductor device

1 to 14 are schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate (active region) 102 field region

104: first pad oxide film 110: second nitride film pattern

118: third nitride film pattern 120: first silicon layer pattern

124: second opening 126: third opening

128: fourth opening 130: recess

134: gate insulating film 136: conductive film

138: conductive film pattern

The present invention relates to a method of forming a semiconductor device. More particularly, the present invention relates to a method of forming a semiconductor device having a recessed gate electrode.

As the semiconductor devices are highly integrated, the line widths of the patterns constituting the semiconductor devices and the intervals between the patterns are also reduced. Therefore, there is a need for a technology for forming fine patterns more precisely and accurately. In such semiconductor devices, semiconductor devices having recessed gate electrodes having sufficient effective channel lengths while reducing the horizontal area occupied by the gate electrodes in the substrate have been developed.

In order to form the recessed gate electrode, a process of embedding a conductive material in a recess portion formed in a semiconductor substrate is required. However, it is not easy to embed a conductive material without voids in the recess portion.

In particular, recently, a gate electrode including a recess having an inner width wider than an upper portion thereof has been developed, and when the gate electrode is formed, the gate electrode is completely filled before the conductive film is completely embedded in the recess. Narrow inlet sites are completely blocked by the deposited conductive film so that voids can easily be created in the wide recesses below.

When the void is located at the center portion of the recess, it does not affect the operation of the completed MOS transistor. However, during the subsequent semiconductor process, the voids are easily migrated to other locations, which degrades the electrical characteristics of the transistors.

In addition, when the void is in contact with the gate oxide layer, the threshold voltage of the MOS transistor does not have a set value and becomes very irregular. Due to such dispersion of the threshold voltage and increase in leakage current, the electrical characteristics of the semiconductor device are greatly degraded.

An object of the present invention for solving the above problems is to provide a method of forming a semiconductor device including a gate electrode is suppressed generation of voids or shims.

According to an aspect of the present invention for achieving the above object, in the method of forming a semiconductor device, a nitride film pattern having a silicon layer and a first opening for exposing the silicon layer is formed on a substrate having a buried oxide pattern . The silicon layer is etched using the nitride film pattern as an etching mask to form a silicon pattern having a second opening exposing the substrate. The silicon pattern is isotropically etched to create a third opening that extends from the second opening. The substrate is anisotropically etched using the nitride layer pattern as an etching mask to form a recess in the buried oxide layer pattern. During the cleaning to remove the native oxide layer formed on the substrate, a portion of the oxide pattern exposed on the sidewall of the recess is etched to extend the recess. The recess inner surface, the silicon pattern side surface, and the substrate are oxidized to form a gate insulating film. A gate conductive film is formed to fill the recess.

In example embodiments, the method of forming the semiconductor device may further include performing nitriding on the third opening sidewall.

According to another embodiment of the present invention, the upper width of the recess in which the gate insulating film is formed may be less than or equal to the width of the third opening in which the gate insulating film is formed.

According to the present invention as described above, by extending the sidewall of the silicon pattern used as the mask pattern for forming the recess, the process margin can be obtained in the process of removing the natural oxide film and the process of forming the gate insulating film. Therefore, during the filling of the recess into the gate conductive film, it is possible to suppress the generation of seams or voids in the conductive film.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and those skilled in the art will appreciate the technical spirit of the present invention. The present invention may be embodied in various other forms without departing from the scope of the present invention. In the accompanying drawings, the dimensions of the substrate, film, region, pad or patterns are shown to be larger than the actual for clarity of the invention. In the present invention, when each film, region, pad or pattern is referred to as being formed "on", "upper" or "top surface" of a substrate, each film, region or pad, each film, region, Meaning that the pad or patterns are formed directly on the substrate, each film, region, pad or patterns, or another film, another region, another pad or other patterns may be additionally formed on the substrate. In addition, where each film, region, pad, site or pattern is referred to as "first," "second," "third," and / or "fourth," it is not intended to limit these members but merely to each film. To distinguish between regions, pads, regions or patterns. Thus, "first", "second", "third" and / or "fourth" may be used selectively or interchangeably for each film, region, pad, site or pattern, respectively.

Hereinafter, a method of forming a semiconductor device according to a preferred embodiment of the present invention will be described in detail.

1 to 14 are schematic cross-sectional views illustrating a method of forming a semiconductor device. 1 to 7 illustrate both the cell region and the peripheral region of the semiconductor substrate, but FIGS. 8 to 14 illustrate process cross-sectional views of the active region and the field region of the cell region.

Referring to FIG. 1, a substrate 100 including a cell area and a peripheral area is prepared.

The substrate 100 may be a semiconductor substrate 100 including silicon. The cell region is a region in which storage elements of a semiconductor device are formed, and the peripheral region is a region in which logic cells of the semiconductor device are provided.

An oxide pattern 102 embedded in the semiconductor substrate 100 is formed. The oxide pattern is the field region 102 of the semiconductor substrate 100, and the active region 100 is defined by the oxide pattern.

Referring to the method of forming the field region 102 in more detail, first, a first pad oxide layer (not shown) is formed on the semiconductor substrate 100. By forming the first pad oxide layer, stress between the first nitride layer (not shown) and the semiconductor substrate 100 formed in a subsequent process may be alleviated. The first pad oxide layer may be formed by performing a thermal oxidation or chemical vapor deposition process.

A first nitride film is formed on the first pad oxide film. The first nitride film may be formed by a chemical vapor deposition process or an atomic layer deposition process.

A first photoresist pattern (not shown) is formed on the first nitride film to partially expose the first nitride film. In this case, before forming the first photoresist pattern, an amorphous carbon film (not shown) and an organic anti-reflection film (not shown) may be further formed on the first nitride film. The amorphous carbon film and the organic antireflective film are provided to prevent the first photoresist pattern sidewall profile from being poor by diffuse reflection in a subsequent photographic process.

The nitride layer is etched using the first photoresist pattern as an etching mask to form a first nitride layer pattern (not shown). After forming the first nitride film pattern, the first photoresist pattern may be removed by an ashing and strip process.

The first pad oxide layer and the semiconductor substrate 100 are etched using the first nitride layer pattern as an etch mask to form a first pad oxide layer pattern and a trench (not shown). Plasma dry etch may be used as the etching process.

After forming the trench, a thermal oxide layer (not shown) may be formed inside the trench. The thermal oxide layer may be formed inside the trench in a thin thickness by thermally oxidizing the trench surface in order to cure the surface damage generated during the previous plasma etching process.

Hundreds of insulation dielectric liners (not shown) may be formed on the inner surface of the trench in which the thermal oxide film is formed. The insulating film liner is formed in order to reduce stress in the oxide film for the device isolation layer embedded in the trench by a subsequent process and to prevent impurities from penetrating into the device isolation pattern.

A buried oxide film (not shown) is formed on the nitride film pattern to fill the trench. The buried oxide film may include a USG (Undoped Silicate Glass) film having excellent gap filling properties, an O ₃ -TEOS USG (O ₃ -Tetra Ethyl Ortho Silicate Undoped Silicate Glass) film, or a high density plasma (HDP) oxide film. have.

If necessary, the buried oxide film may be annealed under a high temperature and inert gas atmosphere of about 800 to 1,050 ° C. to densify the buried oxide film, thereby lowering the wet etch rate for the subsequent cleaning process.

The buried oxide layer is polished to expose the top surface of the nitride layer pattern by an etch back or chemical mechanical polishing process to form a buried oxide layer pattern.

After forming the buried oxide pattern 102, the first nitride film pattern is removed.

As a result, the semiconductor substrate 100 is divided into a field region 102 of a buried oxide pattern and an active region 100 defined by the buried oxide layer pattern. In this case, the field region 102 and the active region 100 are formed in both the cell region and the peripheral region.

Referring to FIG. 2, the second pad oxide film 104, the first silicon layer 106, and the second nitride film 108 are formed on the semiconductor substrate 100 on which the buried oxide film pattern is formed.

The second pad oxide film 104 is performed by a thermal oxidation or chemical vapor deposition process. In particular, the second pad oxide film 104 formed on the peripheral area functions as a gate insulating film, and the second pad oxide film 104 formed on the cell area reduces a stress of the semiconductor substrate 100. Do it.

The first silicon layer 106 is formed by performing a chemical vapor deposition process or an atomic layer deposition process. The first silicon layer 106 may include amorphous silicon. In particular, the first silicon layer 106 formed on the peripheral region is converted into a polysilicon layer by subsequent high temperature processes to function as a gate electrode, and the first silicon layer 106 formed on the cell region is then It can be used as an etch mask to form a recess.

The second nitride film 108 is formed by performing chemical vapor deposition or atomic layer deposition. In particular, the second nitride film 108 formed on the peripheral region is then used as an etch mask to form a gate electrode, and the second nitride film 108 formed on the cell region is then used as an etch mask to form a recess. .

Referring to FIG. 3, a second photoresist pattern (not shown) is formed on the second nitride film 108 to partially expose the second nitride film 108. The exposed second nitride layer 108 is etched using the second photoresist pattern as an etching mask to form a second nitride layer pattern 110.

While forming the second nitride film pattern 110, a first opening 112 defined by the second nitride film pattern 110 is generated.

After forming the second nitride film pattern 110, an etching process is continuously performed to remove a portion of the upper portion of the first silicon layer 106. In this case, the thickness to be removed may have the same thickness as that of the second silicon layer formed thereafter.

After forming the second nitride film pattern 110, the second photoresist pattern may be removed by an ashing and stripping process.

Referring to FIG. 4, a second silicon layer 114 is continuously formed on the second nitride film pattern 110 and the first silicon layer 106. In this case, the second silicon layer 114 may not completely fill the first opening 112 defined by the second nitride film pattern 110.

The second silicon layer 114 may be formed by a chemical vapor deposition process or an atomic layer deposition process. In addition, the thickness of the second silicon layer 114 may be the same as the thickness of the upper portion of the first silicon layer 106 removed. The line width of the recessed gate electrode formed later is determined according to the thickness of the second silicon layer 114 formed on the cell region.

Referring to FIG. 5, a third nitride film 116 is formed on the second silicon layer 114 to fill the first opening 112 between the second nitride film patterns 110.

The third nitride film 116 may be formed by performing a chemical vapor deposition process or an atomic layer deposition process. In addition, the third nitride layer 116 may have the same etching selectivity as the second nitride layer.

Referring to FIG. 6, an upper portion of the third nitride layer 116 is removed to expose the upper surface of the second silicon layer 114. The upper portion of the third nitride layer 116 may be removed using a chemical mechanical polishing process or an etch back process.

An upper portion of the second nitride layer pattern 110, an upper portion of the third nitride layer 116, and an upper portion of the exposed second silicon layer 114 are removed. As a result, the second nitride film pattern 110, the third nitride film pattern 118, and the second silicon layer pattern 122 are alternately formed.

Referring to FIG. 7, the second silicon layer pattern 122 is removed. The second silicon layer pattern 122 may be removed by isotropic etching.

A wet etching process is used as the isotropic etching process, and the wet etching solution used in the wet etching process has a high etching selectivity between silicon and nitride. That is, the second nitride layer pattern 110 and the third nitride layer pattern 118 provided on both sides of the second silicon layer pattern 122 while the second silicon layer pattern 122 is removed using the wet etching solution. Is hardly etched.

While completely removing the second silicon layer pattern 122, a second opening 124 defined by the second nitride film pattern 110 and the third nitride film pattern 118 on the first silicon layer 106. ) Is generated.

Subsequently, a first silicon layer pattern including a third opening 126 for etching the first silicon layer 106 exposed by the second opening 124 to expose the second pad oxide film 104 ( 120). As the etching process, isotropic etching or anisotropic etching may be used. For example, when an isotropic etching is used, a wet etching process may be used, and the same wet etching solution as the wet etching solution may be used during the wet etching process.

In this case, the second opening 124 and the third opening 126 communicate with each other, and the second opening 124 and the third opening 126 have the same width.

As a result, a second pad oxide film 104 is formed on the substrate 100 including the buried oxide pattern 102, and the second pad oxide film 104 includes a third opening 126 on the second pad oxide film 104. The second nitride film pattern 110 and the third nitride film pattern 118 including the first silicon layer pattern 120 and the second opening 124 are formed.

Here, the first silicon layer pattern 120, the second nitride film pattern 110, and the third nitride film pattern 118 formed in the cell region may use a mask pattern for forming a recess. Meanwhile, the first silicon layer pattern 120 formed in the peripheral region is used as a gate electrode, and the second nitride layer pattern 110 and the third nitride layer pattern 118 may be formed to form the first silicon layer pattern 120 in a subsequent process. It performs a protective function.

Therefore, the following processes are selectively performed only in the cell region of the substrate 100. 8 to 14 will be described in greater detail with respect to the active region 100 and the field region 102 of the cell region.

Referring to FIG. 8, the first silicon layer pattern 120 is isotropically etched to generate a fourth opening 128 extending from the third opening 126.

Wet etching is used as the isotropic etching, and the wet etching solution used for the wet etching is a material having an etching selectivity between nitride and silicon. That is, the first nitride layer pattern and the second nitride layer pattern 110 are hardly etched while a portion of the sidewalls of the first silicon layer pattern 120 is removed.

The first silicon layer pattern 120 including the fourth opening 128 is formed on both the active region 100 and the field region 102 of the cell region. In this case, the active region 100 includes silicon, and the field region 102 includes an oxide.

Referring to FIG. 9, plasma nitridation is performed on the sidewall of the first silicon layer pattern 120.

By nitriding the first silicon layer pattern 120, the sidewalls of the first silicon layer pattern 120 may be prevented from being oxidized in a subsequent oxidation process.

Referring to FIG. 10, the recess 130 is formed by etching the exposed semiconductor substrate 100 using the second nitride film pattern 110 and the third nitride film pattern 118 as an etching mask.

The etching process uses full anisotropic etching, and the front anisotropic etching process may include plasma dry etching.

The upper width of the recess 130 has the same width as the second opening 124.

The recess 130 formed in the active region 100 of the cell region has a narrower width toward the bottom, and the recess 130 formed in the field region 102 has substantially the same width as the upper and lower portions. This is because the active region 100 includes silicon, and the field region 102 includes an oxide.

In this case, in the active region 100 exposed by the recess 130, silicon included in the active region 100 may react with oxygen to generate a native oxide layer 132.

Referring to FIG. 11, a cleaning process is performed to remove the native oxide film 132 formed on the inner wall of the recess 130 of the active region 100.

The cleaning solution used in the cleaning process includes SC-1 (standard clean-1) solution containing ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ) and deionized water, and diluted ozone (O). ₃ ) or diluted hydrofluoric acid (HF) may be used.

The recess 130 of the field region 102 is formed of an oxide while the natural oxide film 132 formed on the inner wall of the recess 130 of the active region 100 is removed by the cleaning solution. Is expanded.

Referring to FIG. 12, in order to form the gate insulating layer 134 on the inner surface of the recess 130 of the active region 100, the resultant shown in FIG. 11 is oxidized. The oxidation treatment may be a thermal oxidation process.

When the oxidation process is performed, the inner surface of the recess 130 of the active region 100 including silicon is easily oxidized, and the inner surface of the recess 130 of the field region 102 including the oxide may be easily oxidized. Almost no oxidation In addition, the nitrided first silicon layer pattern 120 is partially oxidized. In other words, the degree of oxidation is rapidly determined in order of the inner surface of the recess 130 of the active region 100, the nitrided first silicon layer pattern 120, and the inner surface of the recess 130 of the field region 102. Is oxidized.

Accordingly, the width of the upper portion of the recess 130 of the active region 100 has a width smaller than or equal to the width of the fourth opening 128, and the width of the upper portion of the recess 130 of the field region 102 is equal to the width of the recess 130 of the field region 102. It may have a width smaller than or equal to the width of the fourth opening 128.

Referring to FIG. 13, a conductive layer may be formed on the second nitride layer pattern 110 and the third nitride layer pattern 118 to fill the recess 130, the second opening 124, and the fourth opening 128. 136).

The conductive layer 136 may include a metal, a metal nitride, or a metal silicide, or may include a combination thereof. For example, the conductive layer 136 may include titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicide (TiSi), and tantalum. Silicide (TaSi), tungsten silicide (WSi), and the like.

In this case, since the upper width of the recess 130 is equal to or smaller than the second opening 124 and the fourth opening 128, the conductive layer 136 is filled with the conductive layer 136 while the conductive film 136 is embedded. The generation of voids, seams, and the like in the film 136 can be suppressed in advance.

The upper portion of the conductive layer 136 is polished to expose the upper portions of the second nitride layer pattern 110 and the third nitride layer pattern 118. Examples of the polishing step include a chemical mechanical polishing process and an etch back.

Referring to FIG. 14, the conductive layer 136 is removed between the second nitride layer pattern 110, the third nitride layer pattern 118, and the second nitride layer pattern 110 and the third nitride layer pattern 118. do.

Subsequently, the semiconductor substrate 100 is exposed by removing the conductive layer 136 between the first silicon layer pattern 120 and the first silicon layer pattern 120.

Subsequently, a portion of the conductive film 136 is removed to form a conductive film pattern 138 having an upper surface lower than that of the semiconductor substrate 100. The conductive layer pattern 138 functions as a gate electrode recessed 130.

Although not shown in detail, source / drain regions may be formed in the semiconductor substrate 100 exposed on both sides of the conductive layer pattern 138.

As a result, a transistor including the gate insulating layer 132, the gate electrode 138, and the source / drain region may be formed. Since voids or shims are not formed inside the gate electrode of the transistor, the dispersion of the threshold voltage can be excellently formed and the leakage current can be suppressed.

As described above, according to a preferred embodiment of the present invention, the upper portion of the recess is formed to be smaller than or equal to the width of the openings in communication with the recess, thereby filling the recess and the openings with a conductive film, while It is possible to suppress the generation of internal voids and shims.

Therefore, the distribution of the threshold voltage of the transistor using the conductive film as the gate electrode can be excellent, and the generation of leakage current can be suppressed, so that the electrical characteristics of the semiconductor device can be further improved.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (3)

Forming a nitride film pattern having a silicon layer and a first opening exposing the silicon layer on a substrate having a buried oxide pattern; Forming a silicon pattern having a second opening exposing the substrate by etching the silicon layer using the nitride film pattern as an etching mask; Isotropically etching the silicon pattern to create a third opening that extends from the second opening; Anisotropically etching the substrate using the nitride film pattern as an etching mask to form a recess in the buried oxide pattern; During the cleaning to remove the native oxide layer formed on the substrate, a portion of the oxide pattern exposed on the sidewalls of the recess is etched to extend the recess; Oxidizing the recess inner surface, the silicon pattern side surface, and the substrate to form a gate insulating film; And And forming a gate conductive film filling the recess. The method of claim 1, further comprising nitriding the third opening sidewalls. The method of claim 1, wherein an upper width of a recess in which the gate insulating layer is formed is less than or equal to a width of a third opening in which the gate insulating layer is formed.

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