KR20030002711A - Method for manufacturing a flash memory cell - Google Patents

Abstract

PURPOSE: A method for fabricating a flash memory cell is provided to broaden an open area of a contact hole and to prevent a leakage current from being increased by an over-etch process by compensating for misalignment of the contact hole in a self-aligned contact(SAC) process. CONSTITUTION: A gate oxide layer(210), the first polysilicon layer(220), a dielectric layer(230), the second polysilicon layer(240) and a tungsten silicide layer(250) are sequentially formed on a semiconductor substrate(200). A nitride layer(260) is formed on the tungsten silicide layer. A gate pattern is formed. Impurity ions are implanted into the exposed semiconductor substrate to form a source/drain. A nitride layer for a spacer(270) is deposited on the resultant structure and is etched to form the spacer. An interlayer dielectric(280) is formed on the resultant structure and is planarized. The contact hole is formed by using an SAC process.

Description

Method for manufacturing a flash memory cell

The present invention relates to a method of manufacturing a flash memory cell, and more particularly, to a method of manufacturing a flash memory cell in which a thick nitride film is deposited and a contact hole is formed using a self-aligned contact (SAC) process.

A method of manufacturing a flash memory cell according to a conventional method will be described with reference to FIGS. 1A to 1C.

First, referring to FIG. 1A, a gate oxide film, a first polysilicon layer, a dielectric layer, a second polysilicon layer, a tungsten silicide layer, and a nitride film are sequentially formed on a semiconductor substrate. In this case, the first polysilicon layer is formed to have a thickness of about 1600 kPa, the second polysilicon layer is about 900 kPa, the tungsten silicide layer is about 1500 kPa, and the nitride film is formed to have a thickness of about 1700 kPa. Thereafter, the gate pattern is formed by etching using a photolithography process. The gate pattern thus formed has a width of approximately 0.23 um and a height of 5000 kV. Impurity ion implantation is then performed to form source / drain regions between each gate pattern.

Referring to FIG. 1B, an oxide spacer (not shown) of a double layer of an oxide layer formed by a thermal oxide layer and a deposition process is formed on the sidewall of the gate pattern by using an oxidation process. Subsequently, a spacer nitride is deposited on the entire structure and then etched to form a spacer. An interlayer insulating film is then formed over the entire structure and planarized. The planarization process is performed until the interlayer insulating film is about 2000 kV from the nitride film of the gate pattern.

Referring to FIG. 1C, a photoresist layer is coated on the interlayer insulating layer and patterned so as to cover only the lower gate pattern. Using the photoresist layer as a mask, the lower interlayer insulating film is etched to form contact holes. In this way, when the contact hole is formed, the width of the contact hole exposing the source region is 0.10 μm or less, and the width of the contact hole exposing the drain region is 0.18 μm or less.

As shown in Fig. 1C, in this method, misalignment of the photoresist pattern is likely to occur, and as a result, misalignment of contact holes is likely to occur. Therefore, there is a problem that the gate pattern region is excessively etched (“A” portion of FIG. 1C) or the contact hole is not formed, and the contact hole is also narrowed due to such misalignment. In addition, in the conventional method, since the open area of the cell contact is not large, the method does not apply an end depth point (EDP) process in the etching process and relies on a method of controlling the etching time. However, even with this method, since the thickness of the interlayer insulating film is not uniform, a phenomenon occurs in which the contact is not exposed or the contact hole is excessively etched. As a result, the tungsten silicide layer is exposed when the contact hole is formed due to damage or excessive etching, resulting in gate-to-contact leakage current.

Therefore, in the conventional contact forming method, the area of the source / drain regions of the semiconductor substrate exposed after the formation of the contact hole is small, the contact resistance is not constant, and the cell characteristics are not constant, thereby causing malfunction in the flash memory cell. do.

Recently, a self-aligned contact (SAC) method is used to form a contact in a flash memory cell. In order to reduce the cell size, the design rule of gate-to-contact space is set to "0" using a nitride spacer (NS-SAC). However, even in this SAC process, the substrate may be damaged and there is a problem of leakage current between the gate and the contact. This problem is caused by the lack of resonance margin associated with mask overlay tolerance.

In particular, in the erase operation of the flash memory cell, the voltage difference between the gate and the contact is larger than that of other memory devices such as DRAM. In the DRAM or the like, a voltage difference of about 3 V occurs during an erase operation, but a voltage difference of about 16 V occurs in a flash memory device. This is because when a voltage is applied to the substrate, a discharge phenomenon occurs at the source and drain junctions, resulting in a voltage difference of about 15.3V between the gate and the source contact and the gate and drain contact.

In the conventional SAC etching process, the dry etching is performed to the part where it meets the barrier nitride on the gate to compensate for the large decrease in the contact hole opening area due to the inclination of the dry etching using the nitride selectivity, which is a subsequent step in the conventional SAC etching process. In this case, since there is no selectivity at all, depending on the wafer state, the nitride film on the gate is excessively etched to expose the lower tungsten silicide layer, so that the cell operates properly due to the short of the gate and the contact or excessive leakage current. You will not be able to. In addition, gate-to-source leakage current as well as drain is becoming more of an issue in flash memories that currently employ W Local Interconnection (WLI).

In order to solve this problem, in the present invention, the nitride film is formed to be thicker by 2,000Å than the conventional method, and the interlayer insulating film is flattened to expose the nitride film, so that the overlay accuracy between the source and drain contacts can be ignored during masking process. You can proceed smoothly. In addition, the gate-to-contact leakage current is minimized even when the contact is etched, and the contact opening area can be secured up to about twice as compared to the conventional art, thereby obtaining uniformly improved characteristics in terms of device performance.

An object of the present invention is to form a thick nitride film formed on top of a tungsten silicide layer when forming a flash memory cell, and to planarize the interlayer insulating film to expose the nitride film, thereby preventing contact hole misalignment when forming a contact hole using the SAC process. In addition, it is possible to prevent the increase of leakage current due to over-etching at the same time.

1A to 1C are cross-sectional views sequentially illustrating a method of manufacturing a flash memory cell according to the prior art.

2A through 2C are cross-sectional views sequentially illustrating a method of manufacturing a flash memory cell according to the present invention.

3 is a layout of a flash memory cell array according to the prior art.

4 is a layout of a flash memory cell array in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

100,200: semiconductor substrate 110,210: gate oxide film

120,220: first polysilicon layer 130, 230: dielectric layer

140,240: second polysilicon layer 150,250: tungsten silicide layer

160,260: nitride film 170,270: spacer

180, 280: interlayer insulating film PR: photoresist layer

In order to achieve the above object, a method of manufacturing a flash memory cell of the present invention comprises the steps of sequentially forming a gate oxide film, a first polysilicon layer, a dielectric layer, a second polysilicon layer, a tungsten silicide layer on a semiconductor substrate; Forming a nitride film on the tungsten silicide layer; Forming a gate pattern; Implanting impurity ions on the exposed semiconductor substrate to form a source and a drain; Depositing a spacer nitride film on the entire structure and then etching to form a spacer; Forming and planarizing an interlayer insulating film over the entire structure; And forming a contact hole using a SAC process.

An embodiment of the present invention will now be described in detail with reference to FIGS. 2A-2C.

First, referring to FIG. 2A, a gate oxide film, a first polysilicon layer, a dielectric layer, a second polysilicon layer, a tungsten silicide layer, and a nitride film are sequentially deposited on a semiconductor substrate. In this case, the first polysilicon layer is formed to a thickness of approximately 1600 kPa, the second polysilicon layer is formed to a thickness of approximately 900 kPa, and the tungsten silicide layer is formed to a thickness of approximately 1500 kPa. Here, the nitride film is formed to a thickness of approximately 3700 kPa, which is as thick as 2000 kPa than the conventional technique. Thereafter, etching is performed to form a gate pattern using a photolithography process. The gate pattern thus formed has a width of approximately 0.23 um and a height of 7000 Å. Impurity ion implantation is then performed to form source / drain regions between each gate pattern.

Referring to FIG. 2B, an oxide spacer (not shown) of a double layer of an oxide layer formed by a thermal oxide layer and a deposition process is formed on the sidewall of the gate pattern by using an oxidation process. The nitride layer for the spacer is deposited on the entire structure and then etched to form the spacer. An interlayer insulating film is then formed over the entire structure and planarized to expose the nitride film. In the present invention, since the exact location of the contact (source / drain) can be known when the contact hole is formed by exposing the nitride film as described above, it is possible to prevent the misalignment of the contact hole when forming the contact hole by the SAC process, thereby forming a wide open area of the contact hole. Can be.

Referring to FIG. 2C, contact holes are formed using a SAC process. In this case, a contact hole is formed by using a blanket etching process using no photoresist layer. Using the blanket etching process, the upper edge of the gate structure may be rounded, and an increase in leakage current due to excessive etching may be prevented. As a result of the formation of the contact hole, the contact hole in which the source region is exposed is 0.10 μm or more, and the contact hole in which the drain region is exposed is 0.18 μm or more.

As described above, in the present invention, since the barrier nitride film has a high barrier nitride on the gate, the height of the interlayer insulating film can be etched at a constant height when the interlayer insulating film is etched by CMP, and the drain contact hole and the drain contact hole are used when masking the contact hole. Only the insulation between the source and drain between the source and drain can be opened for SAC etching. Therefore, the weak portion of the gate-to-contact caused by the conventional overlay problem can be eliminated. In addition, since there is no overlay problem, a constant contact opening area can be always ensured, and a larger contact opening area can be obtained in the same cell pitch than the prior art, thereby reducing contact resistance and improving the speed of the device.

Referring to FIG. 3, a plan view of a memory cell array after forming a contact hole according to the related art is shown. As can be seen from this figure, the contact holes are slightly shifted because they are difficult to form in accordance with the original layout in the process. Therefore, the width of the contact hole is narrow.

4, a plan view of a memory cell array after forming contact holes in accordance with the techniques of the present invention is shown. As shown in FIG. 4, it can be seen that the contact hole is formed wide to include the gate area and the contact hole is formed to almost match the original layout. Such a good memory cell array layout is made possible by forming the nitride film of the gate region very thick in the present invention.

As described above, according to the present invention, the formation of a flash memory cell compensates for the misalignment of contact holes when forming a contact hole by forming a thick nitride film formed over the tungsten silicide layer and flattening the interlayer insulating film to expose the nitride film. Therefore, it is possible to improve the characteristics of the device by increasing the open area of the contact hole and at the same time preventing the increase of the leakage current due to the excessive etching.

Claims (8)

Sequentially forming a gate oxide film, a first polysilicon layer, a dielectric layer, a second polysilicon layer, and a tungsten silicide layer on the semiconductor substrate; Forming a nitride film on the tungsten silicide layer; Forming a gate pattern; Implanting impurity ions on the exposed semiconductor substrate to form a source and a drain; Depositing a spacer nitride film on the entire structure and then etching to form a spacer; Forming and planarizing an interlayer insulating film over the entire structure; And A method of manufacturing a flash memory cell comprising the step of forming a contact hole using a SAC process. The method of claim 1, wherein a width of the contact hole is wider to include a gate region. The method of manufacturing a flash memory cell according to claim 1, wherein the nitride film formed on the tungsten silicide layer is formed to a thickness of 3,700 Å. The flash memory cell of claim 1, wherein the first polysilicon layer is formed to a thickness of 600 kPa, the second polysilicon layer is formed to a thickness of 900 kPa, and the tungsten silicide layer is formed to a thickness of 1500 kPa. Method of preparation. The method of claim 1, wherein both edges of the nitride film are etched in a round shape after the SAC process. The method of claim 1, wherein the interlayer insulating layer is etched to expose the nitride layer when the interlayer insulating layer is formed and planarized. The method of claim 1, wherein a blanket etching process is used to form a contact hole using the SAC process. The method of claim 1, wherein the contact hole is formed using a SAC process.