KR20050122294A - Method for manufacturing a transistor of semiconductor device - Google Patents
Method for manufacturing a transistor of semiconductor device Download PDFInfo
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- KR20050122294A KR20050122294A KR1020040047350A KR20040047350A KR20050122294A KR 20050122294 A KR20050122294 A KR 20050122294A KR 1020040047350 A KR1020040047350 A KR 1020040047350A KR 20040047350 A KR20040047350 A KR 20040047350A KR 20050122294 A KR20050122294 A KR 20050122294A
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 239000010408 film Substances 0.000 claims abstract description 65
- 239000010409 thin film Substances 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000010030 laminating Methods 0.000 claims abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 230000002093 peripheral effect Effects 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000007943 implant Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 17
- 230000009977 dual effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 30
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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Abstract
듀얼 게이트를 갖는 반도체 소자의 트랜지스터 제조 방법에서, 반도체 기판의 제1 영역 및 제2 영역 상에 게이트 산화막, 폴리실리콘막, 도전막 및 하드 마스크막을 차례로 적층하여 다층 박막을 형성한다. 상기 하드마스크 막의 일부를 이방성 식각하여 상기 제1 및 제2 영역 상의 다층박막 간에 단차가 형성되게 한다. 상기 단차가 형성된 다층 박막을 이방성 식각하여 게이트 패턴들을 형성한다. 상기 게이트 패턴들 사이에 노출된 상기 기판 상에 불순물 이온을 주입하여 소오스/드레인 영역을 형성한다. 따라서 상기와 같이 단차가 형성된 게이트 패턴들을 포함하는 반도체 소자의 트랜지스터는 불순물 이온을 주입하기 위한 틸트(tilt) 각도 등 이온 주입 조건이 개선되어 이온주입 공정을 용이하게 수행하므로써 반도체 소자의 특성 및 신뢰성을 향상시킬 수 있다.In the transistor manufacturing method of a semiconductor device having a dual gate, a multi-layer thin film is formed by sequentially laminating a gate oxide film, a polysilicon film, a conductive film, and a hard mask film on the first region and the second region of the semiconductor substrate. A portion of the hard mask film is anisotropically etched so that a step is formed between the multilayer thin films on the first and second regions. Gate patterns are formed by anisotropically etching the multilayer thin film on which the step is formed. Impurity ions are implanted on the substrate exposed between the gate patterns to form a source / drain region. Therefore, the transistor of the semiconductor device including the stepped gate patterns as described above improves ion implantation conditions such as a tilt angle for implanting impurity ions, thereby easily performing the ion implantation process, thereby improving the characteristics and reliability of the semiconductor device. Can be improved.
Description
본 발명은 반도체 장치에서 트랜지스터 제조 방법에 관한 것으로, 보다 상세하게는 듀얼 게이트를 갖는 반도체 소자의 트랜지스터 제조 방법에 관한 것이다. The present invention relates to a transistor manufacturing method in a semiconductor device, and more particularly to a transistor manufacturing method of a semiconductor device having a dual gate.
일반적으로 저전력(low power), 고집적, 고성능(high performance)을 갖는 반도체 소자를 개발하기 위해서는 우수한 트랜지스터 개발이 필수적이다. 이를 위해서는 게이트 산화막, 채널 길이, 게이트 등을 축소할 필요가 있다. 또한, 상기한 요소들을 축소하더라도 트랜지스터의 특성이 충분히 확보되어야 한다. In general, in order to develop a semiconductor device having low power, high integration, and high performance, excellent transistor development is essential. To this end, it is necessary to reduce the gate oxide film, the channel length, the gate, and the like. In addition, even if the above elements are reduced, the characteristics of the transistor must be sufficiently secured.
DRAM 장치에서의 트랜지스터 제조 공정을 간단히 살펴보면, 우선 게이트 구조물을 형성한 이 후, 상기 게이트 구조물을 이온 주입 마스크로 하여 상기 게이트 구조물 양측으로 소오스/드레인을 형성하기 위한 이온 주입 공정을 수행한다. 이어서, 상기 게이트 구조물을 매립하는 층간 절연막을 형성한다. 다음에, 상기 층간 절연막의 소정 부위를 자기 정렬 방식으로 식각하여 상기 소오스/드레인 영역과 전기적으로 접속하는 자기 정렬 콘택홀을 형성하고, 상기 자기 정렬 콘택홀 내에 도전 물질을 매립하여 자기 정렬 콘택을 형성한다. Briefly referring to a transistor fabrication process in a DRAM device, first a gate structure is formed, and then an ion implantation process is performed to form a source / drain on both sides of the gate structure using the gate structure as an ion implantation mask. Subsequently, an interlayer insulating layer filling the gate structure is formed. Next, a predetermined portion of the interlayer insulating layer is etched in a self-aligned manner to form a self-aligned contact hole electrically connecting with the source / drain regions, and a conductive material is embedded in the self-aligned contact hole to form a self-aligned contact. do.
이 때, 상기 게이트 구조물의 높이는 자기정렬 콘택홀을 형성하기 위한 식각 공정시에 숄더 마진에 의해서 결정된다. 그런데, 최근의 DRAM 장치의 경우 숄더 마진이 매우 감소하고 있어서, 상기 게이트 구조물의 높이는 점점 더 높아지고 있다. 또한, 상기 게이트 구조물들 간의 간격은 매우 감소되고 있다. At this time, the height of the gate structure is determined by the shoulder margin during the etching process to form a self-aligned contact hole. However, in recent DRAM devices, the shoulder margin is greatly reduced, and the height of the gate structure is increasing. In addition, the spacing between the gate structures is greatly reduced.
때문에, 상기 게이트 구조물을 이온 주입 마스크로 소오스/드레인을 형성하기 위한 이온주입 공정을 수행할 시에 공정조건이 제한될 수 밖에 없다.Therefore, process conditions are inevitably limited in performing the ion implantation process for forming the source / drain using the gate structure as an ion implantation mask.
상기와 같은 문제점을 해결하기 위한 본 발명의 목적은 소오스/드레인 영역을 형성하기 위한 이온 주입 시에 공정 조건에 제한을 최소화할 수 있는 반도체 소자의 트랜지스터 제조 방법을 제공하는 데 있다.An object of the present invention for solving the above problems is to provide a transistor manufacturing method of a semiconductor device capable of minimizing the limitation on the process conditions at the time of ion implantation for forming the source / drain region.
상기 본 발명의 목적을 달성하기 위하여 본 발명의 일 실시예에 따른 반도체 소자의 트랜지스터 제조 방법은, 반도체 기판에 셀 영역을 정의하는 제1 영역과 코아/주변 영역을 정의하는 제2 영역 상에 게이트 산화막, 폴리실리콘막, 도전막 및 하드 마스크막을 차례로 적층하여 다층 박막을 형성한다. 상기 제2 영역 상의 다층 박막에 포함된 하드 마스크막의 일부를 이방성 식각하여 상기 제1 영역 상에 형성된 다층 박막과 상기 제2 영역 상에 형성된 다층 박막 간에 단차가 형성되도록 한다. 상기 제1 영역 및 제2 영역 상에 형성된 다층 박막을 패터닝하여 게이트 패턴들을 형성한다. 상기 게이트 패턴들 사이에 노출된 상기 기판 상에 불순물 이온을 주입하여 소오스/드레인 영역을 형성한다.In order to achieve the object of the present invention, a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention, a gate on a first region defining a cell region and a second region defining a core / peripheral region on a semiconductor substrate. An oxide film, a polysilicon film, a conductive film, and a hard mask film are stacked in this order to form a multilayer thin film. A portion of the hard mask film included in the multilayer thin film on the second region is anisotropically etched so that a step is formed between the multilayer thin film formed on the first region and the multilayer thin film formed on the second region. Gate patterns are formed by patterning the multilayer thin film formed on the first region and the second region. Impurity ions are implanted on the substrate exposed between the gate patterns to form a source / drain region.
상술한 바와 같은 본 발명에 따르면, 셀 영역 상에 형성된 게이트 패턴들과 코아/주변 영역 상에 형성된 게이트 패턴들 간의 높이를 상이하게 하여, 불순물 이온을 주입하기 위한 틸트(tilt) 각도 등 이온 주입 조건이 개선되어 이온주입 공정을 용이하게 수행하므로써 반도체 소자의 특성 및 신뢰성을 향상시킬 수 있다.According to the present invention as described above, the ion implantation conditions such as the tilt angle for implanting impurity ions by varying the height between the gate patterns formed on the cell region and the gate patterns formed on the core / peripheral region This improvement makes it possible to easily perform the ion implantation process, thereby improving the characteristics and reliability of the semiconductor device.
이하, 본 발명에 따른 바람직한 일 실시예를 첨부된 도면을 참조하여 상세하게 설명한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 7은 본 발명의 일 실시예에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 공정 단면도들이다.1 to 7 are cross-sectional views illustrating a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention.
도 1을 참조하면, 반도체 기판(100)에 셸로우 트렌치 소자 분리 공정을 수행하여 소자분리 영역(120)을 한정하고, 이에 따라 활성 영역을 정의한다. 또한, 상기 반도체 기판에서, 메모리 셀이 형성되기 위한 제1 영역(C) 과 상기 메모리 셀에 외부 신호를 가하기 위한 주변 회로들이 형성되기 위한 제 2 영역을 각각 지정한다.Referring to FIG. 1, a shallow trench device isolation process is performed on a semiconductor substrate 100 to define a device isolation region 120, thereby defining an active region. In the semiconductor substrate, a first region C for forming a memory cell and a second region for forming peripheral circuits for applying an external signal to the memory cell are designated.
상기 제1 영역(C) 및 제2 영역(P) 상에 게이트 산화막(140), 폴리실리콘막(160), 도전막(180) 및 하드 마스크막(200)을 차례로 적층하여 다층 박막을 형성한다.A multi-layered thin film is formed by sequentially stacking the gate oxide layer 140, the polysilicon layer 160, the conductive layer 180, and the hard mask layer 200 on the first region C and the second region P. .
상기 도전막(180)은 텅스텐 실리사이드(WSiX)막으로 형성하거나, 또는 텅스텐 질화(WN)막 및 텅스텐(W)막이 차례로 적층된 복합막으로 형성할 수 있다. 상기 하드 마스크막(200)은 실리콘 질화(SiN)막으로 형성할 수 있다. The conductive layer 180 may be formed of a tungsten silicide (WSiX) layer or a composite layer in which a tungsten nitride (WN) layer and a tungsten (W) layer are sequentially stacked. The hard mask layer 200 may be formed of a silicon nitride (SiN) layer.
상기 폴리실리콘막(160), 도전막(180) 및 하드 마스크막(200)의 두께는 반도체 소자의 특성 등을 고려하여 결정되며, 특히 상기 하드 마스크막(200)의 두께는 후속 자기정렬 콘택 공정에서의 숄더 마진을 고려하여 결정하는 것이 바람직하다. The thicknesses of the polysilicon layer 160, the conductive layer 180, and the hard mask layer 200 are determined in consideration of characteristics of the semiconductor device, and the thickness of the hard mask layer 200 is a subsequent self-aligned contact process. It is desirable to determine the shoulder margin at.
예컨대, 본 발명에 적용되는 상기 각 막의 두께를 살펴보면, 상기 폴리실리콘막(160)은 600~800Å, 상기 도전막(180)은 1000~1200Å, 상기 하드 마스크막(200)은 1800~2200Å의 두께로 형성할 수 있다. 그러나, 상기 막의 두께는 상기 기재된 두께에 한정되지는 않는다. For example, when looking at the thickness of each film applied to the present invention, the polysilicon film 160 is 600 ~ 800Å, the conductive film 180 is 1000 ~ 1200Å, the hard mask film 200 has a thickness of 1800 ~ 2200Å It can be formed as. However, the thickness of the film is not limited to the thickness described above.
도 2를 참조하면, 상기 제1 영역(C) 및 제2 영역(P) 상에 형성된 다층 박막 상에 제1 포토레지스트막(미도시)을 형성한다. 상기 제2 영역(P) 상에 형성된 다층 박막이 선택적으로 노출되도록 노광 및 현상 공정을 통하여 상기 제1 포토레지스트막(미도시)을 패터닝한다. Referring to FIG. 2, a first photoresist film (not shown) is formed on the multilayer thin film formed on the first region C and the second region P. Referring to FIG. The first photoresist film (not shown) is patterned through an exposure and development process so that the multilayer thin film formed on the second region P is selectively exposed.
상기 패터닝 결과 상기 제1 영역(C) 상에 형성된 다층 박막 상에는 제1 포토레지스트 패턴(220a)이 형성된다. As a result of the patterning, a first photoresist pattern 220a is formed on the multilayer thin film formed on the first region C.
도 3을 참조하면, 상기 제1 영역(C) 상에 형성된 다층 박막과 상기 제2 영역(P) 상에 형성된 다층 박막 간에 단차가 형성되도록 상기 제2 영역(P) 상의 다층 박막에 포함된 하드 마스크막(200)의 일부를 이방성 식각한다. 이때, 상기 제1 영역(C) 상에 형성된 다층 박막은 상기 제1 포토레지스트 패턴(220a)에 의해 식각되지 않는다. Referring to FIG. 3, hard included in the multilayer thin film on the second region P such that a step is formed between the multilayer thin film formed on the first region C and the multilayer thin film formed on the second region P. A portion of the mask film 200 is anisotropically etched. In this case, the multilayer thin film formed on the first region C is not etched by the first photoresist pattern 220a.
상기 하드 마스크막(200)에 대한 이방성 식각 공정은 상기 제2 영역(P) 상의 다층 박막에 포함된 도전막(180)이 노출되지 않는 범위에서 상기 이방성 식각의 허용 한도까지 수행되는 것이 바람직하다.The anisotropic etching process for the hard mask layer 200 may be performed to an allowable limit of the anisotropic etching in a range where the conductive layer 180 included in the multilayer thin film on the second region P is not exposed.
상기 이방성 식각이 수행된 후 상기 제1 포토레지스트 패턴(220a)은 통상의 애싱 스트립 공정에 의해 제거된다.After the anisotropic etching is performed, the first photoresist pattern 220a is removed by a conventional ashing strip process.
이상에서와 같이, 상기 제1 영역(C) 및 제2 영역(P) 상에 상기 하드 마스크 막(200)의 높이를 다르게 형성하므로써, 후속 공정에 의해 수반되는 상기 제1 영역(C) 및 제2 영역(P) 상에 형성되는 게이트 패턴(300)들 간에 단차를 형성할 수 있도록 한다. As described above, by differently forming the height of the hard mask film 200 on the first region C and the second region P, the first region C and the first process, which are accompanied by a subsequent process, are formed. It is possible to form a step between the gate patterns 300 formed on the second region (P).
도 4를 참조하면, 상기 이방성 식각 공정에 의해 단차가 형성된 다층 박막 상에 반사 방지막(240)을 형성한다.Referring to FIG. 4, an anti-reflection film 240 is formed on the multilayer thin film in which the step is formed by the anisotropic etching process.
상기 반사 방지막(240)은 유기물 소오스 또는 무기물 소오스를 사용하여 형성한다. 상기 유기물 소오스의 예로서는 테트라키스-디메틸아미도티타늄(TDMAT), 테트라키스-디에틸아미도티타늄(TDEAT) 등을 들 수 있고, 상기 무기물 소오스의 예로서는 실리콘 산질화(SiON)물 등을 들 수 있다.The anti-reflection film 240 is formed using an organic source or an inorganic source. Examples of the organic source include tetrakis-dimethylamidotitanium (TDMAT), tetrakis-diethylamidotitanium (TDEAT), and the like. Examples of the inorganic source include silicon oxynitride (SiON). .
도 5를 참조하면, 상기 반사 방지막(240) 상에 제2 포토레지스트막(미도시)을 형성하고, 노광 및 현상 공정을 통하여 제2 포토레지스트 패턴(260a)들을 형성한다. Referring to FIG. 5, a second photoresist film (not shown) is formed on the anti-reflection film 240, and second photoresist patterns 260a are formed through an exposure and development process.
일반적으로 포토레지스트막의 높이가 상이한 상태에서 포토레지스트막을 패터닝하는 경우 포토레지스트 패턴의 프로파일(profile)을 균일하게 형성할 수 없는 것이 보통이다. 그러나 이러한 문제는 반사 방지막을 사용하므로써 개선될 수 있다.In general, when the photoresist film is patterned in a state where the height of the photoresist film is different, it is common that the profile of the photoresist pattern cannot be uniformly formed. However, this problem can be improved by using an antireflection film.
따라서, 본 발명에 따른 상기 제2 포토레지스트 패턴(260a)들의 프로파일은 상기 반사 방지막(240)에 의해 균일한 형태로 형성될 수 있다. 이는 상기 제2 포토레지스트막(미도시)이 노광될 때 상기 반사 방지막(240)에 의해 빛의 반사율이 균일하게 조절되기 때문이다.Therefore, the profile of the second photoresist patterns 260a according to the present invention may be formed in a uniform shape by the anti-reflection film 240. This is because the reflectance of light is uniformly adjusted by the anti-reflection film 240 when the second photoresist film (not shown) is exposed.
상기 제2 포토레지스트 패턴(260a)들을 식각 마스크로 사용하여 상기 반사 방지막(240) 및 상기 하드 마스크막(200)을 부분적으로 이방성 식각하여 반사 방지막 패턴(240a)들 및 하드 마스크막 패턴(200a)들을 형성한다. 상기 하드 마스크막 패턴(200a)들은 게이트 패턴(300)들을 형성하기 위한 식각 마스크로 사용된다.The anti-reflection film 240 and the hard mask film 200 are partially anisotropically etched using the second photoresist pattern 260a as an etch mask to form the anti-reflection film patterns 240a and the hard mask film pattern 200a. Form them. The hard mask layer patterns 200a may be used as an etch mask for forming the gate patterns 300.
상기 반사 방지막 패턴(240a)들은 에싱 스트립 공정에 의해 상기 제2 포토레지스트 패턴(260a)들과 함께 제거된다.The anti-reflection film patterns 240a are removed together with the second photoresist patterns 260a by an ashing strip process.
도 6을 참조하면, 상기 하드 마스크막 패턴(200a)들을 식각 마스크로 사용하여 상기 도전막(180), 폴리실리콘막(160) 및 게이트 산화막(140)을 패터닝한다. 상기 패터닝에 의해 형성된 도전막 패턴(180a)들, 폴리실리콘막 패턴(160a)들 및 게이트 산화막 패턴(140a)들은 상기 하드 마스크막 패턴(200a)들과 함께 제1 영역(C) 및 제2 영역(P) 상에 게이트 패턴(300)들을 형성한다.Referring to FIG. 6, the conductive layer 180, the polysilicon layer 160, and the gate oxide layer 140 are patterned using the hard mask layer patterns 200a as an etch mask. The conductive layer patterns 180a, the polysilicon layer patterns 160a, and the gate oxide layer patterns 140a formed by the patterning may be formed together with the hard mask layer patterns 200a and the first region C and the second region. Gate patterns 300 are formed on (P).
상기 게이트 패턴(300)들의 높이를 살펴보면, 상기 제2 영역(P) 상에 형성되는 게이트 패턴(300)들의 높이가 상기 제1 영역(C) 상에 형성되는 게이트 패턴(300)들의 높이보다 더 낮게 형성된다. Looking at the height of the gate pattern 300, the height of the gate pattern 300 formed on the second region (P) is greater than the height of the gate pattern 300 formed on the first region (C). Formed low.
상기 제1 영역(C) 및 제2 영역(P) 상에 형성되는 게이트 패턴(300)들 사이에 노출된 상기 반도체 기판 상에 불순물 이온을 주입하여 소오스/드레인 영역(280)을 형성한다.The source / drain regions 280 are formed by implanting impurity ions onto the semiconductor substrate exposed between the gate patterns 300 formed on the first region C and the second region P. FIG.
이때, 상기 제2 영역(P) 상에 형성되는 게이트 패턴(300)들의 높이가 상기 제1 영역 상에 형성되는 게이트 패턴(300)들의 높이보다 낮기 때문에, 상기 불순물 이온을 주입하기 위한 틸트(tilt) 각도(θ, φ)의 범위는 상기 제1 영역(C)보다 상기 제2 영역(P)에서 더 크게 된다. 이와 같은 이온 주입 공정은 통상적으로 15°내지 45°의 틸트 각도의 범위에서 진행된다. In this case, since the height of the gate patterns 300 formed on the second region P is lower than the height of the gate patterns 300 formed on the first region, the tilt for implanting the impurity ions is performed. The range of angles θ and φ is larger in the second region P than in the first region C. Such ion implantation processes typically proceed in the range of tilt angles of 15 ° to 45 °.
그러나, 종래와 같이 셀 영역 및 코아/주변 영역 상에 형성되는 게이트 패턴들이 동일한 상태에서의 이온 주입 공정은 주변 게이트 패턴들에 의한 쉐도우잉(shadowing) 현상으로 틸트 각도의 범위가 제한을 받게 된다.However, the ion implantation process in which the gate patterns formed on the cell region and the core / peripheral region are the same as in the related art is limited by a range of tilt angles due to shadowing caused by peripheral gate patterns.
그리하여, 본 발명은 상기 제1 영역(C) 상에 형성되는 게이트 패턴(300)들과 상기 제2 영역(P) 상에 형성되는 게이트 패턴(300)들 간에 높이를 다르게 하므로서, 상기 제2 영역(P)에서 수행되는 이온 주입 공정은 주변 게이트 패턴들(300)에 의한 쉐도우잉(shadowing) 현상에 따른 영향을 최소화할 수 있으므로 틸트 각도 범위에 제한을 거의 받지 않게된다. .Thus, according to the present invention, the height is varied between the gate patterns 300 formed on the first region C and the gate patterns 300 formed on the second region P, and thus, the second region. Since the ion implantation process performed at (P) may minimize the influence of shadowing caused by the peripheral gate patterns 300, the ion implantation process is hardly limited to the tilt angle range. .
도 7을 참조하면, 상기 게이트 패턴(300)들이 노출되지 않도록 상기 게이트 패턴(300)들 상부에 스페이서용 절연막(미도시)을 형성한다. 상기 스페이서용 절연막(미도시)은 실리콘질화막으로 형성하는 것이 바람직하다.Referring to FIG. 7, an insulating layer (not shown) for spacers is formed on the gate patterns 300 so that the gate patterns 300 are not exposed. The spacer insulating film (not shown) is preferably formed of a silicon nitride film.
상기 스페이서용 절연막(미도시)을 에치백하여 상기 게이트 패턴(300)들 측벽에 스페이서(320)를 형성한다.The spacers 320 are formed on sidewalls of the gate patterns 300 by etching back the spacer insulating layer (not shown).
따라서, 본 발명에 따라 형성된 반도체 소자의 트랜지스터에 의하면, 상기 셀 영역에 형성되는 게이트 패턴들과 상기 코아/주변 영역 상에 형성되는 게이트 패턴들 간에 높이를 상이하게 형성하므로써, 틸트 각도 등 이온 주입 조건을 개선시켜 소오스/드레인을 형성하기 위한 이온 주입 공정을 용이하게 수행하여 반도체 소자의 특성 및 신뢰성을 향상시킬 수 있다.Therefore, according to the transistor of the semiconductor device formed according to the present invention, by forming a height different between the gate patterns formed in the cell region and the gate patterns formed on the core / peripheral region, ion implantation conditions such as tilt angle The ion implantation process for forming the source / drain may be easily performed to improve the characteristics and reliability of the semiconductor device.
상기와 같은 본 발명의 바람직한 일 실시예에 따르면, 셀 영역 상에 형성되는 게이트 패턴들의 높이보다 코아/주변 영역 상에 형성되는 게이트 패턴들의 높이를 낮게 하여 상기 게이트 패턴들 간에 단차를 형성한다. 따라서, 상기 게이트 패턴들을 이용하는 트랜지스터의 개발에서 소오스/드레인 정션 부위에 틸트(tilt) 각도 등 이온 주입 조건이 개선된다. 그리하여, 상기 소오스/드레인 정션 부위에 이온주입 공정을 용이하게 수행하여 반도체 소자의 특성 및 신뢰성을 향상시킬 수 있다.According to an exemplary embodiment of the present invention as described above, the height of the gate patterns formed on the core / peripheral region is lower than the height of the gate patterns formed on the cell region to form a step between the gate patterns. Therefore, in the development of the transistor using the gate patterns, ion implantation conditions such as a tilt angle in the source / drain junction region are improved. Thus, an ion implantation process may be easily performed on the source / drain junction to improve characteristics and reliability of the semiconductor device.
상기에서 본 발명의 바람직한 실시예를 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.Although described above with reference to the preferred embodiment of the present invention, those skilled in the art various modifications and variations of the present invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.
도 1 내지 도 7은 본 발명의 일 실시예에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 공정 단면도들이다.1 to 7 are cross-sectional views illustrating a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on main parts of drawing
100 : 반도체 기판 120 : 소자분리 영역100 semiconductor substrate 120 device isolation region
140 : 게이트 산화막 140a : 게이트 산화막 패턴140: gate oxide film 140a: gate oxide film pattern
160 : 폴리실리콘막 160a : 폴리실리콘막 패턴160: polysilicon film 160a: polysilicon film pattern
180 : 도전막 180a : 도전막 패턴180: conductive film 180a: conductive film pattern
200 : 하드 마스크막 200a : 하드 마스크막 패턴200: hard mask film 200a: hard mask film pattern
220a : 제1 포토레지스트 패턴 240 : 반사 방지막220a: first photoresist pattern 240: antireflection film
240a : 반사 방지막 패턴 260a : 제2 포토레지스트 패턴240a: antireflection film pattern 260a: second photoresist pattern
280 : 소오스/드레인 영역 300 : 게이트 패턴280: source / drain region 300: gate pattern
320 : 스페이서 C : 제1 영역320: spacer C: first region
P : 제2 영역 θ,φ: 틸트(tilt) 각도P: second area θ, φ: tilt angle
Claims (8)
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US8936983B2 (en) | 2010-12-15 | 2015-01-20 | SK Hynix Inc. | Method of fabricating a semiconductor memory device |
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