KR20030000596A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20030000596A KR20030000596A KR1020010036633A KR20010036633A KR20030000596A KR 20030000596 A KR20030000596 A KR 20030000596A KR 1020010036633 A KR1020010036633 A KR 1020010036633A KR 20010036633 A KR20010036633 A KR 20010036633A KR 20030000596 A KR20030000596 A KR 20030000596A
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- Prior art keywords
- silicon substrate
- trench
- pad
- oxide film
- semiconductor device
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 38
- 239000010703 silicon Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 150000004767 nitrides Chemical class 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 11
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000001257 hydrogen Substances 0.000 claims abstract description 9
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000002955 isolation Methods 0.000 abstract description 13
- 238000005530 etching Methods 0.000 abstract description 8
- 238000000137 annealing Methods 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000002244 precipitate Substances 0.000 description 2
- 239000011856 silicon-based particle Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는 트렌치 식각후 수소 어닐링 처리하여 트렌치의 손상을 개선시킬 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving damage to a trench by hydrogen annealing after trench etching.
일반적으로, 반도체 소자는 개개의 회로 패턴을 전기적으로 분리하기 위한 소자 분리 영역을 포함한다. 특히, 반도체 소자가 고집적화 되고 미세화되어 감에 따라 각 개별 소자의 크기를 축소시키는 것 뿐만 아니라 소자 분리 영역의 축소에 대한 연구가 활발히 진행되고 있다.Generally, semiconductor devices include device isolation regions for electrically separating individual circuit patterns. In particular, as semiconductor devices become highly integrated and miniaturized, research on not only reducing the size of each individual device but also reducing the device isolation region is actively conducted.
그 이유는 소자 분리 영역의 형성은 모든 반도체 소자의 제조 단계의 초기 단계로서 활성 영역의 크기 및 후공정 단계의 공정 마진을 좌우하기 때문이다.The reason for this is that the formation of device isolation regions is an initial step in the fabrication of all semiconductor devices, and the size of the active area and the process margin of the post-process step.
최근에, 반도체 소자의 제조에 널리 이용되는 로코스(LOCOS) 소자 분리 방법은 반도체 소자의 고집적화 되어감에 따라 그 한계점이 이르렀다.In recent years, the LOCOS device isolation method widely used in the manufacture of semiconductor devices has reached its limit as the semiconductor devices are highly integrated.
이에 따라 고집적화된 반도체 소자의 소자 분리에 적합한 기술로는 트렌치를 이용한 트렌치 분리(TRENCH ISOLATION) 방법이 제안되었다.Accordingly, as a technique suitable for device isolation of highly integrated semiconductor devices, a trench isolation method using trenches has been proposed.
이러한 트렌치 분리 방법은, 도면에는 도시하지 않았지만, 실리콘 기판상에 패드 산화막 및 패드 질화막을 형성한 후, 포토리소그래피 공정기술 및 식각 공정을 통해 상기 패드 질화막, 패드 산화막 및 실리콘 기판을 선택적으로 제거하여 트렌치를 형성하고 이로써 소자 영역을 형성하였다.Although not shown in the drawing, the trench isolation method may form a pad oxide film and a pad nitride film on a silicon substrate, and then selectively remove the pad nitride film, the pad oxide film, and the silicon substrate through photolithography and etching. Was formed, thereby forming the device region.
위와 같은 공정을 통해 소자 분리 영역이 최소화되고, 기판과의 단차가 거의 존재하지 않아 이후의 공정을 진행하는데 어려움 등이 없는 효과가 얻을 수 있다.Through the above process, the device isolation region is minimized, and since there is almost no step with the substrate, it is possible to obtain an effect without difficulty in the subsequent process.
그러나, 상기 종래 기술에 따른 반도체 소자의 제조 방법에 있어서는 다음과 같은 문제점이 있다.However, there is the following problem in the method of manufacturing a semiconductor device according to the prior art.
종래 기술에 있어서는 실리콘 기판을 에칭하는 과정에서 실리콘 기판에 손상(DAMAGE)을 가하게 되는데, 이러한 실리콘 기판의 손상을 제거하기 위하여 종래에는 트렌치 에칭후 실리콘 산화 공정을 진행하였다. 이와 같은 실리콘 산화 공정을 이용할 경우, 실리콘 기판 표면은 일부가 손실되어 소자 분리 영역의 임계치수(CRITICAL DIMENSION)가 증가하게 되는 문제점이 있다.In the prior art, a damage (DAMAGE) is applied to the silicon substrate in the process of etching the silicon substrate. In order to remove the damage of the silicon substrate, the silicon oxidation process is performed after the trench etching. When using such a silicon oxidation process, a portion of the surface of the silicon substrate is lost, thereby increasing the CRITICAL DIMENSION of the device isolation region.
또한, 종래 기술에 있어서는 실리콘 기판의 손상을 제거하기 위해 실리콘 산화 공정을 수차례 진행하여야 하며 실리콘 손상 제거를 위한 산화막 형성에서 산화막과 실리콘의 팽창계수 차이로 트렌치에 응력(STRESS)을 증가시켜 손상을 유발할 수 있는 문제점도 있었다.In addition, in the prior art, the silicon oxide process has to be carried out several times to remove the damage of the silicon substrate, and the stress is increased by increasing the stress in the trench due to the difference in the expansion coefficient between the oxide film and silicon in forming the oxide film to remove the silicon damage. There was also a problem that could be caused.
이에, 본 발명은 상기 종래 기술의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 실리콘 에칭후에 수소 어닐릴 처리하여 실리콘 기판의 손상을 개선시킬 수 있는 반도체 소자의 제조 방법을 제공함에 있다.Accordingly, the present invention has been made to solve the problems of the prior art, an object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the damage of the silicon substrate by hydrogen annealing after silicon etching.
도 1 내지 4는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 공정별 단면도.1 to 4 are cross-sectional views for each process for explaining a method of manufacturing a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호설명** Explanation of Codes on Major Parts of Drawings *
10:실리콘 기판20:패드 산화막10 silicon substrate 20 pad oxide film
30:패드 질화막40:감광막 패턴30: pad nitride film 40: photosensitive film pattern
50,50a:트렌치60:매립용 산화막50, 50a: trench 60: buried oxide film
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조 방법은, 실리콘 기판상에 패드 산화막 및 패드 질화막을 순차적으로 형성한 후, 상기 질화막상에 감광막 패턴을 형성하는 단계; 상기 감광막 패턴을 마스크로 상기 패드 질화막, 패드 산화막 및 실리콘 기판을 선택적으로 제거하여 트렌치를 형성하는 단계; 상기 감광막 패턴을 제거한 후, 실리콘 기판을 일정 온도와 수소 분위기에서 열처리하는 단계; 및 상기 실리콘 기판의 트렌치를 포함한 전체 구조의 상면에 매립용 산화막을 형성한 후 화학적 기계적 연마로 상기 매립용 산화물을 선택적으로 제거한 다음, 상기 패드 질화막 및 패드 산화막을 제거하여 평탄화하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: sequentially forming a pad oxide film and a pad nitride film on a silicon substrate, and then forming a photoresist pattern on the nitride film; Forming a trench by selectively removing the pad nitride film, the pad oxide film, and the silicon substrate using the photoresist pattern as a mask; Removing the photoresist pattern, and then heat treating the silicon substrate at a constant temperature and a hydrogen atmosphere; And forming a buried oxide film on the upper surface of the entire structure including the trench of the silicon substrate, selectively removing the buried oxide by chemical mechanical polishing, and then removing the planarized film by removing the pad nitride film and the pad oxide film. It features.
이하, 본 발명에 따른 반도체 소자의 제조 방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 4는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 공정별 단면도이다.1 to 4 are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 제조 방법은, 도 1에 도시된 바와 같이, 실리콘 기판(10)상에 버퍼 역할을 하는 패드 산화막(20)과 산화를 억제하는 패드 질화막(30)을 순차적으로 증착하여 형성한 후, 상기 패드 질화막(30) 상면에 소자 분리 영역을 형성하기 위한 감광막 패턴(40)을 형성한다.In the method of manufacturing a semiconductor device according to the present invention, as illustrated in FIG. 1, a pad oxide film 20 serving as a buffer and a pad nitride film 30 inhibiting oxidation are sequentially deposited on a silicon substrate 10. After the formation, the photoresist layer pattern 40 is formed on the upper surface of the pad nitride layer 30 to form an isolation region.
그 다음, 도 2에 도시된 바와 같이, 상기 감광막 패턴(40)을 마스크로 상기 패드 질화막(30), 패드 산화막(20) 및 실리콘 기판(10)을 일정 깊이만큼 선택적으로 식각하여 트렌치(50)를 형성한다. 이때, 상기 실리콘 기판(1)의 트렌치(50) 내부는 식각에 의한 응력(STRESS) 및 상기 실리콘 기판(1)내의 실리콘침입(SILICON INTERSTITIAL)으로 인해 도 2의 "A"와 같이 손상(DAMAGE)이 된다.Next, as illustrated in FIG. 2, the pad nitride layer 30, the pad oxide layer 20, and the silicon substrate 10 may be selectively etched by a predetermined depth using the photoresist pattern 40 as a mask to form a trench 50. To form. At this time, the inside of the trench 50 of the silicon substrate 1 is damaged (DAMAGE) as shown in "A" of FIG. 2 due to the stress (STRESS) by etching and the silicon infiltration (SILICON INTERSTITIAL) in the silicon substrate (1). Becomes
이어서, 도 3에 도시된 바와 같이, 상기 감광막 패턴(40)을 제거하고, 일정온도, 예를 들어 섭씨 약 1,000도 이상의 고온으로 수소 분위기하에서 상기 실리콘 기판(10)을 열처리(ANNEALING)한다. 이때, 이러한 고온 열처리를 진행하면 고온의 열에 상기 실리콘 기판(10)내의 실리콘 입자가 확산을 하게 되고, 이로 인하여 응력이 집중되어 있는 상기 트렌치부는 응력 완화(STRESS RELIEF) 및 결함(DEFECT)과 결합되어 있는 실리콘 입자의 이동 및 재배열을 촉진시켜 손상(DAMAGE)이 제거된 트렌치(50a)가 형성된다.Next, as shown in FIG. 3, the photoresist pattern 40 is removed, and the silicon substrate 10 is heat-treated under a hydrogen atmosphere at a constant temperature, for example, a high temperature of about 1,000 degrees Celsius or more. At this time, when the high temperature heat treatment is performed, the silicon particles in the silicon substrate 10 diffuse into the high temperature heat, and thus the trench in which the stress is concentrated is coupled with the stress relief and the defect. A trench 50a is formed in which damage (DAMAGE) is removed by promoting movement and rearrangement of the silicon particles present.
그 다음, 도 4에 도시된 바와 같이, 손상이 제거된 트렌치(50a)내를 매립하는 매립용 산화막(60:GAP FILL OXIDE)을 전체 구조의 상면에 형성한 후, 상기 패드 질화막(30)이 노출되도록 상기 매립용 산화막(60)을 평탄화한 다음, 상기 패드 질화막(30) 및 패드 화막(20)을 차례로 제거하여 평탄화시킨다.Then, as shown in FIG. 4, after forming a buried oxide film 60 (GAP FILL OXIDE) that fills the trench 50a from which damage is removed, the pad nitride film 30 is formed. The buried oxide film 60 is planarized to be exposed, and then the pad nitride film 30 and the pad nitride film 20 are sequentially removed and planarized.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 살펴 본 바와 같이 본 발명에 따른 반도체 소자의 제조 방법에 있어서는 다음과 같은 효과가 있다.As described above, the manufacturing method of the semiconductor device according to the present invention has the following effects.
소자 분리용 트렌치 형성을 위한 식각 공정시 실리콘 기판의 손상을 제거하기 위하여 실리콘 산화 공정을 수차례 진행하였던 종래 기술과 달리, 본 발명에 있어서는 1회의 수소 어닐링 처리로써 실리콘 기판의 손상을 제거할 수 있으며, 실리콘 기판의 손실이 없으므로 소자 분리 영역의 임계치수를 줄일 수 있다.Unlike the prior art, in which the silicon oxidation process is performed several times to remove the damage of the silicon substrate during the etching process for forming the trench for device isolation, in the present invention, the damage of the silicon substrate can be removed by one hydrogen annealing treatment. Therefore, since there is no loss of the silicon substrate, the critical dimension of the device isolation region can be reduced.
또한, 본 발명에 있어서는 초기 고온 열처리에 의해 실리콘 기판내의 산소 석출물(PRECIPITATE)의 분포를 함께 조절하여 고유 결함 제거(INTRINSIC GETTERING) 효과를 얻을 수 있으며, 침식 영역(DENUDED ZONE) 형성에도 기여할 수 있다.In addition, in the present invention, the distribution of oxygen precipitates (PRECIPITATE) in the silicon substrate may be controlled together by the initial high temperature heat treatment to obtain the INTRINSIC GETTERING effect, and may also contribute to the formation of DENUDED ZONE.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010036633A KR20030000596A (en) | 2001-06-26 | 2001-06-26 | Method for fabricating semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010036633A KR20030000596A (en) | 2001-06-26 | 2001-06-26 | Method for fabricating semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR20030000596A true KR20030000596A (en) | 2003-01-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010036633A KR20030000596A (en) | 2001-06-26 | 2001-06-26 | Method for fabricating semiconductor device |
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| Country | Link |
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| KR (1) | KR20030000596A (en) |
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2001
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