KR200252001Y1 - Up / down switching counter - Google Patents

Abstract

The present invention is to make the existing down counter and up counter circuit separately and configure them as a single counter so that they can be automatically switched by applying a control signal from the outside. Up / down operation of any one of the positive logic signal and the negative logic signal among the output signals of the first JK flip-flop that receives a clock having an arbitrary frequency band and is inputted as a synchronization signal and outputs data in a falling edge state. A first signal selector selectively outputting the mode; Among the output signals of the second JK flip-flop that receives the signal output from the first signal selector to two data input terminals JK, receives a clock having an arbitrary frequency band as a synchronization signal, and outputs data in a falling edge state. A second signal selector configured to selectively output one of a logic signal and a negative logic signal according to an up / down operation mode and a first control signal; And among the output signals of the third JK flip-flop which receives the signal output from the second signal selector to two data input terminals JK, receives a clock having an arbitrary frequency band as a synchronization signal, and outputs data in a falling edge state. And a third signal selector configured to selectively output one of a positive logic signal and a negative logic signal according to an up / down operation mode, a first control signal, and a second control signal to provide a data input of a fourth flip-flop. .

Description

Up / down switching counter

The present invention relates to a counter. In particular, the conventional down counter and up counter circuit, which are used separately, are composed of one counter and an up / down switching counter that can be automatically switched by applying a control signal from the outside. It is about.

In general, when configuring an up counter or a down counter, one flip-flop and an end gate are configured for each bit. An example of the up counter or the down counter is as follows.

1 is a configuration example of an up counter using a JK flip-flop. A predetermined positive voltage (VCC) is input to two data input terminals, JK, and a clock CLK having an arbitrary frequency band is input as a synchronous signal. A first AND gate AND1 that receives a first JK flip-flop JK1 for outputting data in a state and an output signal of the clock CLK and the first JK flip-flop JK1 and performs an AND operation on the output signal. And a second JK flip-flop that receives the positive voltage VCC to two data input terminals JK, receives an output signal of the first AND gate AND1 as a synchronization signal, and outputs data in a falling edge state. JK2, a second AND gate AND2 for receiving the output signals of the clock CLK, the first JK flip-flop JK1 and the second JK flip-flop JK2, and performing an AND operation on the JK2 output signal; The positive voltage VCC is input to two data input terminals JK and the 2 receives the output signal of the AND gate (AND2) to the synchronizing signal consists of a first JK flip-prop 3 (JK3) for outputting data on the falling edge state.

Briefly referring to the operation of the conventional up-counter configured as described above, the j and k inputs are kept high so that the first JK flip-flop JK1 is toggled at the negative of the clock.

Accordingly, the mand gate is used to control the second JK flip-flop JK2 every second clock and also the third JK flip-flop JK3 every fourth clock.

At this time, the clock CLK is directly applied to the first JK flip-flop JK1, and the first JK flip-flop JK1 reacts at the negative transition of the clock input and is toggled when the j and k inputs are high. Change state at negative clock transition.

This problem does not occur in the operation of the counter itself, but if the up and down counters are needed simultaneously in the same circuit, the necessary down counter and up counter must be configured separately. Therefore, the same circuit is added to increase the number of gates. Occurred.

The purpose of the present invention for solving the above problems is that the up / down counter circuit, which has been used separately, is composed of one counter and up / down that can be automatically switched by applying a control signal from the outside. To provide a down conversion counter.

A feature of the present invention for achieving the above object is a counter having a plurality of JK flip-flops, a predetermined positive voltage is input to the two data input terminal JK and a clock having an arbitrary frequency band as a synchronization signal A first signal selector for selectively outputting any one of a positive logic signal and a negative logic signal among the output signals of the first JK flip-flop that receives and outputs data in a falling edge state according to an up / down operation mode; Among the output signals of the second JK flip-flop that receives the signal output from the first signal selector to two data input terminals JK, receives a clock having an arbitrary frequency band as a synchronization signal, and outputs data in a falling edge state. A second signal selector configured to selectively output one of a logic signal and a negative logic signal according to an up / down operation mode and a first control signal; And among the output signals of the third JK flip-flop which receives the signal output from the second signal selector to two data input terminals JK, receives a clock having an arbitrary frequency band as a synchronization signal, and outputs data in a falling edge state. And a third signal selector configured to selectively output one of a positive logic signal and a negative logic signal according to an up / down operation mode, a first control signal, and a second control signal, and provide the signal to a data input of a fourth flip-flop. There is.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is an exemplary configuration diagram of an up / down switching counter according to the present invention, and a predetermined positive voltage VCC is input to two data input terminals JK, and a clock CLK having an arbitrary frequency band is input as a synchronization signal. Receives the first JK flip-flop JF1 for outputting data in the falling edge state, the signal output from the positive logic output terminal A of the first JK flip-flop JF1, and the up counting control signal CU. A first AND gate A1 output by performing an AND operation and a negative logic output terminal of the first JK flip-flop JF1. The second AND gate A2 and the output signal of the first AND gate A1 and the second AND gate A2 that receive the OR signal and the down counting control signal CD outputted from the logical AND operation Receives the first OR gate O1 and the OR signal and outputs the output signal of the first OR gate O1 to two data input terminals JK, and receives the clock CLK as a synchronization signal. The second JK flip-flop JF2 outputting data in the falling edge state, the signal output from the positive logic output terminal B of the second JK flip-flop JF2, the up counting control signal CU, and the first control. A third AND gate A3 for receiving the signal AS and performing an AND operation and outputting the negative logic output terminal of the second JK flip-flop JF2. The signal output from the down counting control signal (CD) and the inverted signal of the first control signal And a second OR for receiving the output signal of the fourth AND gate A4 for outputting the logical AND operation and the third AND gate A3 and the fourth AND gate A4. A third JK flip for inputting the output signal of the gate O2 and the second ora gate O2 to two data input terminals JK, and receiving the clock CLK as a synchronization signal and outputting data in a falling edge state; The signal output from the prop JF3 and the positive logic output terminal C of the third JK flip prop JF3, the up counting control signal CU, the first control signal AS, and the second control signal BS. And the negative logic output terminal of the fifth AND gate A5 and the third JK flip-flop JF3. The signal output from the down counting control signal (CD) and the inverted signal of the first control signal And an inverted signal of the second control signal. And a third OR for receiving the output signal of the sixth AND gate A6 and the OR signal A6 and the sixth AND gate A6. A fourth JK flip for inputting an output signal of the gate O3 and the third ora gate O3 to two data input terminals JK, and receiving the clock CLK as a synchronization signal and outputting data in a falling edge state; It consists of props JF4.

Looking at the preferred operation example of the up / down switching counter according to the present invention configured as described above are as follows.

First, given the gist of the present invention, when both an up counter and a down counter are required in one circuit, an up / down switching counter is provided by adding one or more gates for each bit to the existing counter. .

At this time, the first control signal A is required for the state change every time the clock CLK is operated, and the first flip-flop JF1 is maintained at the high state at both input terminals.

Further, when the count increasing mode, that is, the down counting control signal CD is low and the up counter control signal CU is high, the second control signal B is the first control signal A is high and the clock ( Each time CLK) goes low, the state changes.

The first AND gate A1 outputs a high signal when both the signal output from the positive logic output terminal A of the first JK flip-flop JF1 and the up counting control signal CU are high.

Therefore, the signal applied to the two input terminals of the second JK flip-flop JF2 becomes high whenever the count is increased and the signal output from the positive logic output terminal A of the first JK flip-flop JF1 is high. .

This operation is the same as the operation of the conventional up counter.

However, when the first JK flip-flop (JF1) to the second JK flip-flop (JF2) or the third JK flip-flop (JF3) to the fourth JK flip-flop (JF4) in the count increment form When the first control signal A is in a high state, the negative clock transition toggles the second control signal B.

In the count reduction mode, the second control signal B changes state whenever the first control signal A is high and the clock is operated low.

Accordingly, in the count down mode, the second control signal B changes its state as if it is operating from 0 to 15 or 14 to 13 whenever the first control signal A is high and the clock is low. It will function as a counter.

Therefore, by providing an up / down switching counter according to the present invention operating as described above, it is possible to reduce the number of gates of a circuit by solving it with one counter without separately configuring a counter in a circuit requiring two counter methods. Works.

1 is a diagram illustrating a configuration of a conventional general counter

2 is an exemplary configuration diagram of an up / down switching counter according to the present invention.

Claims (6)

A counter having a plurality of JK flip flops, Among the positive and negative logic signals among the output signals of the first JK flip-flop which inputs a predetermined positive voltage to two data input terminals JK, receives a clock having an arbitrary frequency band as a synchronization signal, and outputs data in a falling edge state. A first signal selector for selectively outputting any one signal according to an up / down operation mode; Among the output signals of the second JK flip-flop that receives the signal output from the first signal selector to two data input terminals JK, receives a clock having an arbitrary frequency band as a synchronization signal, and outputs data in a falling edge state. A second signal selector configured to selectively output one of a logic signal and a negative logic signal according to an up / down operation mode and a first control signal; And Among the output signals of the third JK flip-flop that receives the signal output from the second signal selector to two data input terminals JK, receives a clock having an arbitrary frequency band as a synchronization signal, and outputs data in a falling edge state. And a third signal selector for selectively outputting any one of a logic signal and a negative logic signal according to an up / down operation mode, a first control signal, and a second control signal, and providing the signal to a data input of a fourth flip-flop. Up / down changeover counter characterized by. The method of claim 1, The first signal selector comprises: a first AND gate receiving a signal output from the positive logic output terminal of the first JK flip-flop and an up counting mode selection signal, and performing an AND operation on the signal; A second AND gate receiving a signal output from the negative logic output terminal of the first JK flip-flop and a down counting mode control signal and performing an AND operation to output the result; And And a first OR gate configured to receive an output signal of the first AND gate and the second AND gate and perform an OR operation. The method of claim 1, The second signal selector comprises: a third AND gate receiving a signal output from the positive logic output terminal of the second JK flip-flop, an up counting mode selection signal, and a first control signal and performing an AND operation to output the first control signal; A fourth AND gate receiving a signal output from the negative logic output terminal of the second JK flip-flop, a down counting mode selection signal, and an inverted signal of the first control signal, and performing an AND operation on the first control signal; And And a second OR gate receiving the output signals of the third and fourth AND gates and performing an OR operation. The method of claim 1, The third signal selector receives a signal output from the positive logic output terminal of the third JK flip-flop, an up counting mode selection signal, a first control signal, and a second control signal, and performs a logical AND operation to output the fifth AND gate. Wow; A sixth operation for receiving the signal output from the negative logic output terminal of the third JK flip-flop, the down counting mode selection signal, the inversion signal of the first control signal, and the inversion signal of the second control signal, and performing an AND operation to output the inverse signal; And gates; And An up / down switching counter comprising a third OR gate receiving the output signals of the fifth and sixth AND gates and performing an OR operation; The method according to any one of claims 1 to 4, The first control signal is required for a state change every time the clock is operated, and the first flip-flop is maintained in a high state at both input terminals. The method according to any one of claims 1 to 4, And the second control signal changes state whenever the first control signal is high and the clock is operated in the count increment mode.