JPS62176319A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To obtain a high speed AND logic with respect to plural input data by taking OR logic in a data input section of a slave flip-flop to an inverted output of plural master flip-flops. CONSTITUTION:An input data desired to obtain an AND logic output finally is fed respectively to data input terminals D1, D2 of the 1st and 2nd master flip-flops. The inverted output of the two master flip-flops is inputted to date input transistors (TRs) Q13, Q14 of the slave flip-flop respectively, where the OR logic is executed. Since the TRs are connected in parallel simply and the number of fan-in has only to be increased with respect to the OR logic, no delay time is increased in this circuit part and an AND output of the data is obtained at the inverted output of the slave flip-flop.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a 79x70 circuit, and more particularly to a master-slave FID flip-flop circuit that operates at high speed with a relatively complex logic function as data input.

[Conventional technology]

The D-flip 70-tube circuit, which is a type of 7-bit flip-flop circuit, is called a delay flip-flop, which temporarily holds data and outputs it after 1 bit time for stable operation, and is widely used in measurement circuits, synchronization circuits, etc. ing.

Although a six-pole circuit is conceivable as a basic circuit, FIG. 2 shows an example of a conventional circuit constructed from a current switching logic circuit (ECL), which is often employed when high-speed operation is required.

Here, transistors QCs-Qso are connected to the master flip-flop 9. Transistors Qsl to Qsa constitute a slave flip 70 block and a clock terminal CLK.

Data input terminals DI, D2. and an output terminal Z.

Now, when the level of the clock terminal CLK is low, the master 7 lip 70 is in the data reading state.
The slave flip-flop is in a data holding state. Next, when the level of the clock terminal CLK becomes high, the master flip-flop enters the data holding state and the slave flip-flop enters the data reading state.
changes appear.

The transistors Qz+-Qzt form a two-way AND circuit, and provide the AND logical output of the signals input to the data input terminals D1 and D2 as the data input of the master flexible flop. If AND logic is required in the current switching type logic circuit, it is necessary to add one gate due to the configuration of the vertical logic circuit.

These flip-flops have data input terminals DI, D2
The AND logic output of the signals input to the clock terminal CLK is used as the data input, and the reading and holding of data is alternately repeated depending on the level of the signal applied to the clock terminal CLK.The entire flip-flop circuit is a master-slave type. is formed.

Here, transistor Q2. The two-man power AND circuit formed by ~Qzn is an important element that determines the operating speed of the entire 7 lip-flop circuit. In other words, at operating frequencies near the limit, the AN inserted into the signal path of the data system
Since the delay time of the D circuit affects the characteristics, it is desirable to minimize the delay in this part.

On the other hand, if the logic required for data input is OR logic, it can be easily obtained without increasing delay time by connecting another transistor in parallel with the input transistor Qts of the master flip-flop. There may be cases where an AND circuit is required, but in that case it must be configured with an independent vertical logic circuit as shown in this figure, which increases the delay time in this part, and therefore reduces the maximum operating frequency. Deterioration of characteristics is inevitable.

[Problem that the invention seeks to solve]

In the above-mentioned conventional D flip-flop circuit, the AND logic of the signals input to the data input terminals is obtained by an independent AND circuit. The disadvantage was that the operating frequency was lowered. This performance deterioration has the greatest effect especially in the so-called toggle flip-flop operation in which feedback is applied directly from the output terminal of the flip-flop circuit to the data input terminal.

The purpose of the present invention is to solve this problem and to
It is an object of the present invention to provide a D71J double-flop circuit that does not deteriorate in performance in terms of operating speed even in flip-flop circuits that require logic, and can obtain almost the same performance as when there is no AND logic circuit.

[Means for solving problems]

The 7 flip-flop circuit of the present invention is composed of a plurality of master flip-flops 70 which are constructed by current switching type logic circuits and have data input terminals, and a slave flip-flop having an OR logic function at the input. The reverse phase outputs of the 7a blocks are respectively connected to the inputs of the slave 7 flip-flops, and the AND output of data is obtained from the reverse phase outputs of the slave flip flops 70.

〔Example〕

Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

Here, transistors Q, . ~QII constitutes a slave flip-flop, and the input data to finally obtain an AND logic output are applied to the data input terminals DI, D2 of the first and second master flip-flops, respectively. The clock terminal CLK is commonly connected to each of the 7 flip-flops, and the flip-flops 7 are master-slave as a whole.
It is configured to operate as a zero tube circuit.

Here, the anti-phase outputs of the first and second master 7 flip-flops are respectively input to the data input transistor Qllr Q10 of the slave flip-flop, where OR logic is performed. Regarding this OR logic, since the transistors are simply connected in parallel and the fan-in number is increased, it is considered that there is no increase in the delay time in this part.

In other words, in the conventional circuit, when the level of the clock terminal CLK is at a low level, that is, when the master 7 lip-flop is in a read state, a logic operation is performed using an AND logic circuit provided individually, with an increase in delay time. In contrast, in the present invention, when the master 7 flip-flop is in the read state, only the reverse phase output of the signal input to the data input terminals Di and D2 is obtained as the output of each master flip-flop, and then Clock terminal CLK
Slave flip 70 occurs when the level of
When the knob is in the reading state, press O in the data input part.
By using the R logic and extracting the output from the opposite phase of the input data, the AND logic of the signals input to the data input terminals DI and D2 is finally obtained. Logically, by using the fact that A − B = A + B, the level of the clock terminal CLK is set to a low level in the time axis direction.
Divide into two high-level steps and use high-speed OR logic to
A master-slave D flip-flop circuit that can perform ND logic at high speed has been obtained.

In the present invention, a master flip-flop is required every time one circuit is disconnected, but since an AND logic circuit is not required, the power consumption is the same compared to the conventional circuit, and the number of elements is only 3 transistors added. Well, it has little influence on the actual design.

〔Effect of the invention〕

As explained above, the present invention achieves high speed processing for a plurality of input data as a whole by performing OR logic at the data input section of a slave 7 lip-flop for the reverse phase outputs of a plurality of master 7 lip-flops. AND
It has the effect of creating a master-slave D-flip 70 block circuit that can obtain logic, and is useful in fields such as measuring equipment and electronic equipment that require high-speed flip-flop operation for input data that requires complex logic. The effect is great.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, and Fig. 2 is a circuit diagram of a conventional A
FIG. 2 is a circuit diagram of a master-slave flip-flow 21 with an ND logic gate. R1~R@, RIt1~R*s ””...Resistance, Q+
-Qt*, Qtx~Qss...Transistor% II~Is, I! 1-Its... Constant current source, vRl, vRl... Power supply, Dr r
D”...Data input terminal, CLK...
・Clock input terminal, Z...output terminal. Yu °−゛n・、

Claims (1)

[Claims] It is composed of a plurality of master flip-flops that are constructed of current switching type logic circuits and have data input terminals, and a slave flip-flop that has an OR logic function at the input.
The negative phase outputs of the plurality of master flip-flops are connected to the inputs of the slave flip-flops, respectively, and the AND output of the signals input to the data input terminals is obtained from the negative phase outputs of the slave flip-flops. Features a flip-flop circuit.