KR200202059Y1 - adhesive for bonding chip in fabrication of vari able chip-size applicable package - Google Patents
adhesive for bonding chip in fabrication of vari able chip-size applicable package Download PDFInfo
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- KR200202059Y1 KR200202059Y1 KR2019970033235U KR19970033235U KR200202059Y1 KR 200202059 Y1 KR200202059 Y1 KR 200202059Y1 KR 2019970033235 U KR2019970033235 U KR 2019970033235U KR 19970033235 U KR19970033235 U KR 19970033235U KR 200202059 Y1 KR200202059 Y1 KR 200202059Y1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
본 고안은 브이·씨·에이 패키지 제조를 위한 칩본딩에 사용되는 접착제에 관한 것으로서, 상기 접착제에 스페이서를 첨가하여 접착제의 접착후 두께를 일정크기 이상으로 유지하여 칩과 인너리드와의 콘택을 방지하는 한편, 칩과 인너리드 사이의 갭에 에폭시 몰드 콤파운드가 미충전되어 발생하는 패키지의 크랙을 방지할 수 있도록 한 것이다.The present invention relates to an adhesive used for chip bonding for manufacturing a V-C package, by adding a spacer to the adhesive to maintain a thickness after the adhesion of the adhesive to a certain size to prevent contact between the chip and the inner lead. Meanwhile, the epoxy mold compound is not filled in the gap between the chip and the inner lead to prevent cracking of the package.
이를 위해, 본 고안은 브이·씨·에이 패키지 제조를 위한 패키징시 다이패드(1)와 칩(2) 사이에 도포되어 칩(2)을 다이패드(1)에 고정시키게 되는 접착제(3)에 있어서; 상기 접착제(3)에 접착제(3)가 경화된 후의 두께를 소정의 두께로 관리할 수 있도록 하기 위한 스페이서가 첨가됨을 특징으로 하는 브이·씨·에이 패키지의 칩 본딩용 접착제가 제공된다.To this end, the present invention is applied to the adhesive (3) which is applied between the die pad (1) and the chip (2) in the packaging for manufacturing the V-C package to fix the chip (2) to the die pad (1) In; An adhesive for chip bonding of a V-C package is provided, wherein a spacer is added to the adhesive 3 so as to manage the thickness after the adhesive 3 is cured to a predetermined thickness.
Description
본 고안은 브이·씨·에이 패키지에 관한 것으로서, 더욱 상세하게는 브이·씨·에이 패키지 제조를 위한 칩 본딩에 사용되는 접착제에 관한 것이다.The present invention relates to a V-C package, and more particularly, to an adhesive used for chip bonding for manufacturing a V-C package.
일반적으로, 브이·씨·에이(VCA:Variable Chip-size Applicable) 패키지는 칩(2)에 형성되는 본딩패드 수가 이에 대응하는 인너리드(5)의 수를 넘지 않는 범위에서 도 1에 나타낸 바와 같이 칩 사이즈가 다이패드(1)보다 작거나, 혹은 도 2에 나타낸 바와 같이 인너리드(5) 내측 영역을 벗어날 정도로 크더라도 이에 구애받지 않고 하나의 리드 프레임을 이용하여 정상적으로 패키지 공정을 진행할 수 있도록 한 것이다.In general, a VCA (Variable Chip-size Applicable) package has a number of bonding pads formed in the chip 2, as shown in FIG. 1 within a range not exceeding the number of inner leads 5 corresponding thereto. Even if the chip size is smaller than the die pad 1 or large enough to escape the inner region of the inner lead 5 as shown in FIG. 2, the package process can be normally performed using a single lead frame. will be.
한편, 브이·씨·에이 패키지의 패키징 과정은 다음과 같다.On the other hand, the packaging process of V-C package is as follows.
먼저, 웨이퍼에 집적회로를 형성하는 FAB공정을 완료한 후, 웨이퍼 상에 만들어진 각 칩(2)을 서로 분리시키는 다이싱(Dicing)이 끝나면, 분리된 각 칩(2)을 리드 프레임(Lead Frame)에 안착시키게 된다.First, after completing the FAB process of forming the integrated circuit on the wafer, and after dicing dividing each chip 2 formed on the wafer from each other, the separated chips 2 are placed in a lead frame. Settled in).
이때, 칩(2)의 크기에 따라, 다이패드(1)(Die pad) 내에 안착시키거나, 상기 다이패드(1) 및 인너리드(5)에 동시에 안착시키는 칩 본딩(Chip Bonding)을 수행하게 된다.At this time, according to the size of the chip (2), to be mounted in the die pad (Die pad), or to perform the chip bonding (Chip Bonding) to be simultaneously seated on the die pad 1 and the inner lead (5) do.
즉, 칩(2)의 크기가 다이패드(1) 보다 작은 경우에는 다이패드(1) 내에 위치하지만, 상기 인너리드(5) 선단을 연결한 영역보다 클 경우에는 다이패드(1) 및 인너리드(5) 선단에 걸쳐져 안착된다.That is, when the size of the chip 2 is smaller than the die pad 1, the chip 2 is located in the die pad 1, but when the chip 2 is larger than the area where the tip of the inner lead 5 is connected, the die pad 1 and the inner lead are formed. (5) It rests across the tip.
이 때, 상기 인너리드(5)에는 절연부재가 부착되고, 상기 다이패드(1) 상부면에는 접착제(3)인 에폭시(Epoxy)가 도포되며, 접착제(3)를 리드프레임에 도포한 상태에서 칩(2)을 눌러서 본딩시킨 후, 일정한 열을 가해서 접착제(3)를 경화시키게 된다.In this case, an insulating member is attached to the inner lead 5, and an epoxy 3, an adhesive 3, is applied to the upper surface of the die pad 1, and the adhesive 3 is applied to the lead frame. After the chip 2 is pressed and bonded, constant heat is applied to cure the adhesive 3.
이어서, 칩(2) 상에 형성된 외부접속단자인 본딩 패드(Bonding pad)와 리드 프레임의 인너리드(5)(Inner Lead)를 전기적으로 접속시키는 와이어(6) 본딩(Wire Bonding)을 순차적으로 수행한 후, 상기 칩(2) 및 본딩된 와이어(6)를 감싸 보호하기 위한 몰딩(Molding)을 수행하게 된다.Subsequently, a wire bonding is performed in order to electrically connect the bonding pad, which is an external connection terminal formed on the chip 2, and the inner lead 5 of the lead frame. Afterwards, molding is performed to wrap and protect the chip 2 and the bonded wire 6.
또한, 몰딩을 수행한 후에는 리드 프레임의 타이 바(Tie Bar) 및 댐 바(Dam Bar)를 자르는 트리밍(Trimming) 및, 아웃터리드(7)를 소정의 형상으로 성형하는 포밍(Forming)을 차례로 수행하게 된다.In addition, after molding, trimming to cut the tie bar and the dam bar of the lead frame, and forming to form the outer 7 into a predetermined shape are performed in order. Will be performed.
트리밍 및 포밍 완료 후에는 최종적으로 솔더링(Soldering)을 실시하므로써 반도체소자 패키지 공정을 완료하게 된다.After trimming and forming, the soldering process is finally performed to complete the semiconductor device package process.
그러나, 이와 같은 브이·씨·에이 패키지 제조를 위한 패키징시, 칩 사이즈가 다이패드(1) 보다 작은 경우에는 문제가 되지 않지만, 도 2에 나타낸 바와 같이 칩(2)의 사이즈가 다이패드(1) 보다 큰 경우에는 칩 본딩 과정에서 다음과 같은 문제가 발생할 우려가 있다.However, there is no problem when the chip size is smaller than the die pad 1 in packaging for manufacturing such a V-C package. However, as shown in FIG. 2, the size of the chip 2 is the die pad 1. If larger than), the following problems may occur in the chip bonding process.
먼저, 브이·씨·에이 패키지의 조립를 위한 패키징시, 종래의 접착제(3)를 사용하여 칩 본딩을 할 경우, 경화된 후의 접착제(3) 두께인 BLT(Bond Line Thickness)(이하, "BLT"라고 한다.)가 약 6∼15㎛ 정도밖에 되지 않는다.First, when packaging for assembling the V-C package, when chip bonding using the conventional adhesive (3), BLT (Bond Line Thickness), which is the thickness of the adhesive (3) after curing (hereinafter referred to as "BLT") Is only about 6 to 15 µm.
따라서, 도 3에 나타낸 바와 같이 인너리드(5) 팁(Tip)에 벤트(bent)가 발생되거나, 칩(2)이 기운 경우에 칩(2)과 인너리드(5) 간의 접촉이 일어나게 되는 문제점이 있었다.Therefore, as shown in FIG. 3, when a bent is generated at the tip of the inner lead 5 or when the chip 2 is inclined, contact between the chip 2 and the inner lead 5 occurs. There was this.
또한, 상기한 바와 같이 접착제(3)의 BLT(Bond Line Thickness)가 약 6∼15㎛이므로 인해, 후공정에서 에폭시 몰드 콤파운드(4)를 이용하여 칩(2) 및 와이어(6)를 봉지하는 과정에서 칩(2)과 인너리드(5) 사이의 갭으로 에폭시 몰드 콤파운드(4)가 충진되지 못하는 문제점이 있었다.In addition, as described above, since the BLT (Bond Line Thickness) of the adhesive 3 is about 6 to 15 µm, the chip 2 and the wire 6 are encapsulated using the epoxy mold compound 4 in a later step. In the process, there is a problem in that the epoxy mold compound 4 is not filled in the gap between the chip 2 and the inner lead 5.
이는, 에폭시 몰드 콤파운드(4)를 구성하는 필러(filler)의 입자 크기가 20㎛ 수준이어서 약 6∼15㎛ 수준인 갭 사이로 들어갈 수가 없기 때문이다.This is because the particle size of the filler constituting the epoxy mold compound 4 is 20 mu m level so that it cannot enter between gaps of about 6 to 15 mu m level.
따라서, 이 경우에는 패키징 완료 후, 패키지 내부에 미충전으로 인한 빈공간(void)이 발생하게 되며, 이 빈공간으로의 수분 침투시 패키지에 크랙이 발생할 우려가 있는 등 많은 문제점이 있었다.Therefore, in this case, after the packaging is completed, voids are generated due to uncharged inside the package, and there are many problems such as a crack may occur in the package when moisture penetrates into the empty space.
본 고안은 상기한 제반 문제점을 해결하기 위한 것으로서, 본 고안은 브이·씨·에이 패키지 제조를 위한 칩 본딩에 사용되는 접착제에 일정 직경의 스페이서를 첨가하여 접착제의 접착후 두께를 일정크기 이상으로 유지하므로써 칩과 인너리드와의 콘택을 방지하는 한편, 칩과 인너리드 사이의 갭에 에폭시 몰드 콤파운드가 미충전되어 발생하는 패키지의 크랙을 방지할 수 있도록 한 브이·씨·에이 패키지의 칩 본딩용 접착제를 제공하는데 그 목적이 있다.The present invention is to solve the above problems, the present invention is to add a spacer of a certain diameter to the adhesive used for chip bonding for the manufacture of V, C, A package to maintain the thickness after the adhesion of the adhesive to a certain size or more This prevents chip-inner lead contact and prevents cracking of the package due to unfilled epoxy mold compound in the gap between chip and inner lead. The purpose is to provide.
도 1은 종래의 브이·씨·에이 패키지를 나타낸 것으로서, 스몰 칩이 적용된 경우를 나타낸 종단면도1 is a vertical cross-sectional view illustrating a conventional V-C package, in which a small chip is applied.
도 2는 종래의 브이·씨·에이 패키지를 나타낸 것으로서, 라지 칩이 적용된 경우를 나타낸 종단면도Fig. 2 is a vertical cross-sectional view showing a conventional V-C package, in which a large chip is applied.
도 3는 종래의 브이·씨·에이 패키징시 발생하는 문제점을 나타낸 종단면도Figure 3 is a longitudinal sectional view showing a problem occurring in the conventional V-C-A packaging
도 4는 본 고안에 따른 브이·씨·에이 패키지를 나타낸 종단면도Figure 4 is a longitudinal sectional view showing a V-C package according to the present invention
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
1:다이패드 2:칩1: diepad 2: chip
3:접착제 4:몰드 콤파운드3: Adhesive 4: Mold Compound
5:인너리드 6:와이어5: inner lead 6: wire
7:아웃터리드7: Outstanding
상기한 목적을 달성하기 위해, 본 고안은 브이·씨·에이 패키지 제조를 위한 패키징시 다이패드와 칩 사이에 도포되어 칩을 다이패드에 고정시키게 되는 접착제에 있어서; 상기 접착제에 접착제가 경화된 후의 두께를 소정의 두께로 관리할 수 있도록 하기 위한 스페이서가 첨가됨을 특징으로 하는 브이·씨·에이 패키지의 칩본딩용 접착제가 제공된다.In order to achieve the above object, the present invention is an adhesive that is applied between the die pad and the chip during packaging for manufacturing the V-C package to secure the chip to the die pad; An adhesive for chip bonding of a V-C package is provided, wherein a spacer is added to the adhesive to manage the thickness after the adhesive is cured to a predetermined thickness.
이하, 본 고안의 일실시예를 첨부도면 도 4를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 4는 본 고안에 따른 브이·씨·에이 패키지를 나타낸 종단면도로서, 본 고안은 브이·씨·에이 패키지 제조를 위한 패키징시 다이패드(1)와 칩(2) 사이에 도포되어 칩(2)을 다이패드(1)에 고정시키게 되는 접착제(3)에, 상기 접착제(3)가 경화된 후의 두께를 소정의 두께로 관리할 수 있도록 하기 위한 스페이서(Spacer)가 첨가되어 구성된다.4 is a longitudinal cross-sectional view showing a V-C package according to the present invention, the present invention is applied between the die pad (1) and the chip (2) during packaging for the manufacture of V-C package chip 2 ) Is added to the adhesive 3 to fix the die pad 1 to a spacer for managing the thickness after the adhesive 3 is cured to a predetermined thickness.
이 때, 상기 스페이서는 구형(ball)이며, 그 재질은 Al2O3, SiO2, K2O으로 이루어지며, 직경이 25∼50㎛가 되도록 제조된다.At this time, the spacer is a ball (ball), the material is made of Al 2 O 3 , SiO 2 , K 2 O, it is manufactured to have a diameter of 25 ~ 50㎛.
한편, 본 고안에서는 상기 접착제(3)에 스페이서를 첨가함과 더불어, 칩(2)과 와이어(6) 등의 봉지시 사용되는 에폭시 몰드 콤파운드(4)의 필러(도시는 생략함) 사이즈를 6㎛ 이하로하여 사용하도록 구성된다.On the other hand, in the present invention, while adding a spacer to the adhesive 3, the filler (not shown) size of the epoxy mold compound 4 used for encapsulation of the chip 2, the wire 6, etc. It is comprised so that it may use in less than micrometer.
이와 같이 구성된 본 고안의 작용은 다음과 같다.The operation of the present invention configured as described above is as follows.
브이·씨·에이 패키지의 경우 인너리드(5) 위쪽으로 칩(2)이 탑재되기 때문에 칩(2)과 인너리드(5)가 콘택될 가능성이 높다.In the case of the V-C package, since the chip 2 is mounted above the inner lead 5, the chip 2 and the inner lead 5 are likely to contact each other.
따라서, 다이 본딩시 인너리드(5)와 칩(2) 사이의 갭이 일정한 두께로 관리가 되어야 하며, 이를 위해서는 먼저 접착제(3)의 BLT가 관리가 되어야 한다.Therefore, the gap between the inner lead 5 and the chip 2 should be managed at a constant thickness during die bonding, and for this purpose, the BLT of the adhesive 3 should be managed first.
한편, 요구되는 BLT를 관리하기 위해서는 기존의 접착제(3)가 경화후에 유지해야할 요구 두께와 동일한 치수의 직경을 갖는 스페이서를 첨가하여 접착제(3)를 제조한 후, 이를 칩 본딩시에 적용하면 된다.Meanwhile, in order to manage the required BLT, the adhesive 3 may be manufactured by adding a spacer having a diameter equal to the required thickness of the existing adhesive 3 to be maintained after curing, and then applying the same during chip bonding. .
즉, 본 고안에서는 칩 본딩시 다이패드(1)에 도포되는 접착제(3)의 직경이 25∼50㎛가 되기 때문에 접착제(3)의 경화후, BLT는 약 30∼40㎛로 관리된다.That is, in the present invention, since the diameter of the adhesive 3 applied to the die pad 1 at the time of chip bonding becomes 25-50 μm, the BLT is managed at about 30-40 μm after curing of the adhesive 3.
이는, 칩 본딩재로 사용되는 접착제(3)를 다이패드(1)에 도포한 후, 칩(2)을 누르더라도 일정한 두께의 스페이서에 의해 더 이상 눌러지지 않기 때문이다.This is because, after applying the adhesive 3 used as the chip bonding material to the die pad 1, even if the chip 2 is pressed, it is no longer pressed by a spacer of a constant thickness.
이와 같이 접착제(3)의 BLT가 충분히 확보됨에 따라, 인너리드(5)의 벤트나, 칩(2)의 틸트가 발생하더라도 칩(2)이 인너리드(5) 팁과 접촉하는 현상을 방지할 수 있게 된다.As such, the BLT of the adhesive 3 is sufficiently secured to prevent the chip 2 from contacting the inner lead 5 tip even when the inner lead 5 is bent or the chip 2 is tilted. It becomes possible.
또한, 접착제(3)의 BLT가 약 30∼40㎛로 충분히 큰 사이즈로 확보됨과 동시에 에폭시 몰드 콤파운드(4)의 필러 입도가 6㎛ 이하로 관리됨에 따라, 인너리드(5)와 칩(2) 사이이 갭으로 에폭시 몰드 콤파운드(4)가 미충전되는 현상이 완전히 해소되며, 이에 따라 패키징 후, 패키지 내부에 빈공간이 생기는 현상을 방지할 수 있게 된다.In addition, as the BLT of the adhesive 3 is secured to a sufficiently large size of about 30 to 40 µm and the filler particle size of the epoxy mold compound 4 is managed to be 6 µm or less, the inner lead 5 and the chip 2 are maintained. The phenomenon in which the epoxy mold compound 4 is not filled with the gap is completely eliminated, and thus, after packaging, it is possible to prevent a phenomenon in which an empty space is generated inside the package.
즉, 패키지 내부에 미충전으로 인한 빈공간이 없어짐에 따라 상기 빈공간으로의 수분침투시 발생하던 패키지의 크랙을 방지하여 패키지의 신뢰성을 향상시킬수 있게 된다.That is, as the empty space due to uncharged inside the package disappears, it is possible to prevent the crack of the package generated when water penetrates into the empty space, thereby improving the reliability of the package.
이상에서와 같이, 본 고안은 칩 본딩용 접착제(3)에 스페이서를 첨가하여 접착제(3)의 접착후 두께를 일정크기 이상으로 유지하도록 하는 한 것이다.As described above, the present invention is to add a spacer to the adhesive for chip bonding 3 to maintain the thickness after the adhesion of the adhesive 3 more than a certain size.
이에 따라, 본 고안의 칩(2)과 인너리드(5)와의 콘택을 방지하는 한편, 칩(2)과 인너리드(5) 사이의 갭에 에폭시 몰드 콤파운드(4)가 미충전되어 발생하는 패키지의 크랙을 방지할 수 있도록 하므로써, 브이·씨·에이 패키지에 대한 신뢰성을 향상시킬 수 있게 된다This prevents contact between the chip 2 and the inner lead 5 of the present invention, while the epoxy mold compound 4 is not filled in the gap between the chip 2 and the inner lead 5. By preventing cracks, the reliability of VC-A packages can be improved.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970033235U KR200202059Y1 (en) | 1997-11-21 | 1997-11-21 | adhesive for bonding chip in fabrication of vari able chip-size applicable package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970033235U KR200202059Y1 (en) | 1997-11-21 | 1997-11-21 | adhesive for bonding chip in fabrication of vari able chip-size applicable package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990019838U KR19990019838U (en) | 1999-06-15 |
| KR200202059Y1 true KR200202059Y1 (en) | 2000-12-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019970033235U KR200202059Y1 (en) | 1997-11-21 | 1997-11-21 | adhesive for bonding chip in fabrication of vari able chip-size applicable package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR200202059Y1 (en) |
-
1997
- 1997-11-21 KR KR2019970033235U patent/KR200202059Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR19990019838U (en) | 1999-06-15 |
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