KR20020091391A - Ddp type semiconductor chip package - Google Patents

Abstract

PURPOSE: A DDP(Dual Die Package) type semiconductor chip package is provided to reduce thickness and size of the semiconductor package by using one lead frame. CONSTITUTION: The first bonding pad is formed on the first active face of the first semiconductor chip(11). The second bonding pad is formed on an edge of the second active face of the second semiconductor(13). The first semiconductor chip(11) and the second semiconductor chip(13) are mounted on an inner lead(21). The inner lead(21) and an outer lead are formed on a single LOC(Lead On Chip) type lead frame. A tip step portion is formed at an end portion of the inner lead(21). A non-conductive adhesion portion(41) is formed on a lower face of the inner lead(21) of the first semiconductor chip(11). A non-conductive adhesion portion is formed on an upper face of the inner lead(21) of the second semiconductor chip(13). The bonding pad of the first semiconductor chip(11) is connected with the tip step portion of the inner lead(21) by the first bonding wire. The bonding pad of the second semiconductor chip(13) is connected with an upper face of the inner lead(21) by the second bonding wire(33). The first and the second semiconductor chips(11,13), the inner lead(21), the first boding wire, and the second boding wire(33) are protected by a package body(51).

Description

DDP type semiconductor chip package {DDP TYPE SEMICONDUCTOR CHIP PACKAGE}

The present invention relates to a semiconductor chip package, and more particularly, to a DDP type semiconductor chip package in which two semiconductor chips are mounted in a single lead frame and configured as one unit package.

With the recent development of the semiconductor industry and the demands of users, electronic devices are increasingly required to be smaller and lighter. One of the technologies applied to satisfy such a demand is a multi chip packaging technology. Multi-chip packaging technology is a technology that constitutes a package of a plurality of semiconductor chips, using a multi-chip package with this technology is smaller, lighter and more effective than using multiple packages containing a single semiconductor chip It is advantageous.

Multi-chip packaging techniques include a method of stacking a plurality of semiconductor chips and arranging them in parallel. In the former case, since the semiconductor chip is laminated, the mounting area can be reduced. In the latter case, the structure is arranged in a plurality of semiconductor chips on a plane. Recently, a multi-chip package is applied to a package requiring miniaturization and light weight, and a stacking type of semiconductor chips is used. The multi-chip package in which two semiconductor chips are mounted in a lead frame among the stacked multi-chip packages is called a DDP-type semiconductor chip package.

1 is a cross-sectional view illustrating an example of a dual die package (DDP) type semiconductor chip package according to the prior art.

Referring to FIG. 1, the DDP type semiconductor chip package 210 includes two semiconductor chips 211 and 213 in which bonding pads 212 and 214 are disposed in a central portion of an active surface on which an integrated circuit is formed. The first semiconductor chip 213 located in the upper portion is bent under the upwardly bent portion of the upper inner lead 221a, and the second semiconductor chip 211 located in the lower portion is bent downward in the lower inner lead 221b. It is attached to the lower part of the part by adhesive means 241 and 243, such as adhesive tape, respectively. The semiconductor chips 211 and 213 are positioned between the upper inner lead 221a and the lower inner lead 221b, and the respective bonding pads 212 and 214 are positioned between the facing inner leads 221a and 221b. Each of the semiconductor chips 211 and 213 is electrically bonded by bonding the bonding pads 212 and 214 to the inner leads 221a and 221b to which the semiconductor chips 211 and 213 are attached to the internal leads 231 and 233b. have. The electrical connection is protected from the external environment by the package body 251 encapsulating the semiconductor chips 211 and 213, the bonding wires 231 and 233, and the inner leads 221a and 221b. At this time, the upper inner lead 221a and the lower inner lead 221b are attached to each other and electrically connected to each other. Among the outer leads, the lower outer lead is cut and the upper outer lead 223a is bent in a form suitable for mounting. It is.

2 is a cross-sectional view showing another example of a DDP type semiconductor chip package according to the prior art.

Referring to FIG. 2, the DDP type semiconductor chip package 310 has a structure in which the first semiconductor chip 313 and the second semiconductor chip 311 are attached to the upper and lower surfaces of the die pad 324 by an adhesive. . Each of the semiconductor chips 311 and 313 has bonding pads 312 and 314 formed at edges of the active surface, and the active surfaces of the first semiconductor chip 313 and the second semiconductor chip 311 face opposite directions. Bonding pads 312 and 314 of the first semiconductor chip 313 and the second semiconductor chip 311 corresponding to the upper and lower surfaces of the inner lead 321 spaced apart from the die pad 324 by a predetermined interval are bonded wires ( 331,333). The semiconductor chips 311 and 313, the bonding wires 331 and 333, and the inner leads 321 are protected from the external environment by the package body 351, and the outer leads 323 formed integrally with the inner leads 321. It is bent to suit this mounting. Reference numeral 25 is a tie bar.

As described above, among the conventional DDP type semiconductor chip packages, the DDP type semiconductor chip package as shown in FIG. 1 is manufactured by using two LOC type lead frames, and thus the manufacturing cost is high, and the two lead frame junction interfaces are moisture absorption paths. It has a problem of deteriorating package reliability by generating delamination and package cracks due to moisture penetration.

In addition, although the DDP-type semiconductor chip package as shown in FIG. 2 is manufactured using one lead frame, the lead frame must have a die pad for attaching the semiconductor chip. Because it must be made in the manufacturing process and handling is difficult.

Accordingly, an object of the present invention is to provide a DDP type semiconductor chip package that can be manufactured using a single lead frame while reducing the thickness and size of the package and can be easily manufactured.

1 is a cross-sectional view showing an example of a dual die package (DDP) type semiconductor chip package according to the prior art;

2 is a cross-sectional view showing another example of a DDP type semiconductor chip package according to the prior art;

3 is a partial cutaway perspective view showing an embodiment of a DDP type semiconductor chip package according to the present invention;

4 is a cross-sectional view taken along the line A-A of FIG.

5 is an enlarged view of a portion “B” of FIG. 4;

6 is a cross-sectional view showing another embodiment of a DDP type semiconductor chip package according to the present invention.

Explanation of symbols on the main parts of the drawings

10,110; DDP-type semiconductor chip package

11,13,111,113; Semiconductor chips 12,14,112,114; Bonding pad

21,121; Internal lead 22; Internal lead tip step

23,123; Outer lead 25,125; Tie bar

31,33,131,133; Bonding wires 41,43,141,143; Adhesive means

51,151; Package body

DDP semiconductor chip package according to the present invention for achieving the above object, a single LOC type lead frame having a plurality of inner leads and outer leads formed integrally therewith, and attached to the lower surface of the inner lead and bonded to the center A first semiconductor chip having a pad formed thereon, a second semiconductor chip attached to an upper surface of the inner lead and a bonding pad formed thereon, and a first bonding wire bonded to a bonding pad of the first semiconductor chip and an upper end surface of the inner lead corresponding thereto; And a second bonding wire bonded to the bonding pad of the second semiconductor chip and the upper surface of the inner lead corresponding to the second semiconductor chip, the first semiconductor chip, the second semiconductor chip, the first and second bonding wires, and the inner lead. It characterized in that it comprises a package body.

The second semiconductor chip may be attached by an adhesive means having a predetermined thickness not in contact with the first bonding wire, or the inner lead tip stepped portion may be formed at a predetermined depth from an upper surface at an end portion at which the inner leads are wire bonded. It is desirable to ensure that no damage occurs. On the other hand, it is preferable that the inner lead has a structural stability by allowing the inner end portion to be down-set.

Hereinafter, a DDP type semiconductor chip package using a single lead frame according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a partial cutaway perspective view showing an embodiment of a DDP type semiconductor chip package according to the present invention, FIG. 4 is a cross-sectional view taken along line AA of FIG. 3, and FIG. 5 is an enlarged view of part “B” of FIG. 4. .

3 to 5, the DDP type semiconductor chip package 10 according to the present invention shown in FIG. 3 includes the first semiconductor chip 11 and the active surface of which the bonding pad 12 is formed at the center of the active surface. It has the 2nd semiconductor chip 13 in which the bonding pad 14 was formed in the edge. In addition, a single LOC type lead frame including an inner lead 21 on which the first semiconductor chip 11 and the second semiconductor chip 13 are mounted and an outer lead 23 formed integrally therewith is used. The inner lead 21 is down-set with the inner part bent downward, and the inner lead tip step portion 22 is formed at a predetermined depth from the upper surface at the inner lead end portion.

The first semiconductor chip 11 is attached to the lower surface of the down-set inner lead 21 with non-conductive adhesive means 41, such as adhesive tape. The active surface of the first semiconductor chip 11 is used for attachment, and the bonding pad 12 is positioned between the inner leads 21 facing each other. The second semiconductor chip 13 is attached to the top surface of the down-set inner lead 21 by non-conductive adhesive means 43. The lower surface corresponding to the active surface of the second semiconductor chip 13 is used for attachment.

The bonding pad 12 of the first semiconductor chip 11 is wire-bonded with the first bonding wire 31 and electrically connected to the inner lead tip step portion 22 of the upper end of the inner lead 21 corresponding thereto. The bonding pad 14 of the second semiconductor chip 13 is wire-bonded and electrically connected to the upper surface of the up-set portion of the inner lead 21 by the second bonding wire 33. The first bonding wire 31 adjusts the thickness of the adhesive means 43 used to attach the second semiconductor chip 13 to secure the height of the wire loop of the first bonding wire 31 so that the second bonding chip 43 is secured. It is not in contact with the semiconductor chip 13. In particular, the height of the wire loop can be properly maintained by the inner lead tip step portion 22. The wire bonding is first performed first with respect to the first semiconductor chip 11 and secondly after mounting of the second semiconductor chip 13.

The first semiconductor chip 11, the second semiconductor chip 13, the inner lead 21, and the bonding wires 31 and 33 are protected from the external environment by the package body 51 formed of an epoxy molding resin. The outer lead 23 protruding to the outside of the package body 51 integrally with the inner lead 21 is molded in a form suitable for mounting.

This DDP type semiconductor chip package has the characteristics of a lead on chip (LOC) type for the semiconductor chips below the inner leads and a chip on lead (COL) type characteristic for the semiconductor chips above the inner leads. Such a DDP type semiconductor chip package can include two semiconductor chips without a separate die pad by using a single LOC type lead frame. The use of LOC type leadframes increases the footprint of semiconductor chips over packages. In addition, wire bonding may proceed in the same direction, thereby facilitating the progress and handling of the process.

On the other hand, the DDP type semiconductor chip package according to the present invention is not limited to the above-described embodiment may be variously modified within the scope not departing from the technical spirit of the present invention. For example, although the inner leads are down-set in the above-described embodiment, the inner leads may be kept horizontal or processed in an up-set type as necessary. In addition, although the bonding pad is formed at the edge of the second semiconductor chip, a semiconductor chip having a bonding pad in the center may be applied. The DDP type semiconductor chip package to which this is applied is shown in FIG. 6. 6 is a cross-sectional view showing another embodiment of the DDP type semiconductor chip package according to the present invention. In the DDP type semiconductor chip package 110, the second semiconductor chip 113 has a bonding pad 114 formed at the center thereof. The structure other than the structure in which the upper surface of the inner lead 121 is wire bonded is the same as in the above-described embodiment. The length of the second bonding wire 133 that connects the second semiconductor chip 113 and the inner lead 121 is long.

According to the DDP-type semiconductor chip package according to the present invention as described above, since the same process is repeatedly applied using a single LOC type lead frame, it can significantly contribute to productivity and cost reduction.

Claims (4)

A single LOC type lead frame having a plurality of inner leads and outer leads integrally formed thereon, a first semiconductor chip attached to a lower surface of the inner lead and having a bonding pad formed at the center thereof, and attached to an upper surface of the inner lead; A second semiconductor chip having a bonding pad formed at an edge thereof, a first bonding wire bonded to the bonding pad of the first semiconductor chip and an upper surface of the inner lead end corresponding thereto, and a bonding pad of the second semiconductor chip, And a second bonding wire bonded to a corresponding upper surface of the inner lead, a package body encapsulating the first semiconductor chip, the second semiconductor chip, the first and second bonding wires, and the inner lead. DDP semiconductor chip package. The DDP type semiconductor chip package according to claim 1, wherein the inner leads have inner lead tip steps formed at a predetermined depth from an upper surface of a wire bonded end portion. The DDP type semiconductor chip package of claim 1, wherein the inner leads are down-set on an inner end thereof. The DDP type semiconductor chip package according to claim 1, wherein the second semiconductor chip is attached by an adhesive means having a predetermined thickness not in contact with the first bonding wire.