KR20020090250A - Socket structure for testing a semiconductor package by using a multiple line grid array - Google Patents

Abstract

PURPOSE: A socket structure for a semiconductor package test using a multi-line grid array is provided to produce a compact high-density test board used for testing semiconductor packages. CONSTITUTION: A socket structure for a semiconductor package test using a multi-line grid array(120) includes a multi-line grid and a socket(130). The multi-line grid has functional elements(124) and a plurality of electrodes penetrating the grid. The bottom of each of the electrodes is electrically connected to and supported by each input/output node of a test board(110). The socket accommodates a semiconductor package(134) and includes a plurality of connection pins(132) respectively corresponding to the electrodes. The top of each connection pin is electrically connected to each of solder balls(136) formed at the semiconductor package, and the bottom of each connection pin is electrically connected to each electrode of the multi-line grid.

Description

SOCKET STRUCTURE FOR TESTING A SEMICONDUCTOR PACKAGE BY USING A MULTIPLE LINE GRID ARRAY}

The present invention relates to a technique for testing a semiconductor package, and more particularly, to a socket structure for testing a semiconductor package using a multiple line grid array suitable for performing a test for determining the goodness of a ball grid array (BGA) package. .

As is well known, a conventional semiconductor package has a form in which one semiconductor chip is mounted (Single Chip Package) or at least two semiconductor chips (Multi Chip Package).

A ball grid array (BGA) is a common technique for the recent semiconductor package, and after manufacturing such a BGA package, a test process is finally performed.

7 is a cross-sectional view of a socket structure for a conventional semiconductor package test. The socket structure for a conventional test includes a test board 710 and a socket 720 electrically connected to each other through a bump 716. At various positions on the test board 710, various functional elements 712a and 712b are mounted to stabilize the system and improve electrical characteristics, and each functional element 712a and 712b has corresponding electrode wirings 714a and 714b. Is electrically connected to the bump 716 via < RTI ID = 0.0 > Here, the functional elements 712a and 712b may be, for example, capacitors, inductors, resistors or filters.

In addition, the socket 720 employed in the conventional test socket structure is connected to a structure (for example, a Y-shaped structure) in which the corresponding solder balls 726 formed on the semiconductor package 724 (that is, the BGA package) can be seated. Fins 722 are formed, and each of these connecting pins 722 has a shape that is electrically connected to each corresponding bump 716.

Accordingly, in the conventional test socket structure having the above-described structure, the solder balls 726 formed on the manufactured semiconductor package 724 are required to be seated on the corresponding connection pins 722 and electrically connected thereto. Test will be performed.

However, the conventional test socket structure as described above has a problem that the area of the test board becomes unnecessarily large because a functional element for stabilizing the system and improving the electrical characteristics is mounted on the test board. In addition, there is a problem that lowers the freedom of design of the test board, and this problem acts as a factor that hinders the shortening and thinning of the product.

In addition, the conventional test socket structure is equipped with a functional element for the stabilization of the system and the improvement of the electrical characteristics on the test board, the length of the signal line is long, causing a delay in signal transmission or noise is inserted in the signal transmission process As a result, electrical deterioration was accompanied with a fundamental limitation that the reliability of the test was deteriorated.

Accordingly, the present invention is to solve the above-mentioned problems of the prior art, a semiconductor package test socket structure using a multiple line grid array capable of realizing high density and light weight of the test board for testing the semiconductor package. The purpose is to provide.

Another object of the present invention is to provide a socket structure for testing a semiconductor package using a multiple line grid array which can increase the test reliability of the semiconductor package by suppressing an increase in the length of the electrode wiring for connection with the functional element.

In accordance with one aspect of the present invention, there is provided a socket structure for testing a semiconductor package, which can be used in equipment having a test board for testing the quality of a manufactured semiconductor package. A multiple line grid having a plurality of electrode wirings formed therebetween, the lower lines of each electrode wiring being electrically connected to and supported by respective corresponding input / output nodes in the test board; And a structure capable of accommodating the semiconductor package, wherein a plurality of connection pins respectively corresponding to the plurality of electrode wirings are formed, and an upper portion of each of the connection pins is in electrical contact with each of the corresponding solder balls formed in the semiconductor package. It provides a socket structure for a semiconductor package test using a multiple line grid array having a socket having a lower portion each of which is electrically connected to each of the corresponding electrode wiring in the multiple line grid.

In accordance with another aspect of the present invention, there is provided a socket structure for testing a semiconductor package that can be used in a device having a test board for testing the quality of a manufactured semiconductor package. A plurality of electrode wirings, the multiple line grids having lower portions of the electrode wirings electrically connected and supported to respective corresponding input / output nodes in the test board; A structure capable of accommodating the semiconductor package, wherein a plurality of connection pins respectively corresponding to the plurality of electrode wirings are formed, and an upper portion of each of the connection pins is in electrical contact with each of the corresponding solder balls formed in the semiconductor package. A socket having a lower portion electrically connected to a corresponding electrode wiring in the multiple line grid; And a socket structure for testing a semiconductor package using a multiple line grid array including at least one functional element mounted in a form electrically connected to a corresponding electrode wiring at a predetermined outer portion of the multiple line grid.

In accordance with another aspect of the present invention, there is provided a socket structure for testing a semiconductor package that can be used in a device having a test board for testing the quality of a manufactured semiconductor package. A plurality of electrode wirings are formed, a lower line of each of the electrode wirings is electrically connected to and supported by each corresponding input / output node in the test board, and at least one cavity in which at least one cavity for accommodating functional elements is formed in an outer predetermined portion grid; A structure capable of accommodating the semiconductor package, wherein a plurality of connection pins respectively corresponding to the plurality of electrode wirings are formed, and an upper portion of each of the connection pins is in electrical contact with each of the corresponding solder balls formed in the semiconductor package. A socket having a lower portion electrically connected to a corresponding electrode wiring in the multiple line grid; And at least one functional element accommodated in the at least one cavity and electrically connected to a corresponding electrode wiring.

According to another aspect of the present invention, there is provided a socket structure for testing a semiconductor package, which can be used in equipment having a test board for testing the quality of a manufactured semiconductor package. A multiple line grid having a plurality of electrode wirings formed therebetween, the lower lines of each of the electrode wirings being electrically connected and supported to respective corresponding input / output nodes in the test board; A plurality of connection pins corresponding to each of the via holes are formed, and a lower portion of each of the connection pins is contacted or non-contacted with an upper portion of each electrode wiring by a pressure input, and an upper portion thereof contacts each corresponding solder ball formed in the semiconductor package. A pin guider having a structure; A package guider having a structure capable of accommodating the semiconductor package and fixedly supporting the pin guider at an upper position of the multiple line grid; And a plurality of package holders mounted at predetermined positions of the package guider and configured to support each solder ball formed in the semiconductor package to be in electrical contact with corresponding connection pins. Provide structure.

In accordance with another aspect of the present invention, there is provided a socket structure for testing a semiconductor package that can be used in a device having a test board for testing the quality of a manufactured semiconductor package. A multiple line grid having a plurality of electrode wirings, the lower lines of each of the electrode wirings being electrically connected and supported to respective corresponding input / output nodes in the test board; At least one functional element mounted in a form electrically connected to a corresponding electrode wiring at an outer predetermined portion of the multiple line grid; A plurality of connection pins corresponding to the respective electrode wirings are formed, and a lower portion of each of the connection pins is contacted or non-contacted with an upper portion of each electrode wiring by a pressure input, and an upper portion thereof is formed on each corresponding solder ball formed in the semiconductor package. A pin guider having a structure in contact; A package guider having a structure capable of accommodating the semiconductor package and fixedly supporting the pin guider at an upper position of the multiple line grid; And a plurality of package holders mounted at predetermined positions of the package guider and configured to support each solder ball formed in the semiconductor package so as to be in electrical contact with the corresponding connection pins. Provide structure.

According to another aspect of the present invention, there is provided a socket structure for testing a semiconductor package, which can be used in equipment having a test board for testing the quality of a manufactured semiconductor package. A plurality of electrode wirings are formed, a lower line of each of the electrode wirings is electrically connected to each of the corresponding input / output nodes in the test board, and at least one cavity is formed in the outer predetermined portion to accommodate the functional element. grid; At least one functional element mounted in a form accommodated in the at least one cavity and electrically connected to a corresponding electrode wiring; A plurality of connection pins corresponding to the respective electrode wirings are formed, and a lower portion of each of the connection pins is contacted or non-contacted with an upper portion of each electrode wiring by a pressure input, and an upper portion thereof is formed on each corresponding solder ball formed in the semiconductor package. A pin guider having a structure in contact; A package guider having a structure capable of accommodating the semiconductor package and fixedly supporting the pin guider at an upper position of the multiple line grid; And a plurality of package holders mounted at predetermined positions of the package guider and configured to support each solder ball formed in the semiconductor package so as to be in electrical contact with the corresponding connection pins. Provide structure.

1 is a cross-sectional view of a socket structure for testing a semiconductor package using a multiple line grid array according to a first embodiment of the present invention;

2 is a cross-sectional view of a socket structure for testing a semiconductor package using a multiple line grid array according to a second embodiment of the present invention;

3 is a cross-sectional view of a socket structure for testing a semiconductor package using a multiple line grid array according to a third embodiment of the present invention;

4 is a cross-sectional view of a socket structure for testing a semiconductor package using a multiple line grid array according to a fourth embodiment of the present invention;

5 is a cross-sectional view of a socket structure for testing a semiconductor package using a multiple line grid array according to a fifth embodiment of the present invention;

6 is a cross-sectional view of a socket structure for testing a semiconductor package using a multiple line grid array according to a sixth embodiment of the present invention;

7 is a cross-sectional view of a socket structure for testing a conventional semiconductor package.

<Description of the code | symbol about the principal part of drawing>

110, 402: test board 112: lower bump

120, 406: multiple line grid 122: upper bump

124, 406b: Functional element 126, 408: Via hole

128,406a: cavity 130: socket

132, 412: connecting pins 134, 420: semiconductor package

136, 422: solder ball 410: pin guider

414: Package Guider 416a, 416b: Package Holder

418a, 418b: set screw

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The core technical aspect of the present invention is different from the above-described prior art having a structure in which a functional element is mounted at an arbitrary position on a test board and connected to an electrical connection point (bump) of a test socket through electrode wiring extending outward. , Various types of multiple line grids (MLGs) proposed by the present inventors and disclosed in the Korean Patent Application No. 1997-15770, 2000-7640, 2000-25605, 2000-65176, ie, semiconductors accompanying high functionalization and high integration. By adopting a structure that connects the test board and the socket structurally and electrically by using a multiple line grid of a functional element built-in or a functional element external type that can cope with the miniaturization and miniaturization of the device. It is easy to achieve the purpose.

Example 1

1 is a cross-sectional view of a socket structure for testing a semiconductor package using a multiple line grid array according to a first embodiment of the present invention.

Referring to FIG. 1, the socket structure for testing a semiconductor package according to the present exemplary embodiment includes a structure in which the multiple line grid 120 and the socket 130 are sequentially mounted on the test board 110, that is, the lower bump 112. Input / output nodes (not shown) of the test board 110 and lower input / output contacts (not shown) of the multiple line grids 120 respectively are connected to each other, and the upper bumps 122 of the multiple line grids 120 are connected to each other. The upper input / output contact (not shown) and the lower contact of the corresponding connection pin 132 in the socket 130 are connected. Here, each of the lower bumps 112 and the corresponding upper bumps 122 are electrically connected through the corresponding respective via holes 126.

In this case, the functional device is not mounted on the test board 110, and the required functional device 124 is formed inside the multiple line grid 120. Thus, the desired functional device is inside the multiple line grid 120. The method and process for forming 124 is described in detail in patent application 2000-65176 proposed by the inventor and filed with the Korean Patent Office. Here, the functional element may be, for example, a capacitor, an inductor, a resistor or a filter.

Meanwhile, a plurality of connection pins 132 having a form extending from an inner side to an outer side thereof are formed at a lower side of the socket 130 employed in the socket structure for testing a semiconductor package according to the present embodiment, and each connection pin 132 is formed. ) Has a Y-shaped structure so that each of the corresponding solder balls 136 formed under the semiconductor package 134 (eg, BGA package) inserted into the socket 130 for testing can be stably seated.

In the socket structure for testing a semiconductor package according to the present embodiment having the structure as described above, when the semiconductor package 134 is seated, each solder ball 136-each connection pin 132-each upper bump 122-each via hole ( 126)-each lower bump 112-each input and output node (not shown) in the test board 110 is electrically connected, through this connection structure to test whether the semiconductor package 134 is good.

Therefore, in the socket structure for testing a semiconductor package according to the present embodiment, the functional element required at an arbitrary position on the test board is mounted as in the conventional socket structure described above, and the functional element is made by using the electrode wiring drawn out to the outside. Since there is no need to connect between the input and output contacts in the socket and the socket, it is possible to realize high density and light weight reduction of the test board, and to suppress the increase in the length of the electrode wiring for connection with the functional element, thereby reducing the test reliability of the semiconductor package. Can be greatly improved.

Example 2

2 is a cross-sectional view of a socket structure for testing a semiconductor package using a multiple line grid array according to a second exemplary embodiment of the present invention.

Referring to FIG. 2, the socket structure for testing a semiconductor package according to the present embodiment is different from the above-described embodiment 1 in that a multiple line grid is not embedded with a functional element, but all external components are described above. It is substantially the same as Example 1. Therefore, in order to avoid unnecessary overlapping description, the description here is abbreviate | omitted about the substantially same part.

That is, in the above-described Embodiment 1, a multiple line grid having a built-in functional element is used, whereas in the present embodiment, as illustrated in FIG. 2, one or more functional elements 124 are connected to the multiple line grid 120. Multiple line of functional device external type having a form mounted on the lower side of the multiple line grid 120 in the space formed between the multiple line grid 120 and the test board 110 by the outer side, that is, the lower bump 112 Use the grid.

In addition, in the present embodiment, as shown in FIG. 2 as an example, it has been described as mounting a functional element required on the lower side space of the multiple line grid 120, the present invention is necessarily limited thereto In some embodiments, the upper and lower parts of the multiple line grid 120 may be mounted, or the functional device may be mounted on both the upper and lower parts, if necessary.

Thus, unlike the first embodiment described above, the socket structure for testing a semiconductor package according to the present embodiment uses an external multiple-line grid, which is not a functional element embedded, but can substantially achieve the same results and effects.

Example 3

3 is a cross-sectional view of a socket structure for testing a semiconductor package using a multiple line grid array according to a third embodiment of the present invention.

Referring to FIG. 3, the socket structure for testing a semiconductor package according to the present embodiment is the same as in the above-described second embodiment in that a multiple line grid encloses a functional element, but the functional element to be enclosed is formed in the multiple line grid. It differs in that it is sheathed in the form accommodated in a cavity, and all other components are substantially the same as Example 2 mentioned above. Therefore, in order to avoid unnecessary overlapping description, the description here is abbreviate | omitted about the substantially same part.

That is, in the above-described Embodiment 2, the external functional element is formed on the lower portion of the multiple line grid on the space formed between the lower portion of the multiple line grid and the upper portion of the test board (or the space formed between the upper portion of the multiple line grid and the lower portion of the socket). Or an upper portion), in the present embodiment, as shown in FIG. 3, one or more cavities 128 are formed in a predetermined portion of the multiple line grid 120, and each cavity 128 is formed. ), The desired functional element 124 is mounted.

In addition, in the present embodiment, as shown in FIG. 3 as an example, it has been described as mounting a functional element required in the cavity formed in the lower portion of the multiple line grid 120, the present invention is not limited thereto. In other words, the cavity may be formed on the multiple line grid 120 to mount the functional device, or the cavity may be formed on both the top and the bottom of the multiple line grid 120 to mount the functional device.

Therefore, the socket structure for testing a semiconductor package according to the present embodiment can achieve substantially the same results and effects as in the above-described Embodiment 2, and forms a cavity for accommodating a functional element in a multiple line grid. Since the functional element is mounted in a cavity accommodated in the cavity, it is possible to obtain another effect that the socket structure for testing a semiconductor package can be made even thinner than in the above-described Embodiment 2.

Example 4

4 is a cross-sectional view of a socket structure for testing a semiconductor package using a multiple line grid array according to a fourth embodiment of the present invention.

Referring to FIG. 4, in the socket structure for testing a semiconductor package according to the present embodiment, a multiple line grid 406 and a pin guider 410 are sequentially formed on a test board 402, and the pin guider 410 is packaged. The guider 414 has a structure fixedly supported at an upper position of the multiple line grid 406.

At this time, the functional element 406a is formed in the multiple line grid 406, and a plurality of via holes 408, i.e., the input / output contacts of the semiconductor package 420 to be tested and corresponding to the predetermined portions, respectively. A plurality of via holes are formed to electrically connect each input / output node (not shown) in the test board 402, and a lower side of each via hole 408 filled with a conductive material is connected to the test board 402 through bumps 404. Are electrically connected to respective corresponding input / output nodes in the top and bottom sides, and the upper side is electrically connected to each corresponding connecting pin 412 formed in the pin guider 410. Such built-in functional elements may be, for example, capacitors, inductors, resistors or filters.

Thus, the socket structure for testing a semiconductor package according to the present embodiment does not need to mount any functional element on the test board 402 because the multiple line grid 406 accommodates the functional element.

Here, each of the connection pins 412 has a structure in which the respective contact pins 412 are in contact or non-contact with each corresponding via hole 408 by a push input, as shown in an enlarged portion in FIG. 4. The solder balls 422 formed on the lower portion of the semiconductor package 420 to be tested are electrically contacted with the upper portion of the upper surface of the solder package.

In addition, the package guider 414 is fixed by a plurality of fixing screws 418a and 418b to fix and support the pin guider 410 at an upper position of the multiple line grid 406, and at least a higher position than the pin guider 410. A predetermined portion of the plurality of package holders (416a, 416b), that is, a plurality for supporting each of the solder ball 422 of the semiconductor package 420 inserted for the test to be in electrical contact with the corresponding connection pins 412 The package holder of the is formed. Herein, the package holders 416a and 416b hold and hold the semiconductor package 420 when the semiconductor package 420 is pressed once, as in a conventional push button, and press the semiconductor package (when pressing again in the fixed holding state). And 420 to release the fixed support.

In the socket structure for testing a semiconductor package according to the present embodiment having the above-described structure, when the semiconductor package 420 is inserted, each solder ball 422-each connection pin 412-each via hole 408-each bump 404 Each input / output node (not shown) in the test board 402 is electrically connected to each other to test whether the semiconductor package 420 is good or not.

Therefore, the socket structure for testing a semiconductor package according to the present embodiment does not need to mount the functional elements required on the test board as in the above-described embodiments 1, 2, and 3, and thus the high density of the test board. In addition to the reduction in size and light weight, the test reliability of the semiconductor package can be greatly improved by suppressing the increase in the length of the electrode wiring for connection with the functional element.

Example 5

5 is a cross-sectional view of a socket structure for testing a semiconductor package using a multiple line grid array according to a fifth embodiment of the present invention.

Referring to FIG. 5, the socket structure for testing a semiconductor package according to the present embodiment is different from the above-described embodiment 4 in that the multiple line grid is not embedded with a functional element, but all other components are described above. It is substantially the same as Example 4. Therefore, in order to avoid unnecessary overlapping description, the description here is abbreviate | omitted about the substantially same part.

That is, in the above-described Embodiment 4, a multiple line grid having a built-in functional element is used, whereas in the present embodiment, as illustrated in FIG. 5, one or more functional elements 406a are connected to the multiple line grid 406. A functional element external multiple line grid having a form mounted on the lower side of the multiple line grid 406 in a space formed between the external line, that is, the bump 404 between the multiple line grid 406 and the test board 402. Use

In addition, in the present embodiment, as illustrated in FIG. 5 as an example, it has been described as mounting a functional element required on the lower side space of the multiple line grid 406, but the present invention is necessarily limited thereto. It is not necessary to mount the upper part of the multiple line grid 406 instead of the lower part, or the functional element may be mounted both on the upper part and the lower part if necessary.

Therefore, unlike the embodiment 4 described above, the socket structure for testing a semiconductor package according to the present exemplary embodiment uses an external multiple line grid, which is not a functional element embedded, but may substantially achieve the same results and effects.

Example 6

6 is a cross-sectional view of a socket structure for testing a semiconductor package using a multiple line grid array according to a sixth embodiment of the present invention.

Referring to FIG. 6, the socket structure for testing a semiconductor package according to the present embodiment is the same as that of the fifth embodiment in that a multiple line grid encloses a functional element, but the external functional element is formed on the multiple line grid. It differs in that it is sheathed in the form accommodated in a cavity, and all other components are substantially the same as Example 2 mentioned above. Therefore, in order to avoid unnecessary overlapping description, the description here is abbreviate | omitted about the substantially same part.

That is, in the above-described Embodiment 5, the bottom of the multiple line grid (the space formed between the bottom of the multiple line grid and the top of the multiple line grid and the bottom of the socket) is formed in the external functional element. Or an upper part), in the present embodiment, as shown in FIG. 6, one or a plurality of cavities 406a are formed in a predetermined portion of the multiple line grid 406, and the cavity 406a is provided. To a desired functional element 406b.

In addition, in the present embodiment, as illustrated in FIG. 6 as an example, the functional element required for mounting in the cavity formed under the multiple line grid 406 has been described, but the present invention is necessarily limited thereto. Although not necessarily, the functional device may be mounted by forming a cavity on the multiple line grid 406 or a cavity may be formed on both the upper and lower parts as necessary.

Therefore, the socket structure for testing a semiconductor package according to the present embodiment can achieve substantially the same results and effects as in the above-described embodiment 5, and forms a cavity for accommodating a functional element in a multiple line grid. Since the functional element is mounted in a cavity accommodated, it is possible to obtain another effect that a socket structure for a semiconductor package test can be manufactured even thinner than in the above-described fifth embodiment.

As described above, according to the present invention, in contrast to the above-described prior art which mounts a functional element connected to the required electrode wiring on an arbitrary position on the test board, the multiple lines are not mounted on the test board. By forming in a grid or embedded in a grid, it is possible to realize high density and light weight reduction of the test board, and to greatly increase the test reliability of the semiconductor package by suppressing an increase in the length of electrode wiring for connection with a functional element. Can be promoted.

Claims (21)

In the socket structure for testing a semiconductor package that can be used in equipment having a test board for testing the quality of the manufactured semiconductor package, A multiple line grid having a functional element embedded therein, wherein a plurality of electrode wirings are formed to penetrate between an upper portion and a lower portion, and a lower portion of each electrode wiring is electrically connected and supported to each corresponding input / output node in the test board; And A structure capable of accommodating the semiconductor package, wherein a plurality of connection pins respectively corresponding to the plurality of electrode wirings are formed, and an upper portion of each of the connection pins is in electrical contact with each of the corresponding solder balls formed in the semiconductor package. And a socket structure for testing a semiconductor package using a multiple line grid array, the bottom line having a socket electrically connected to each of the corresponding electrode wires in the multiple line grid. In the socket structure for testing a semiconductor package that can be used in equipment having a test board for testing the quality of the manufactured semiconductor package, A multiple line grid having a plurality of electrode wirings formed in a form penetrating between an upper portion and a lower portion, the lower lines of each electrode wiring being electrically connected to and supported by respective corresponding input / output nodes in the test board; The semiconductor package may have a structure capable of accommodating the semiconductor package, and a plurality of connection pins may be formed on the plurality of electrode wires, and an upper portion of each of the connection pins may be in electrical contact with each of the corresponding solder balls formed on the semiconductor package. A socket having a lower portion electrically connected to a corresponding electrode wiring in the multiple line grid; And A socket structure for testing a semiconductor package using a multiple line grid array comprising at least one functional element mounted in a form electrically connected to a corresponding electrode wiring at a predetermined outer portion of the multiple line grid. The socket structure of claim 2, wherein the functional device is positioned in a space formed between a lower portion of the multiple line grid and an upper portion of a test board. The socket structure of claim 2, wherein the functional device is positioned in a space formed between an upper portion of the multiple line grid and a lower portion of the socket. The multiplexing device of claim 2, wherein the functional device is positioned in a space formed between a lower portion of the multiple line grid and an upper portion of the test board, and a space formed between an upper portion of the multiple line grid and a lower portion of the socket. Socket structure for semiconductor package test using line grid array. In the socket structure for testing a semiconductor package that can be used in equipment having a test board for testing the quality of the manufactured semiconductor package, A plurality of electrode wirings are formed which penetrate between the upper and lower portions, the lower portion of each of the electrode wirings is electrically connected to each corresponding input / output node in the test board, and is capable of accommodating functional elements in an outer predetermined portion. A multiple line grid on which at least one cavity is formed; A structure capable of accommodating the semiconductor package, wherein a plurality of connection pins respectively corresponding to the plurality of electrode wirings are formed, and an upper portion of each of the connection pins is in electrical contact with each of the corresponding solder balls formed in the semiconductor package. A socket having a lower portion electrically connected to a corresponding electrode wiring in the multiple line grid; And A socket structure for testing a semiconductor package using a multiple line grid array comprising at least one functional element housed in the at least one cavity and electrically connected to a corresponding electrode wiring. 7. The socket structure of claim 6, wherein the cavity is formed under the multiple line grid. 7. The socket structure of claim 6, wherein the cavity is formed on the multiple line grid. 7. The socket structure of claim 6, wherein the cavity is formed above and below the multiple line grid, respectively. In the socket structure for testing a semiconductor package that can be used in equipment having a test board for testing the quality of the manufactured semiconductor package, A multiple line grid having a functional element embedded therein, wherein a plurality of electrode wirings are formed to penetrate between an upper portion and a lower portion, and a lower portion of each electrode wiring is electrically connected and supported to each corresponding input / output node in the test board; A plurality of connection pins corresponding to each of the via holes are formed, and a lower portion of each of the connection pins is contacted or non-contacted with an upper portion of each electrode wiring by a pressure input, and an upper portion thereof contacts each corresponding solder ball formed in the semiconductor package. A pin guider having a structure; A package guider having a structure capable of accommodating the semiconductor package and fixedly supporting the pin guider at an upper position of the multiple line grid; And Socket structure for testing a semiconductor package using a multiple line grid array which is mounted at a predetermined position of the package guider and comprises a plurality of package holders for supporting each solder ball formed in the semiconductor package so as to be in electrical contact with the corresponding connection pins. . The socket structure for testing a semiconductor package using a multiple line grid array according to claim 10, wherein the plurality of package holders fix or support the semiconductor package by a repetitive press-fit operation. In the socket structure for testing a semiconductor package that can be used in equipment having a test board for testing the quality of the manufactured semiconductor package, A multiple line grid having a plurality of electrode wirings formed in a form penetrating between an upper portion and a lower portion, the lower portion of each electrode wiring being electrically connected to and supported by each corresponding input / output node in the test board; At least one functional element mounted in a form electrically connected to a corresponding electrode wiring at an outer predetermined portion of the multiple line grid; A plurality of connection pins corresponding to the respective electrode wirings are formed, and a lower portion of each of the connection pins is contacted or non-contacted with an upper portion of each electrode wiring by a pressure input, and an upper portion thereof is formed on each corresponding solder ball formed in the semiconductor package. A pin guider having a structure in contact; A package guider having a structure capable of accommodating the semiconductor package and fixedly supporting the pin guider at an upper position of the multiple line grid; And A socket structure for testing a semiconductor package using a multiple line grid array, which is mounted at a predetermined position of the package guider and includes a plurality of package holders for supporting each solder ball formed in the semiconductor package to be in electrical contact with a corresponding connection pin. . The socket structure of claim 12, wherein the functional device is positioned in a space formed between a lower portion of the multiple line grid and an upper portion of a test board. The socket structure of claim 12, wherein the functional device is positioned in a space formed between an upper portion of the multiple line grid and a lower portion of the pin guider. The method of claim 12, wherein the functional element is located in the space formed between the bottom of the multiple line grid and the top of the test board and the space formed between the top of the multiple line grid and the bottom of the pin guider. Socket structure for semiconductor package test using multiple line grid array. The semiconductor package test according to any one of claims 12 to 15, wherein the plurality of package holders hold or release the semiconductor package by a repetitive press-fit operation. Socket structure. In the socket structure for testing a semiconductor package that can be used in equipment having a test board for testing the quality of the manufactured semiconductor package, A plurality of electrode wirings are formed which penetrate between the upper and lower portions, the lower portion of each of the electrode wirings is electrically connected to each corresponding input / output node in the test board, and is capable of accommodating functional elements in an outer predetermined portion. A multiple line grid on which at least one cavity is formed; At least one functional element mounted in a form accommodated in the at least one cavity and electrically connected to a corresponding electrode wiring; A plurality of connection pins corresponding to the respective electrode wirings are formed, and a lower portion of each of the connection pins is contacted or non-contacted with an upper portion of each electrode wiring by a pressure input, and an upper portion thereof is formed on each corresponding solder ball formed in the semiconductor package. A pin guider having a structure in contact; A package guider having a structure capable of accommodating the semiconductor package and fixedly supporting the pin guider at an upper position of the multiple line grid; And A socket structure for testing a semiconductor package using a multiple line grid array, which is mounted at a predetermined position of the package guider and includes a plurality of package holders for supporting each solder ball formed in the semiconductor package to be in electrical contact with a corresponding connection pin. . 18. The socket structure of claim 17, wherein the cavity is formed under the multiple line grid. 18. The socket structure of claim 17, wherein the cavity is formed on the multiple line grid. 18. The socket structure of claim 17, wherein the cavity is formed above and below the multiple line grid, respectively. 21. The semiconductor package test according to any one of claims 17 to 20, wherein the plurality of package holders hold or release the semiconductor package by a repetitive press-fit operation. Socket structure.